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nrhw20: io mux settings updated and cleaned up

This commit is contained in:
Rene Straub 2018-05-25 17:07:25 +02:00
parent 765e9dd5a7
commit 9c31a29136
1 changed files with 5 additions and 11 deletions
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16
board/nm/nrhw20/mux.c
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@ -32,7 +32,6 @@ static struct module_pin_mux gpio_pin_mux[] = {
* GPIO0_16: RST_PHY~ * GPIO0_16: RST_PHY~
* GPIO0_17: PMIC FAULT * GPIO0_17: PMIC FAULT
* GPIO0_27: RST_SHIELD~ * GPIO0_27: RST_SHIELD~
* GPIO0_31: GSM_WAKE
* *
* GPIO1_14: DIG_OUT * GPIO1_14: DIG_OUT
* GPIO1_15: DIG_IN * GPIO1_15: DIG_IN
@ -42,7 +41,6 @@ static struct module_pin_mux gpio_pin_mux[] = {
* GPIO1_26: WLAN_EN * GPIO1_26: WLAN_EN
* GPIO1_27: WLAN_IRQ * GPIO1_27: WLAN_IRQ
* *
* GPIO3_0: BUTTON
* GPIO3_4: PCIe_IO.WAKE * GPIO3_4: PCIe_IO.WAKE
* GPIO3_9: PCIe_IO.W_DIS * GPIO3_9: PCIe_IO.W_DIS
* GPIO3_10: PCIe_IO.RST * GPIO3_10: PCIe_IO.RST
@ -52,7 +50,6 @@ static struct module_pin_mux gpio_pin_mux[] = {
/* Bank 0 */ /* Bank 0 */
{OFFSET(spi0_sclk), (MODE(7) | PULLUDDIS)}, /* (A17) gpio0[2] */ /* RST_GNSS */ {OFFSET(spi0_sclk), (MODE(7) | PULLUDDIS)}, /* (A17) gpio0[2] */ /* RST_GNSS */
/* TODO: Wrong, circuit should use pull down instead of pull up */
{OFFSET(spi0_d0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (B17) gpio0[3] */ /* GEOFENCE_GNSS */ {OFFSET(spi0_d0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (B17) gpio0[3] */ /* GEOFENCE_GNSS */
{OFFSET(spi0_d1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (B16) gpio0[4] */ /* RTK_STAT_GNSS */ {OFFSET(spi0_d1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (B16) gpio0[4] */ /* RTK_STAT_GNSS */
{OFFSET(spi0_cs0), (MODE(7) | PULLUDEN | PULLDOWN_EN)}, /* (A16) gpio0[5] */ /* EXTINT_GNSS */ {OFFSET(spi0_cs0), (MODE(7) | PULLUDEN | PULLDOWN_EN)}, /* (A16) gpio0[5] */ /* EXTINT_GNSS */
@ -61,8 +58,6 @@ static struct module_pin_mux gpio_pin_mux[] = {
{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)}, /* (J18) gpio0[16] */ /* RST_PHY~ */ {OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)}, /* (J18) gpio0[16] */ /* RST_PHY~ */
{OFFSET(mii1_txd2), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (K15) gpio0[17] */ /* PMIC_FAULT */ {OFFSET(mii1_txd2), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (K15) gpio0[17] */ /* PMIC_FAULT */
{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)}, /* (U12) gpio0[27] */ /* RST_SHIELD~ */ {OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)}, /* (U12) gpio0[27] */ /* RST_SHIELD~ */
{OFFSET(gpmc_wpn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},/* (U17) gpio0[31] */ /* GSM_WAKE */
/* TODO: Check gpmc_wpn */
/* Bank 1 */ /* Bank 1 */
{OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)}, /* (V13) gpio1[14] */ /* DIG_OUT */ {OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)}, /* (V13) gpio1[14] */ /* DIG_OUT */
@ -90,7 +85,7 @@ static struct module_pin_mux gpio_pin_mux[] = {
#endif #endif
/* Bank 3 */ /* Bank 3 */
{OFFSET(mii1_col), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},/* (H16) gpio3[0] */ /* BUTTON */ {OFFSET(mii1_col), (MODE(7) | PULLUDEN | PULLUP_EN)}, /* (H16) gpio3[0] */ /* BUTTON */
{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},/* (J17) gpio3[4] */ /* PCIe_IO.WAKE */ {OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},/* (J17) gpio3[4] */ /* PCIe_IO.WAKE */
{OFFSET(mii1_txclk), (MODE(7) | PULLUDDIS)}, /* (K18) gpio3[9] */ /* PCIe_IO.W_DIS */ {OFFSET(mii1_txclk), (MODE(7) | PULLUDDIS)}, /* (K18) gpio3[9] */ /* PCIe_IO.W_DIS */
{OFFSET(mii1_rxclk), (MODE(7) | PULLUDDIS)}, /* (L18) gpio3[10] */ /* PCIe_IO.RST */ {OFFSET(mii1_rxclk), (MODE(7) | PULLUDDIS)}, /* (L18) gpio3[10] */ /* PCIe_IO.RST */
@ -160,10 +155,10 @@ static struct module_pin_mux mmc1_emmc_pin_mux[] = {
{-1}, {-1},
}; };
/* TODO: Check, configure as GPIO, instead of USB_DRVBUS */ /* USB_DRVBUS not used -> configure as GPIO */
static struct module_pin_mux usb_pin_mux[] = { static struct module_pin_mux usb_pin_mux[] = {
{OFFSET(usb0_drvvbus), (MODE(0) | PULLUDDIS)}, /* (F16) USB0_DRVVBUS */ {OFFSET(usb0_drvvbus), (MODE(7) | PULLUDDIS)}, /* (F16) USB0_DRVVBUS */
{OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS)}, /* (F15) USB1_DRVVBUS */ {OFFSET(usb1_drvvbus), (MODE(7) | PULLUDDIS)}, /* (F15) USB1_DRVVBUS */
{-1}, {-1},
}; };
@ -171,12 +166,11 @@ static struct module_pin_mux usb_pin_mux[] = {
static struct module_pin_mux uart0_pin_mux[] = { static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (E15) UART0_RXD */ {OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (E15) UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* (E16) UART0_TXD */ {OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* (E16) UART0_TXD */
/* TODO: Place same defaults for uart0_rts, uart_cts? */
{-1}, {-1},
}; };
/* UART0: Shield I/F (UART, CAN) */ /* UART0: Shield I/F (UART, CAN) */
/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */ /* Leave UART0 unconfigured because we want to configure it as needed by Linux (can/spi/uart/etc) */
/* Mode 7 = GPIO */ /* Mode 7 = GPIO */
static struct module_pin_mux uart0_disabled_pin_mux[] = { static struct module_pin_mux uart0_disabled_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (E15) GPIO1_10 */ {OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (E15) GPIO1_10 */