nbhw18: allow use of external serial port

board/nm/common/nbhw_env.c

@@ -18,9 +18,10 @@ void find_and_set_active_partition(void)
 
 void set_console(void)
 {
-#if defined(CONFIG_PRE_CONSOLE_BUFFER)
 	char buf[50] = "\0";
 	char *defaultconsole = env_get("defaultconsole");
+
+#if defined(CONFIG_PRE_CONSOLE_BUFFER)
 	int len = 0;
 
 	read_file_set_blk_dev("mmc", "0:3", FS_TYPE_EXT);
@@ -34,9 +35,9 @@ void set_console(void)
 		strncpy(buf, defaultconsole, sizeof(buf));
 	}
 	printf("consoledev: %s\n", buf);
-	env_set("consoledev", buf);
 #else
-	env_set("consoledev", "ttyS0");
+	strcpy(buf, defaultconsole);
 #endif
+	env_set("consoledev", buf);
 }
 

board/nm/common/nbhw_fpga_gpio.c

@@ -586,13 +586,15 @@ static int fpga_boot_buffer(const struct nbhw_fpga_priv *priv, const u8* data, i
 	u8* raw_bitstream;
 	int raw_num_bytes;
 
+printf("BITSTREAM IS COMPILED IN. CHECK SKIPPED.\n");
+#if 0
 	printf("Checking FPGA bitstream...\n");
 	raw_num_bytes = num_bytes;
 	if (fpga_check_bitstream(priv, data, &raw_bitstream, &raw_num_bytes)) {
 		printf("Not a valid FPGA image at 0x%p\n", data);
 		goto abort;
 	}
-
+#endif
 	/* Write bit stream */
 	switch (priv->fpga_type) {
 		case FPGA_LATTICE_SSPI :

board/nm/nbhw18_v2/board.c

@@ -3,7 +3,7 @@
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
-#define DEBUG
+#undef DEBUG
 #include <common.h>
 #include <i2c.h>
 #include <miiphy.h>
@@ -35,19 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
  * Those values and defines are taken from the Marvell U-Boot version
  * "u-boot-2013.01-2014_T3.0"
  */
-#ifdef NBHW18_V1
-
-#define GPP_OUT_ENA_LOW				(~(BIT(7) | BIT(19) | BIT(21))) /* 1=Input, default input */
-
-#define GPP_OUT_ENA_MID				(~(BIT(9) | BIT(12)))
-
-#define GPP_OUT_VAL_LOW				(BIT(21))
-#define GPP_OUT_VAL_MID				(BIT(9))
-#define GPP_POL_LOW	0x0
-#define GPP_POL_MID	0x0
-
-#else
-
 #define GPP_OUT_ENA_LOW				(~(BIT(6) | BIT(19) | BIT(29))) /* 1=Input, default input */
 
 #define GPP_OUT_ENA_MID				(~(BIT(12) | BIT(15)))
@@ -57,8 +44,6 @@ DECLARE_GLOBAL_DATA_PTR;
 #define GPP_POL_LOW	0x0
 #define GPP_POL_MID	0x0
 
-#endif
-
 #define BD_EEPROM_ADDR			(0x50)	/* CPU BD EEPROM (8kByte) is at 50 (A0) */
 #define BD_ADDRESS				(0x0000)  /* Board descriptor at beginning of EEPROM */
 #define PD_ADDRESS				(0x0200)  /* Product descriptor */
@@ -189,16 +174,6 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
 				if ((type >= SGMII0) && (type <= SGMII2)) {
 					board_serdes_map[i].serdes_speed = SERDES_SPEED_1_25_GBPS;
 					board_serdes_map[i].serdes_mode = SERDES_DEFAULT_MODE;
-#ifdef NBHW18_V1
-					if (i==1) {
-						/* Polarity of SERDES1 to switch extension seems
-						   to be inverted. Not sure, if the swapping happens 
-						   on the main board or the extension board??? */
-						board_serdes_map[i].swap_rx = 1;
-						board_serdes_map[i].swap_tx = 1;
-					}
-#else
-#endif
 				}
 				else if ((type >= PEX0) && (type <= PEX3)) {
 					board_serdes_map[i].serdes_speed = SERDES_SPEED_5_GBPS;
@@ -216,13 +191,10 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
 					type = board_serdes_map[i].serdes_type;
 				}
 
-#ifdef NBHW18_V1
-#else
 				if (i==3) {
 					/* On V2 TX line for PCIe slot1 is inverted*/
 					board_serdes_map[i].swap_tx = 1;
 				}
-#endif
 
 				debug("Configure SERDES %d to %d\n", i, type);
 
@@ -388,8 +360,9 @@ int misc_init_r(void)
 	/* Because U-Boot is buggy, we need to call this funktion again
 	 * it will print the pre console buffer */
 
-	init_console();
+	/* TODO: Moved following two lines to board_late_init because ttyS1 is currently not working without loaded bitstream */
-	console_init_f();
+//	init_console();
+//	console_init_f();
 
 	return 0;
 }
@@ -413,27 +386,24 @@ static void set_phy_fast_blink_mode(int phy_addr)
 
 int board_late_init(void)
 {
-#ifdef NBHW18_V1
-	gpio_request(21, "RST_ETH_PHY_N");
-	gpio_direction_output(21, 0);
-#else
 	gpio_request(29, "RST_ETH_PHY_N");
 	gpio_direction_output(29, 0);
-#endif
+
 	find_and_set_active_partition();
 	pass_hw_rev();
 
 	/* Todo: It seems that something with the network is wrong */
 	run_command("run load_fpga", CMD_FLAG_ENV);
 
+	/* TODO: Move the following two lines up to misc_init_r when ttyS1 works without FPGA again */
+	init_console();
+	console_init_f();
+
 	set_mac_addresses(3);
 
 	/* Take phy out of reset after FPGA was loaded */
-#ifdef NBHW18_V1
-	gpio_set_value(21, 1);
-#else
 	gpio_set_value(29, 1);
-#endif
+
 	return 0;
 }
 

board/nm/nbhw18_v2/nbhw_fpga_config.c

@@ -103,7 +103,7 @@ static int request_and_set_gpio_by_name(ofnode fdt,
 	if (gpio_request_by_name_nodev(fdt, name, 0, desc,
 			GPIOD_IS_OUT))
 	{
-		printf("Could not request gpio %s\n", name);
+		debug("Could not request gpio %s\n", name);
 		return -1;
 	}
 

board/nm/nbhw18_v2/nbhw_mvswitch.c

@@ -294,6 +294,9 @@ void configure_mvswitch(void)
 			puts("No extension BD detected\n");
 			return;
 		}
+	} else {
+		puts("No extension EEPROM detected\n");
+		return;
 	}
 
 	/* Reset the switch */

configs/armada-385-nbhw18-v2_defconfig

@@ -11,7 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-nbhw18-spl"
 CONFIG_SMBIOS_PRODUCT_NAME="nbhw18_v2"
 CONFIG_BOOTDELAY=3
 CONFIG_BOOTSTAGE_STASH_SIZE=4096
-# CONFIG_PRE_CONSOLE_BUFFER is not set
+CONFIG_PRE_CONSOLE_BUFFER=y
 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
 CONFIG_PRE_CON_BUF_SZ=4096
 CONFIG_PRE_CON_BUF_ADDR=0x04000000

include/configs/armada-385-nbhw18-v2.h

@@ -129,11 +129,12 @@
 	"defaultconsole=ttyS1\0" \
 	"tftp_recovery=tftpboot $kernel_addr recovery-image; tftpboot $fdt_addr recovery-dtb; setenv bootargs rdinit=/etc/preinit console=$defaultconsole,115200 debug; bootz $kernel_addr - $fdt_addr\0" \
 	"pxe_recovery=sleep 3 && dhcp && pxe get && pxe boot\0" \
-	"load_fpga=ext4load mmc 0:$root_part $kernel_addr /logic/LG00000000 && nbhw_fpga program lattice-sspi 0xffffffff $kernel_addr $filesize && nbhw_fpga configure\0" \
+	"load_fpga=nbhw_fpga program lattice-sspi 0xffffffff 0 0 && nbhw_fpga configure\0" \
 	"recovery=run pxe_recovery || setenv ipaddr $ipaddr; setenv serverip $serverip; run tftp_recovery\0" /* setenv ipaddr and serverip is necessary, because dhclient can destroy the IPs inernally */
 
 #endif
 
+/*	"load_fpga=ext4load mmc 0:$root_part $kernel_addr /logic/LG00000000 && nbhw_fpga program lattice-sspi 0xffffffff $kernel_addr $filesize && nbhw_fpga configure\0" \ */
 
 /* SPL */
 /*