nbhw18: allow use of external serial port
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9cbe653246
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@ -18,9 +18,10 @@ void find_and_set_active_partition(void)
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void set_console(void)
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{
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#if defined(CONFIG_PRE_CONSOLE_BUFFER)
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char buf[50] = "\0";
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char *defaultconsole = env_get("defaultconsole");
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#if defined(CONFIG_PRE_CONSOLE_BUFFER)
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int len = 0;
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read_file_set_blk_dev("mmc", "0:3", FS_TYPE_EXT);
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@ -34,9 +35,9 @@ void set_console(void)
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strncpy(buf, defaultconsole, sizeof(buf));
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}
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printf("consoledev: %s\n", buf);
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env_set("consoledev", buf);
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#else
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env_set("consoledev", "ttyS0");
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strcpy(buf, defaultconsole);
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#endif
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env_set("consoledev", buf);
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}
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@ -586,13 +586,15 @@ static int fpga_boot_buffer(const struct nbhw_fpga_priv *priv, const u8* data, i
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u8* raw_bitstream;
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int raw_num_bytes;
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printf("BITSTREAM IS COMPILED IN. CHECK SKIPPED.\n");
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#if 0
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printf("Checking FPGA bitstream...\n");
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raw_num_bytes = num_bytes;
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if (fpga_check_bitstream(priv, data, &raw_bitstream, &raw_num_bytes)) {
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printf("Not a valid FPGA image at 0x%p\n", data);
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goto abort;
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}
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#endif
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/* Write bit stream */
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switch (priv->fpga_type) {
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case FPGA_LATTICE_SSPI :
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@ -3,7 +3,7 @@
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#define DEBUG
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#undef DEBUG
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#include <common.h>
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#include <i2c.h>
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#include <miiphy.h>
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@ -35,19 +35,6 @@ DECLARE_GLOBAL_DATA_PTR;
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* Those values and defines are taken from the Marvell U-Boot version
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* "u-boot-2013.01-2014_T3.0"
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*/
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#ifdef NBHW18_V1
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#define GPP_OUT_ENA_LOW (~(BIT(7) | BIT(19) | BIT(21))) /* 1=Input, default input */
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#define GPP_OUT_ENA_MID (~(BIT(9) | BIT(12)))
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#define GPP_OUT_VAL_LOW (BIT(21))
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#define GPP_OUT_VAL_MID (BIT(9))
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#define GPP_POL_LOW 0x0
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#define GPP_POL_MID 0x0
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#else
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#define GPP_OUT_ENA_LOW (~(BIT(6) | BIT(19) | BIT(29))) /* 1=Input, default input */
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#define GPP_OUT_ENA_MID (~(BIT(12) | BIT(15)))
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@ -57,8 +44,6 @@ DECLARE_GLOBAL_DATA_PTR;
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#define GPP_POL_LOW 0x0
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#define GPP_POL_MID 0x0
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#endif
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#define BD_EEPROM_ADDR (0x50) /* CPU BD EEPROM (8kByte) is at 50 (A0) */
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#define BD_ADDRESS (0x0000) /* Board descriptor at beginning of EEPROM */
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#define PD_ADDRESS (0x0200) /* Product descriptor */
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@ -189,16 +174,6 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
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if ((type >= SGMII0) && (type <= SGMII2)) {
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board_serdes_map[i].serdes_speed = SERDES_SPEED_1_25_GBPS;
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board_serdes_map[i].serdes_mode = SERDES_DEFAULT_MODE;
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#ifdef NBHW18_V1
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if (i==1) {
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/* Polarity of SERDES1 to switch extension seems
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to be inverted. Not sure, if the swapping happens
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on the main board or the extension board??? */
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board_serdes_map[i].swap_rx = 1;
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board_serdes_map[i].swap_tx = 1;
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}
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#else
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#endif
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}
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else if ((type >= PEX0) && (type <= PEX3)) {
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board_serdes_map[i].serdes_speed = SERDES_SPEED_5_GBPS;
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@ -216,13 +191,10 @@ int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count)
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type = board_serdes_map[i].serdes_type;
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}
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#ifdef NBHW18_V1
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#else
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if (i==3) {
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/* On V2 TX line for PCIe slot1 is inverted*/
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board_serdes_map[i].swap_tx = 1;
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}
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#endif
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debug("Configure SERDES %d to %d\n", i, type);
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@ -388,8 +360,9 @@ int misc_init_r(void)
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/* Because U-Boot is buggy, we need to call this funktion again
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* it will print the pre console buffer */
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init_console();
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console_init_f();
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/* TODO: Moved following two lines to board_late_init because ttyS1 is currently not working without loaded bitstream */
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// init_console();
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// console_init_f();
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return 0;
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}
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@ -413,27 +386,24 @@ static void set_phy_fast_blink_mode(int phy_addr)
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int board_late_init(void)
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{
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#ifdef NBHW18_V1
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gpio_request(21, "RST_ETH_PHY_N");
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gpio_direction_output(21, 0);
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#else
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gpio_request(29, "RST_ETH_PHY_N");
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gpio_direction_output(29, 0);
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#endif
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find_and_set_active_partition();
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pass_hw_rev();
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/* Todo: It seems that something with the network is wrong */
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run_command("run load_fpga", CMD_FLAG_ENV);
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/* TODO: Move the following two lines up to misc_init_r when ttyS1 works without FPGA again */
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init_console();
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console_init_f();
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set_mac_addresses(3);
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/* Take phy out of reset after FPGA was loaded */
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#ifdef NBHW18_V1
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gpio_set_value(21, 1);
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#else
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gpio_set_value(29, 1);
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#endif
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return 0;
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}
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@ -103,7 +103,7 @@ static int request_and_set_gpio_by_name(ofnode fdt,
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if (gpio_request_by_name_nodev(fdt, name, 0, desc,
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GPIOD_IS_OUT))
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{
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printf("Could not request gpio %s\n", name);
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debug("Could not request gpio %s\n", name);
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return -1;
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}
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@ -294,6 +294,9 @@ void configure_mvswitch(void)
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puts("No extension BD detected\n");
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return;
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}
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} else {
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puts("No extension EEPROM detected\n");
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return;
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}
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/* Reset the switch */
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@ -11,7 +11,7 @@ CONFIG_DEFAULT_DEVICE_TREE="armada-385-nbhw18-spl"
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CONFIG_SMBIOS_PRODUCT_NAME="nbhw18_v2"
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CONFIG_BOOTDELAY=3
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CONFIG_BOOTSTAGE_STASH_SIZE=4096
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# CONFIG_PRE_CONSOLE_BUFFER is not set
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CONFIG_PRE_CONSOLE_BUFFER=y
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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CONFIG_PRE_CON_BUF_SZ=4096
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CONFIG_PRE_CON_BUF_ADDR=0x04000000
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@ -129,11 +129,12 @@
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"defaultconsole=ttyS1\0" \
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"tftp_recovery=tftpboot $kernel_addr recovery-image; tftpboot $fdt_addr recovery-dtb; setenv bootargs rdinit=/etc/preinit console=$defaultconsole,115200 debug; bootz $kernel_addr - $fdt_addr\0" \
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"pxe_recovery=sleep 3 && dhcp && pxe get && pxe boot\0" \
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"load_fpga=ext4load mmc 0:$root_part $kernel_addr /logic/LG00000000 && nbhw_fpga program lattice-sspi 0xffffffff $kernel_addr $filesize && nbhw_fpga configure\0" \
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"load_fpga=nbhw_fpga program lattice-sspi 0xffffffff 0 0 && nbhw_fpga configure\0" \
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"recovery=run pxe_recovery || setenv ipaddr $ipaddr; setenv serverip $serverip; run tftp_recovery\0" /* setenv ipaddr and serverip is necessary, because dhclient can destroy the IPs inernally */
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#endif
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/* "load_fpga=ext4load mmc 0:$root_part $kernel_addr /logic/LG00000000 && nbhw_fpga program lattice-sspi 0xffffffff $kernel_addr $filesize && nbhw_fpga configure\0" \ */
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/* SPL */
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/*
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