86xx: Remove old-style law setup code
This includes mpc8610hpcd, mpc8641hpcn, and sbc8641d. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
This commit is contained in:
Becky Bruce
Jon Loeliger
parent
713d818664
commit
9cd32426f2
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@ -27,8 +27,6 @@ endif
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LIB = $(obj)lib$(BOARD).a
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LIB = $(obj)lib$(BOARD).a
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SOBJS := init.o
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COBJS := $(BOARD).o law.o
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COBJS := $(BOARD).o law.o
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COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o
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COBJS-${CONFIG_FSL_DIU_FB} += mpc8610hpcd_diu.o
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@ -1,147 +0,0 @@
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/*
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* Copyright 2007 Freescale Semiconductor.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* Version 2 as published by the Free Software Foundation.
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*/
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#include <config.h>
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <mpc86xx.h>
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#define LAWAR_TRGT_PCI1 0x00000000
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#define LAWAR_TRGT_PCIE1 0x00200000
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#define LAWAR_TRGT_PCIE2 0x00100000
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#define LAWAR_TRGT_LBC 0x00400000
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#define LAWAR_TRGT_DDR 0x00f00000
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#else
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#define LAWBAR1 0
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#define LAWAR1 ((LAWAR_TRGT_DDR | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR2 ((CFG_PCIE1_MEM_BASE>>12) & 0xffffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR3 ((CFG_PCIE2_MEM_BASE>>12) & 0xffffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR4 ((PIXIS_BASE>>12) & 0xffffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
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#define LAWBAR5 ((CFG_PCIE1_IO_PHYS>>12) & 0xffffff)
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#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_PCIE1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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#define LAWBAR6 ((CFG_PCIE2_IO_PHYS>>12) & 0xffffff)
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#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_PCIE2 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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#define LAWBAR7 ((CFG_FLASH_BASE >>12) & 0xffffff)
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#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR8 ((CFG_PCI1_MEM_PHYS>>12) & 0xffffff)
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#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#define LAWBAR9 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
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#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_1M))
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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lis r7,CFG_CCSRBAR@h
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ori r7,r7,CFG_CCSRBAR@l
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addi r4,r7,0
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addi r5,r7,0
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/* Skip LAWAR0, start at LAWAR1 */
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lis r6,LAWBAR1@h
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ori r6,r6,LAWBAR1@l
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stwu r6, 0xc28(r4)
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lis r6,LAWAR1@h
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ori r6,r6,LAWAR1@l
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stwu r6, 0xc30(r5)
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/* LAWBAR2, LAWAR2 */
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lis r6,LAWBAR2@h
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ori r6,r6,LAWBAR2@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR2@h
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ori r6,r6,LAWAR2@l
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stwu r6, 0x20(r5)
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/* LAWBAR3, LAWAR3 */
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lis r6,LAWBAR3@h
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ori r6,r6,LAWBAR3@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR3@h
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ori r6,r6,LAWAR3@l
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stwu r6, 0x20(r5)
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/* LAWBAR4, LAWAR4 */
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lis r6,LAWBAR4@h
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ori r6,r6,LAWBAR4@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR4@h
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ori r6,r6,LAWAR4@l
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stwu r6, 0x20(r5)
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/* LAWBAR5, LAWAR5 */
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lis r6,LAWBAR5@h
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ori r6,r6,LAWBAR5@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR5@h
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ori r6,r6,LAWAR5@l
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stwu r6, 0x20(r5)
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/* LAWBAR6, LAWAR6 */
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lis r6,LAWBAR6@h
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ori r6,r6,LAWBAR6@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR6@h
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ori r6,r6,LAWAR6@l
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stwu r6, 0x20(r5)
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/* LAWBAR7, LAWAR7 */
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lis r6,LAWBAR7@h
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ori r6,r6,LAWBAR7@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR7@h
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ori r6,r6,LAWAR7@l
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stwu r6, 0x20(r5)
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/* LAWBAR8, LAWAR8 */
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lis r6,LAWBAR8@h
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ori r6,r6,LAWBAR8@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR8@h
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ori r6,r6,LAWAR8@l
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stwu r6, 0x20(r5)
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/* LAWBAR9, LAWAR9 */
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lis r6,LAWBAR9@h
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ori r6,r6,LAWBAR9@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR9@h
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ori r6,r6,LAWAR9@l
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stwu r6, 0x20(r5)
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blr
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@ -51,7 +51,6 @@ SECTIONS
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.text :
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.text :
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{
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{
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cpu/mpc86xx/start.o (.text)
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cpu/mpc86xx/start.o (.text)
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board/freescale/mpc8610hpcd/init.o (.bootpg)
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cpu/mpc86xx/traps.o (.text)
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cpu/mpc86xx/traps.o (.text)
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cpu/mpc86xx/interrupts.o (.text)
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cpu/mpc86xx/interrupts.o (.text)
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cpu/mpc86xx/cpu_init.o (.text)
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cpu/mpc86xx/cpu_init.o (.text)
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@ -27,8 +27,6 @@ LIB = $(obj)lib$(BOARD).a
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COBJS := $(BOARD).o law.o
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COBJS := $(BOARD).o law.o
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SOBJS := init.o
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
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OBJS := $(addprefix $(obj),$(COBJS))
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OBJS := $(addprefix $(obj),$(COBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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SOBJS := $(addprefix $(obj),$(SOBJS))
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@ -1,179 +0,0 @@
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/*
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* Copyright 2004 Freescale Semiconductor.
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* Jeff Brown
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* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <ppc_asm.tmpl>
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#include <ppc_defs.h>
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#include <asm/cache.h>
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#include <asm/mmu.h>
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#include <config.h>
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#include <mpc86xx.h>
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/*
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* LAW(Local Access Window) configuration:
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*
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* 0x0000_0000 0x7fff_ffff DDR 2G
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* 0x8000_0000 0x9fff_ffff PCI1 MEM 512M
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* 0xa000_0000 0xbfff_ffff PCI2 MEM 512M
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* 0xc000_0000 0xdfff_ffff RapidIO 512M
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* 0xe200_0000 0xe2ff_ffff PCI1 IO 16M
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* 0xe300_0000 0xe3ff_ffff PCI2 IO 16M
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* 0xf800_0000 0xf80f_ffff CCSRBAR 1M
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* 0xf810_0000 0xf81f_ffff PIXIS 1M
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* 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M
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*
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* Notes:
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* CCSRBAR don't need a configured Local Access Window.
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* If flash is 8M at default position (last 8M), no LAW needed.
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*/
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
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#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#else
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#define LAWBAR1 0
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#define LAWAR1 ((LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
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#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
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#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M))
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/*
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* This is not so much the SDRAM map as it is the whole localbus map.
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*/
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#define LAWBAR4 ((0xf8100000>>12) & 0xffffff)
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#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
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#define LAWBAR5 ((CFG_PCI1_IO_PHYS>>12) & 0xffffff)
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#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
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#define LAWBAR6 ((CFG_PCI2_IO_PHYS>>12) & 0xffffff)
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#define LAWAR6 (LAWAR_EN | LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M))
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#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
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#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
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#if !defined(CONFIG_SPD_EEPROM)
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#define LAWBAR8 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
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#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
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#else
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#define LAWBAR8 0
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#define LAWAR8 ((LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_512M)) & ~LAWAR_EN)
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#endif
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#define LAWBAR9 ((CFG_RIO_MEM_PHYS>>12) & 0xfffff)
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#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
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.section .bootpg, "ax"
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.globl law_entry
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law_entry:
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lis r7,CFG_CCSRBAR@h
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ori r7,r7,CFG_CCSRBAR@l
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addi r4,r7,0
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addi r5,r7,0
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/* Skip LAWAR0, start at LAWAR1 */
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lis r6,LAWBAR1@h
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ori r6,r6,LAWBAR1@l
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stwu r6, 0xc28(r4)
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lis r6,LAWAR1@h
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ori r6,r6,LAWAR1@l
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stwu r6, 0xc30(r5)
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/* LAWBAR2, LAWAR2 */
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lis r6,LAWBAR2@h
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ori r6,r6,LAWBAR2@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR2@h
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ori r6,r6,LAWAR2@l
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stwu r6, 0x20(r5)
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/* LAWBAR3, LAWAR3 */
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lis r6,LAWBAR3@h
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ori r6,r6,LAWBAR3@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR3@h
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ori r6,r6,LAWAR3@l
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stwu r6, 0x20(r5)
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/* LAWBAR4, LAWAR4 */
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lis r6,LAWBAR4@h
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ori r6,r6,LAWBAR4@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR4@h
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ori r6,r6,LAWAR4@l
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stwu r6, 0x20(r5)
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/* LAWBAR5, LAWAR5 */
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lis r6,LAWBAR5@h
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ori r6,r6,LAWBAR5@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR5@h
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ori r6,r6,LAWAR5@l
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stwu r6, 0x20(r5)
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/* LAWBAR6, LAWAR6 */
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lis r6,LAWBAR6@h
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ori r6,r6,LAWBAR6@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR6@h
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ori r6,r6,LAWAR6@l
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stwu r6, 0x20(r5)
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/* LAWBAR7, LAWAR7 */
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lis r6,LAWBAR7@h
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ori r6,r6,LAWBAR7@l
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stwu r6, 0x20(r4)
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lis r6,LAWAR7@h
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ori r6,r6,LAWAR7@l
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stwu r6, 0x20(r5)
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|
|
||||||
/* LAWBAR8, LAWAR8 */
|
|
||||||
lis r6,LAWBAR8@h
|
|
||||||
ori r6,r6,LAWBAR8@l
|
|
||||||
stwu r6, 0x20(r4)
|
|
||||||
|
|
||||||
lis r6,LAWAR8@h
|
|
||||||
ori r6,r6,LAWAR8@l
|
|
||||||
stwu r6, 0x20(r5)
|
|
||||||
|
|
||||||
/* LAWBAR9, LAWAR9 */
|
|
||||||
lis r6,LAWBAR9@h
|
|
||||||
ori r6,r6,LAWBAR9@l
|
|
||||||
stwu r6, 0x20(r4)
|
|
||||||
|
|
||||||
lis r6,LAWAR9@h
|
|
||||||
ori r6,r6,LAWAR9@l
|
|
||||||
stwu r6, 0x20(r5)
|
|
||||||
|
|
||||||
blr
|
|
||||||
|
|
@ -51,7 +51,6 @@ SECTIONS
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
cpu/mpc86xx/start.o (.text)
|
cpu/mpc86xx/start.o (.text)
|
||||||
board/freescale/mpc8641hpcn/init.o (.bootpg)
|
|
||||||
cpu/mpc86xx/traps.o (.text)
|
cpu/mpc86xx/traps.o (.text)
|
||||||
cpu/mpc86xx/interrupts.o (.text)
|
cpu/mpc86xx/interrupts.o (.text)
|
||||||
cpu/mpc86xx/cpu_init.o (.text)
|
cpu/mpc86xx/cpu_init.o (.text)
|
||||||
|
|
|
||||||
|
|
@ -26,7 +26,6 @@ include $(TOPDIR)/config.mk
|
||||||
LIB = $(obj)lib$(BOARD).a
|
LIB = $(obj)lib$(BOARD).a
|
||||||
|
|
||||||
COBJS := $(BOARD).o law.o
|
COBJS := $(BOARD).o law.o
|
||||||
SOBJS := init.o
|
|
||||||
|
|
||||||
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
|
||||||
OBJS := $(addprefix $(obj),$(COBJS))
|
OBJS := $(addprefix $(obj),$(COBJS))
|
||||||
|
|
|
||||||
|
|
@ -1,192 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2007 Wind River Systemes, Inc. <www.windriver.com>
|
|
||||||
* Copyright 2007 Embedded Specialties, Inc.
|
|
||||||
* Joe Hamman joe.hamman@embeddedspecialties.com
|
|
||||||
*
|
|
||||||
* Copyright 2004 Freescale Semiconductor.
|
|
||||||
* Jeff Brown
|
|
||||||
* Srikanth Srinivasan (srikanth.srinivasan@freescale.com)
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <ppc_asm.tmpl>
|
|
||||||
#include <ppc_defs.h>
|
|
||||||
#include <asm/cache.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
#include <config.h>
|
|
||||||
#include <mpc86xx.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* LAW(Local Access Window) configuration:
|
|
||||||
*
|
|
||||||
* 0x0000_0000 0x0fff_ffff DDR1 256M
|
|
||||||
* 0x1000_0000 0x1fff_ffff DDR2 256M
|
|
||||||
* 0xe000_0000 0xffff_ffff LBC 512M
|
|
||||||
*
|
|
||||||
* Notes:
|
|
||||||
* CCSRBAR doesn't need a configured Local Access Window.
|
|
||||||
* If flash is 8M at default position (last 8M), no LAW needed.
|
|
||||||
*/
|
|
||||||
|
|
||||||
# DDR Bank 1
|
|
||||||
# #define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
|
|
||||||
# #define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
|
||||||
|
|
||||||
# DDR Bank 2
|
|
||||||
# #define LAWBAR2 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
|
|
||||||
# #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
|
||||||
|
|
||||||
# LBC
|
|
||||||
# #define LAWBAR3 ((0xe0000000>>12) & 0xffffff)
|
|
||||||
# #define LAWAR3 (LAWAR_EN & (LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_512M)))
|
|
||||||
|
|
||||||
/*
|
|
||||||
* LAW (Local Access Window) configuration:
|
|
||||||
*
|
|
||||||
* 0x0000_0000 DDR 256M
|
|
||||||
* 0x1000_0000 DDR2 256M
|
|
||||||
* 0x8000_0000 PCI1 MEM 512M
|
|
||||||
* 0xa000_0000 PCI2 MEM 512M
|
|
||||||
* 0xc000_0000 RapidIO 512M
|
|
||||||
* 0xe200_0000 PCI1 IO 16M
|
|
||||||
* 0xe300_0000 PCI2 IO 16M
|
|
||||||
* 0xf800_0000 CCSRBAR 2M
|
|
||||||
* 0xfe00_0000 FLASH (boot bank) 32M
|
|
||||||
*
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define LAWBAR1 ((CFG_DDR_SDRAM_BASE>>12) & 0xffffff)
|
|
||||||
#define LAWAR1 (LAWAR_EN | LAWAR_TRGT_IF_DDR1 | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
|
||||||
|
|
||||||
#define LAWBAR2 ((CFG_PCI1_MEM_BASE>>12) & 0xffffff)
|
|
||||||
#define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
|
||||||
|
|
||||||
#define LAWBAR3 ((CFG_PCI2_MEM_BASE>>12) & 0xffffff)
|
|
||||||
#define LAWAR3 (~LAWAR_EN & (LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_512M)))
|
|
||||||
|
|
||||||
#define LAWBAR4 ((0xf8000000>>12) & 0xffffff)
|
|
||||||
#define LAWAR4 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_2M))
|
|
||||||
|
|
||||||
#define LAWBAR5 ((CFG_PCI1_IO_BASE>>12) & 0xffffff)
|
|
||||||
#define LAWAR5 (LAWAR_EN | LAWAR_TRGT_IF_PCI1 | (LAWAR_SIZE & LAWAR_SIZE_16M))
|
|
||||||
|
|
||||||
#define LAWBAR6 ((CFG_PCI2_IO_BASE>>12) & 0xffffff)
|
|
||||||
#define LAWAR6 (~LAWAR_EN &( LAWAR_TRGT_IF_PCI2 | (LAWAR_SIZE & LAWAR_SIZE_16M)))
|
|
||||||
|
|
||||||
#define LAWBAR7 ((0xfe000000 >>12) & 0xffffff)
|
|
||||||
#define LAWAR7 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_32M))
|
|
||||||
|
|
||||||
#define LAWBAR8 ((CFG_DDR_SDRAM_BASE2>>12) & 0xffffff)
|
|
||||||
#define LAWAR8 (LAWAR_EN | LAWAR_TRGT_IF_DDR2 | (LAWAR_SIZE & LAWAR_SIZE_256M))
|
|
||||||
|
|
||||||
#define LAWBAR9 ((CFG_RIO_MEM_BASE>>12) & 0xfffff)
|
|
||||||
#define LAWAR9 (LAWAR_EN | LAWAR_TRGT_IF_RIO | (LAWAR_SIZE & LAWAR_SIZE_512M))
|
|
||||||
|
|
||||||
.section .bootpg, "ax"
|
|
||||||
.globl law_entry
|
|
||||||
law_entry:
|
|
||||||
lis r7,CFG_CCSRBAR@h
|
|
||||||
ori r7,r7,CFG_CCSRBAR@l
|
|
||||||
|
|
||||||
addi r4,r7,0
|
|
||||||
addi r5,r7,0
|
|
||||||
|
|
||||||
/* Skip LAWAR0, start at LAWAR1 */
|
|
||||||
lis r6,LAWBAR1@h
|
|
||||||
ori r6,r6,LAWBAR1@l
|
|
||||||
stwu r6, 0xc28(r4)
|
|
||||||
|
|
||||||
lis r6,LAWAR1@h
|
|
||||||
ori r6,r6,LAWAR1@l
|
|
||||||
stwu r6, 0xc30(r5)
|
|
||||||
|
|
||||||
/* LAWBAR2, LAWAR2 */
|
|
||||||
lis r6,LAWBAR2@h
|
|
||||||
ori r6,r6,LAWBAR2@l
|
|
||||||
stwu r6, 0x20(r4)
|
|
||||||
|
|
||||||
lis r6,LAWAR2@h
|
|
||||||
ori r6,r6,LAWAR2@l
|
|
||||||
stwu r6, 0x20(r5)
|
|
||||||
|
|
||||||
/* LAWBAR3, LAWAR3 */
|
|
||||||
lis r6,LAWBAR3@h
|
|
||||||
ori r6,r6,LAWBAR3@l
|
|
||||||
stwu r6, 0x20(r4)
|
|
||||||
|
|
||||||
lis r6,LAWAR3@h
|
|
||||||
ori r6,r6,LAWAR3@l
|
|
||||||
stwu r6, 0x20(r5)
|
|
||||||
|
|
||||||
/* LAWBAR4, LAWAR4 */
|
|
||||||
lis r6,LAWBAR4@h
|
|
||||||
ori r6,r6,LAWBAR4@l
|
|
||||||
stwu r6, 0x20(r4)
|
|
||||||
|
|
||||||
lis r6,LAWAR4@h
|
|
||||||
ori r6,r6,LAWAR4@l
|
|
||||||
stwu r6, 0x20(r5)
|
|
||||||
|
|
||||||
/* LAWBAR5, LAWAR5 */
|
|
||||||
lis r6,LAWBAR5@h
|
|
||||||
ori r6,r6,LAWBAR5@l
|
|
||||||
stwu r6, 0x20(r4)
|
|
||||||
|
|
||||||
lis r6,LAWAR5@h
|
|
||||||
ori r6,r6,LAWAR5@l
|
|
||||||
stwu r6, 0x20(r5)
|
|
||||||
|
|
||||||
/* LAWBAR6, LAWAR6 */
|
|
||||||
lis r6,LAWBAR6@h
|
|
||||||
ori r6,r6,LAWBAR6@l
|
|
||||||
stwu r6, 0x20(r4)
|
|
||||||
|
|
||||||
lis r6,LAWAR6@h
|
|
||||||
ori r6,r6,LAWAR6@l
|
|
||||||
stwu r6, 0x20(r5)
|
|
||||||
|
|
||||||
/* LAWBAR7, LAWAR7 */
|
|
||||||
lis r6,LAWBAR7@h
|
|
||||||
ori r6,r6,LAWBAR7@l
|
|
||||||
stwu r6, 0x20(r4)
|
|
||||||
|
|
||||||
lis r6,LAWAR7@h
|
|
||||||
ori r6,r6,LAWAR7@l
|
|
||||||
stwu r6, 0x20(r5)
|
|
||||||
|
|
||||||
/* LAWBAR8, LAWAR8 */
|
|
||||||
lis r6,LAWBAR8@h
|
|
||||||
ori r6,r6,LAWBAR8@l
|
|
||||||
stwu r6, 0x20(r4)
|
|
||||||
|
|
||||||
lis r6,LAWAR8@h
|
|
||||||
ori r6,r6,LAWAR8@l
|
|
||||||
stwu r6, 0x20(r5)
|
|
||||||
|
|
||||||
/* LAWBAR9, LAWAR9 */
|
|
||||||
lis r6,LAWBAR9@h
|
|
||||||
ori r6,r6,LAWBAR9@l
|
|
||||||
stwu r6, 0x20(r4)
|
|
||||||
|
|
||||||
lis r6,LAWAR9@h
|
|
||||||
ori r6,r6,LAWAR9@l
|
|
||||||
stwu r6, 0x20(r5)
|
|
||||||
|
|
||||||
blr
|
|
||||||
|
|
@ -51,7 +51,6 @@ SECTIONS
|
||||||
.text :
|
.text :
|
||||||
{
|
{
|
||||||
cpu/mpc86xx/start.o (.text)
|
cpu/mpc86xx/start.o (.text)
|
||||||
board/sbc8641d/init.o (.bootpg)
|
|
||||||
cpu/mpc86xx/traps.o (.text)
|
cpu/mpc86xx/traps.o (.text)
|
||||||
cpu/mpc86xx/interrupts.o (.text)
|
cpu/mpc86xx/interrupts.o (.text)
|
||||||
cpu/mpc86xx/cpu_init.o (.text)
|
cpu/mpc86xx/cpu_init.o (.text)
|
||||||
|
|
|
||||||
|
|
@ -1123,7 +1123,6 @@ spd_sdram(void)
|
||||||
int memsize_ddr1 = 0;
|
int memsize_ddr1 = 0;
|
||||||
unsigned int law_size_ddr1;
|
unsigned int law_size_ddr1;
|
||||||
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
volatile immap_t *immap = (immap_t *)CFG_IMMR;
|
||||||
volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
|
|
||||||
#ifdef CONFIG_DDR_INTERLEAVE
|
#ifdef CONFIG_DDR_INTERLEAVE
|
||||||
volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
|
volatile ccsr_ddr_t *ddr1 = &immap->im_ddr1;
|
||||||
#endif
|
#endif
|
||||||
|
|
@ -1181,13 +1180,6 @@ spd_sdram(void)
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_FSL_LAW
|
#ifdef CONFIG_FSL_LAW
|
||||||
set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
|
set_law(1, CFG_DDR_SDRAM_BASE, law_size_interleaved, LAW_TRGT_IF_DDR_INTRLV);
|
||||||
#else
|
|
||||||
mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
|
|
||||||
mcm->lawar1 = (LAWAR_EN
|
|
||||||
| LAWAR_TRGT_IF_DDR_INTERLEAVED
|
|
||||||
| (LAWAR_SIZE & law_size_interleaved));
|
|
||||||
debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
|
|
||||||
debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
|
|
||||||
#endif
|
#endif
|
||||||
debug("Interleaved memory size is 0x%08lx\n", memsize_total);
|
debug("Interleaved memory size is 0x%08lx\n", memsize_total);
|
||||||
|
|
||||||
|
|
@ -1245,13 +1237,6 @@ spd_sdram(void)
|
||||||
*/
|
*/
|
||||||
#ifdef CONFIG_FSL_LAW
|
#ifdef CONFIG_FSL_LAW
|
||||||
set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
|
set_law(1, CFG_DDR_SDRAM_BASE, law_size_ddr1, LAW_TRGT_IF_DDR_1);
|
||||||
#else
|
|
||||||
mcm->lawbar1 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
|
|
||||||
mcm->lawar1 = (LAWAR_EN
|
|
||||||
| LAWAR_TRGT_IF_DDR1
|
|
||||||
| (LAWAR_SIZE & law_size_ddr1));
|
|
||||||
debug("DDR: LAWBAR1=0x%08x\n", mcm->lawbar1);
|
|
||||||
debug("DDR: LAWAR1=0x%08x\n", mcm->lawar1);
|
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
@ -1281,18 +1266,6 @@ spd_sdram(void)
|
||||||
set_law(8,
|
set_law(8,
|
||||||
(ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
|
(ddr1_enabled ? (memsize_ddr1 * 1024 * 1024) : CFG_DDR_SDRAM_BASE),
|
||||||
law_size_ddr2, LAW_TRGT_IF_DDR_2);
|
law_size_ddr2, LAW_TRGT_IF_DDR_2);
|
||||||
#else
|
|
||||||
if (ddr1_enabled)
|
|
||||||
mcm->lawbar8 = (((memsize_ddr1 * 1024 * 1024) >> 12)
|
|
||||||
& 0xfffff);
|
|
||||||
else
|
|
||||||
mcm->lawbar8 = ((CFG_DDR_SDRAM_BASE >> 12) & 0xfffff);
|
|
||||||
|
|
||||||
mcm->lawar8 = (LAWAR_EN
|
|
||||||
| LAWAR_TRGT_IF_DDR2
|
|
||||||
| (LAWAR_SIZE & law_size_ddr2));
|
|
||||||
debug("\nDDR: LAWBAR8=0x%08x\n", mcm->lawbar8);
|
|
||||||
debug("DDR: LAWAR8=0x%08x\n", mcm->lawar8);
|
|
||||||
#endif
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -283,11 +283,6 @@ in_flash:
|
||||||
bl setup_ccsrbar
|
bl setup_ccsrbar
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
#ifndef CONFIG_FSL_LAW
|
|
||||||
bl law_entry
|
|
||||||
sync
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* run low-level CPU init code (from Flash) */
|
/* run low-level CPU init code (from Flash) */
|
||||||
bl cpu_init_f
|
bl cpu_init_f
|
||||||
sync
|
sync
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue