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MLK-20784-2 imx8mm: Load fuse for TMU TCALIV and TASR 

On iMX8MM, the default value of TMU registers TCALIV and TASR need
be loaded from fuse. HW won't do this, it expect SW loads them before
using TMU.

Signed-off-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Bai Ping <ping.bai@nxp.com>
This commit is contained in:
Ye Li 2019-01-21 00:33:38 -08:00
parent 1a66350d1b
commit 9dada8a697
3 changed files with 49 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
arch/arm/include/asm/arch-imx8m/imx-regs-imx8mm.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2018 NXP
* Copyright 2018-2019 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -229,6 +229,17 @@ struct fuse_bank1_regs {
u32 rsvd3[3];
};
struct fuse_bank3_regs {
u32 mem_trim0;
u32 rsvd0[3];
u32 mem_trim1;
u32 rsvd1[3];
u32 mem_trim2;
u32 rsvd2[3];
u32 ana0;
u32 rsvd3[3];
};
struct fuse_bank9_regs {
u32 mac_addr0;
u32 rsvd0[3];

13
arch/arm/include/asm/arch-imx8m/imx-regs-imx8mq.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2017-2018 NXP
* Copyright 2017-2019 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -217,6 +217,17 @@ struct fuse_bank1_regs {
u32 rsvd3[3];
};
struct fuse_bank3_regs {
u32 mem_trim0;
u32 rsvd0[3];
u32 mem_trim1;
u32 rsvd1[3];
u32 ana0;
u32 rsvd2[3];
u32 ana1;
u32 rsvd3[3];
};
struct anamix_pll {
u32 audio_pll1_cfg0;
u32 audio_pll1_cfg1;

26
arch/arm/mach-imx/imx8m/soc.c
View File

@ -1,5 +1,5 @@
/*
* Copyright 2017-2018 NXP
* Copyright 2017-2019 NXP
*
* Peng Fan <peng.fan@nxp.com>
*
@ -712,3 +712,27 @@ int imx8m_usb_power(int usb_id, bool on)
#endif
return 0;
}
void nxp_tmu_arch_init(void *reg_base)
{
if (is_imx8mm()) {
/* Load TCALIV and TASR from fuses */
struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
struct fuse_bank *bank = &ocotp->bank[3];
struct fuse_bank3_regs *fuse =
(struct fuse_bank3_regs *)bank->fuse_regs;
u32 tca_rt, tca_hr, tca_en;
u32 buf_vref, buf_slope;
tca_rt = fuse->ana0 & 0xFF;
tca_hr = (fuse->ana0 & 0xFF00) >> 8;
tca_en = (fuse->ana0 & 0x2000000) >> 25;
buf_vref = (fuse->ana0 & 0x1F00000) >> 20;
buf_slope = (fuse->ana0 & 0xF0000) >> 16;
writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28);
writel((tca_en << 31) |(tca_hr <<16) | tca_rt, (ulong)reg_base + 0x30);
}
}