power domain: MediaTek: add power domain driver for MT7623 SoC
This adds power domain (scpsys) support for MT7623 SoC. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org>
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					@ -14,9 +14,19 @@
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#include <asm/processor.h>
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					#include <asm/processor.h>
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#include <linux/iopoll.h>
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					#include <linux/iopoll.h>
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					#include <dt-bindings/power/mt7623-power.h>
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#include <dt-bindings/power/mt7629-power.h>
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					#include <dt-bindings/power/mt7629-power.h>
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#define SPM_EN			(0xb16 << 16 | 0x1)
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					#define SPM_EN			(0xb16 << 16 | 0x1)
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					#define SPM_VDE_PWR_CON		0x0210
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					#define SPM_MFG_PWR_CON		0x0214
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					#define SPM_ISP_PWR_CON		0x0238
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					#define SPM_DIS_PWR_CON		0x023c
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					#define SPM_CONN_PWR_CON	0x0280
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					#define SPM_BDP_PWR_CON		0x029c
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					#define SPM_ETH_PWR_CON		0x02a0
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					#define SPM_HIF_PWR_CON		0x02a4
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					#define SPM_IFR_MSC_PWR_CON	0x02a8
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#define SPM_ETHSYS_PWR_CON	0x2e0
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					#define SPM_ETHSYS_PWR_CON	0x2e0
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#define SPM_HIF0_PWR_CON	0x2e4
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					#define SPM_HIF0_PWR_CON	0x2e4
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#define SPM_HIF1_PWR_CON	0x2e8
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					#define SPM_HIF1_PWR_CON	0x2e8
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					@ -29,6 +39,15 @@
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#define PWR_ON_2ND_BIT		BIT(3)
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					#define PWR_ON_2ND_BIT		BIT(3)
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#define PWR_CLK_DIS_BIT		BIT(4)
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					#define PWR_CLK_DIS_BIT		BIT(4)
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					#define PWR_STATUS_CONN		BIT(1)
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					#define PWR_STATUS_DISP		BIT(3)
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					#define PWR_STATUS_MFG		BIT(4)
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					#define PWR_STATUS_ISP		BIT(5)
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					#define PWR_STATUS_VDEC		BIT(7)
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					#define PWR_STATUS_BDP		BIT(14)
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					#define PWR_STATUS_ETH		BIT(15)
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					#define PWR_STATUS_HIF		BIT(16)
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					#define PWR_STATUS_IFR_MSC	BIT(17)
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#define PWR_STATUS_ETHSYS	BIT(24)
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					#define PWR_STATUS_ETHSYS	BIT(24)
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#define PWR_STATUS_HIF0		BIT(25)
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					#define PWR_STATUS_HIF0		BIT(25)
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#define PWR_STATUS_HIF1		BIT(26)
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					#define PWR_STATUS_HIF1		BIT(26)
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					@ -41,6 +60,7 @@
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#define DCM_TOP_EN		BIT(0)
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					#define DCM_TOP_EN		BIT(0)
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enum scp_domain_type {
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					enum scp_domain_type {
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						SCPSYS_MT7623,
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	SCPSYS_MT7629,
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						SCPSYS_MT7629,
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};
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					};
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					@ -62,6 +82,59 @@ struct scp_domain {
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	struct scp_domain_data *data;
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						struct scp_domain_data *data;
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};
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					};
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					static struct scp_domain_data scp_domain_mt7623[] = {
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						[MT7623_POWER_DOMAIN_CONN] = {
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							.sta_mask = PWR_STATUS_CONN,
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							.ctl_offs = SPM_CONN_PWR_CON,
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							.bus_prot_mask = BIT(8) | BIT(2),
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						},
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						[MT7623_POWER_DOMAIN_DISP] = {
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							.sta_mask = PWR_STATUS_DISP,
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							.ctl_offs = SPM_DIS_PWR_CON,
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							.sram_pdn_bits = GENMASK(11, 8),
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							.bus_prot_mask = BIT(2),
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						},
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						[MT7623_POWER_DOMAIN_MFG] = {
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							.sta_mask = PWR_STATUS_MFG,
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							.ctl_offs = SPM_MFG_PWR_CON,
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							.sram_pdn_bits = GENMASK(11, 8),
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							.sram_pdn_ack_bits = GENMASK(12, 12),
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						},
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						[MT7623_POWER_DOMAIN_VDEC] = {
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							.sta_mask = PWR_STATUS_VDEC,
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							.ctl_offs = SPM_VDE_PWR_CON,
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							.sram_pdn_bits = GENMASK(11, 8),
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							.sram_pdn_ack_bits = GENMASK(12, 12),
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						},
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						[MT7623_POWER_DOMAIN_ISP] = {
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							.sta_mask = PWR_STATUS_ISP,
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							.ctl_offs = SPM_ISP_PWR_CON,
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							.sram_pdn_bits = GENMASK(11, 8),
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							.sram_pdn_ack_bits = GENMASK(13, 12),
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						},
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						[MT7623_POWER_DOMAIN_BDP] = {
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							.sta_mask = PWR_STATUS_BDP,
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							.ctl_offs = SPM_BDP_PWR_CON,
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							.sram_pdn_bits = GENMASK(11, 8),
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						},
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						[MT7623_POWER_DOMAIN_ETH] = {
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							.sta_mask = PWR_STATUS_ETH,
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							.ctl_offs = SPM_ETH_PWR_CON,
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							.sram_pdn_bits = GENMASK(11, 8),
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							.sram_pdn_ack_bits = GENMASK(15, 12),
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						},
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						[MT7623_POWER_DOMAIN_HIF] = {
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							.sta_mask = PWR_STATUS_HIF,
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							.ctl_offs = SPM_HIF_PWR_CON,
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							.sram_pdn_bits = GENMASK(11, 8),
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							.sram_pdn_ack_bits = GENMASK(15, 12),
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						},
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						[MT7623_POWER_DOMAIN_IFR_MSC] = {
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							.sta_mask = PWR_STATUS_IFR_MSC,
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							.ctl_offs = SPM_IFR_MSC_PWR_CON,
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						},
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					};
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static struct scp_domain_data scp_domain_mt7629[] = {
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					static struct scp_domain_data scp_domain_mt7629[] = {
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	[MT7629_POWER_DOMAIN_ETHSYS] = {
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						[MT7629_POWER_DOMAIN_ETHSYS] = {
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		.sta_mask = PWR_STATUS_ETHSYS,
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							.sta_mask = PWR_STATUS_ETHSYS,
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					@ -252,6 +325,9 @@ static int mtk_power_domain_hook(struct udevice *dev)
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	scpd->type = (enum scp_domain_type)dev_get_driver_data(dev);
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						scpd->type = (enum scp_domain_type)dev_get_driver_data(dev);
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	switch (scpd->type) {
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						switch (scpd->type) {
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						case SCPSYS_MT7623:
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							scpd->data = scp_domain_mt7623;
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							break;
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	case SCPSYS_MT7629:
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						case SCPSYS_MT7629:
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		scpd->data = scp_domain_mt7629;
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							scpd->data = scp_domain_mt7629;
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		break;
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							break;
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					@ -302,6 +378,10 @@ static int mtk_power_domain_probe(struct udevice *dev)
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}
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					}
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static const struct udevice_id mtk_power_domain_ids[] = {
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					static const struct udevice_id mtk_power_domain_ids[] = {
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						{
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							.compatible = "mediatek,mt7623-scpsys",
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							.data = SCPSYS_MT7623,
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						},
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	{
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						{
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		.compatible = "mediatek,mt7629-scpsys",
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							.compatible = "mediatek,mt7629-scpsys",
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		.data = SCPSYS_MT7629,
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							.data = SCPSYS_MT7629,
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