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MLK-20794-2 imx8qxp_arm2: Add support for 17x17 validation boards 

There are two new validation boards: LPDDR4 board (30123) and DDR3L board (30010)
for imx8x family 17x17 chips. These two boards have same design except the DDR.
Since SCFW is resposible for DDR initialization, U-boot could use one build to
cover two boards.
The 8DX 17x17 DDR3L ARM2 has been added into u-boot before, so we rename the config
CONFIG_TARGET_IMX8DX_DDR3_ARM2 to CONFIG_TARGET_IMX8X_17X17_VAL to cover DDR3L and
LPDDR4.

Considering 8DX and 8QXP 17x17 may solder to the boards, we create two defconfig:
one for DX and another for 8qxp to share with the CONFIG_TARGET_IMX8X_17X17_VAL
but with different FDTs.

Signed-off-by: Ye Li <ye.li@nxp.com>
This commit is contained in:
Ye Li 2019-01-23 01:32:40 -08:00
parent da636e4b8e
commit 9eea203022
10 changed files with 134 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
arch/arm/dts/Makefile
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@ -470,11 +470,12 @@ dtb-$(CONFIG_ARCH_IMX8M) += fsl-imx8mq-evk.dtb \
fsl-imx8mm-ddr4-val.dtb \
fsl-imx8mm-evk.dtb
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8dx-ddr3-arm2.dtb \
dtb-$(CONFIG_ARCH_IMX8) += fsl-imx8dx-17x17-val.dtb \
fsl-imx8qm-ddr4-arm2.dtb \
fsl-imx8qm-lpddr4-arm2.dtb \
fsl-imx8qm-mek.dtb \
fsl-imx8qm-mek-xen.dtb \
fsl-imx8qxp-17x17-val.dtb \
fsl-imx8qxp-lpddr4-arm2.dtb \
fsl-imx8qxp-mek.dtb

19
arch/arm/dts/fsl-imx8dx-17x17-val.dts Normal file
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@ -0,0 +1,19 @@
/*
* Copyright 2018 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "fsl-imx8qxp-17x17-val.dts"
/ {
model = "Freescale i.MX8DX 17x17 Validation board";
};

2
arch/arm/dts/fsl-imx8dx-ddr3-arm2.dts → arch/arm/dts/fsl-imx8qxp-17x17-val.dts
View File

@ -15,7 +15,7 @@
#include "fsl-imx8qxp-lpddr4-arm2.dts"
/ {
model = "Freescale i.MX8DX DDR3 ARM2";
model = "Freescale i.MX8QXP 17x17 Validation board";
};
&i2c1 {

4
arch/arm/mach-imx/imx8/Kconfig
View File

@ -73,8 +73,8 @@ config TARGET_IMX8QXP_DDR3_ARM2
select BOARD_LATE_INIT
select IMX8QXP
config TARGET_IMX8DX_DDR3_ARM2
bool "Support i.MX8DX ddr3 validation board"
config TARGET_IMX8X_17X17_VAL
bool "Support i.MX8QXP/DX 17x17 validation board"
select BOARD_LATE_INIT
select IMX8QXP

2
board/freescale/imx8qxp_arm2/Kconfig
View File

@ -1,4 +1,4 @@
if TARGET_IMX8QXP_LPDDR4_ARM2 || TARGET_IMX8QXP_DDR3_ARM2 || TARGET_IMX8DX_DDR3_ARM2
if TARGET_IMX8QXP_LPDDR4_ARM2 || TARGET_IMX8QXP_DDR3_ARM2 || TARGET_IMX8X_17X17_VAL
config SYS_BOARD
default "imx8qxp_arm2"

6
board/freescale/imx8qxp_arm2/imx8qxp_arm2.c
View File

@ -183,7 +183,7 @@ int board_early_init_f(void)
#ifndef CONFIG_SPL_BUILD
static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
{USDHC1_BASE_ADDR, 0, 8},
#ifndef CONFIG_TARGET_IMX8DX_DDR3_ARM2
#ifndef CONFIG_TARGET_IMX8X_17X17_VAL
{USDHC2_BASE_ADDR, 0, 4},
#endif
};
@ -472,8 +472,8 @@ int checkboard(void)
{
#if defined(CONFIG_TARGET_IMX8QXP_DDR3_ARM2)
puts("Board: iMX8QXP DDR3 ARM2\n");
#elif defined(CONFIG_TARGET_IMX8DX_DDR3_ARM2)
puts("Board: iMX8DX DDR3 ARM2\n");
#elif defined(CONFIG_TARGET_IMX8X_17X17_VAL)
puts("Board: iMX8X(QXP/DX) 17x17 Validation Board\n");
#else
puts("Board: iMX8QXP LPDDR4 ARM2\n");
#endif

2
board/freescale/imx8qxp_arm2/spl.c
View File

@ -65,7 +65,7 @@ DECLARE_GLOBAL_DATA_PTR;
static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = {
{USDHC1_BASE_ADDR, 0, 8},
#ifndef CONFIG_TARGET_IMX8DX_DDR3_ARM2
#ifndef CONFIG_TARGET_IMX8X_17X17_VAL
{USDHC2_BASE_ADDR, 0, 4},
#endif
};

5
configs/imx8dx_ddr3_arm2_defconfig → configs/imx8dx_17x17_val_defconfig
View File

@ -1,7 +1,8 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-ddr3-arm2"
CONFIG_TARGET_IMX8DX_DDR3_ARM2=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8dx-17x17-val"
CONFIG_TARGET_IMX8X_17X17_VAL=y
CONFIG_DEFAULT_FDT_FILE="fsl-imx8dx-17x17-val.dtb"
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_CMD_IMPORTENV=n
CONFIG_SYS_MALLOC_F_LEN=0x2000

99
configs/imx8qxp_17x17_val_defconfig Normal file
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@ -0,0 +1,99 @@
CONFIG_ARM=y
CONFIG_ARCH_IMX8=y
CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qxp-17x17-val"
CONFIG_TARGET_IMX8X_17X17_VAL=y
CONFIG_DEFAULT_FDT_FILE="fsl-imx8qxp-17x17-val.dtb"
CONFIG_SYS_TEXT_BASE=0x80020000
CONFIG_CMD_IMPORTENV=n
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_DM=y
CONFIG_CMD_CACHE=y
CONFIG_DM_SERIAL=y
CONFIG_FSL_LPUART=y
CONFIG_OF_CONTROL=y
CONFIG_DM_I2C=y
# CONFIG_DM_I2C_COMPAT is not set
CONFIG_SYS_I2C_IMX_LPI2C=y
CONFIG_CMD_I2C=y
CONFIG_FASTBOOT=y
CONFIG_USB_FUNCTION_FASTBOOT=y
CONFIG_CMD_FASTBOOT=y
CONFIG_ANDROID_BOOT_IMAGE=y
CONFIG_FSL_FASTBOOT=y
CONFIG_FASTBOOT_BUF_ADDR=0x82800000
CONFIG_FASTBOOT_BUF_SIZE=0x40000000
CONFIG_FASTBOOT_FLASH=y
CONFIG_FASTBOOT_FLASH_MMC_DEV=0
CONFIG_FASTBOOT_USB_DEV=0
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_IMX8=y
CONFIG_DM_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_CMD_USB=y
CONFIG_USB=y
CONFIG_USB_STORAGE=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_GADGET_MANUFACTURER="FSL"
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
# CONFIG_USB_CDNS3=y
# CONFIG_USB_CDNS3_GADGET=y
# CONFIG_USB_GADGET_DUALSPEED=y
CONFIG_CMD_GPIO=y
CONFIG_DM_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_BOOTDELAY=3
CONFIG_IMX_BOOTAUX=y
CONFIG_FS_FAT=y
CONFIG_CMD_FAT=y
CONFIG_CMD_MMC=y
CONFIG_DM_MMC=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_ES_SUPPORT=y
CONFIG_EFI_PARTITION=y
CONFIG_FSL_FSPI=y
CONFIG_DM_SPI=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_4BYTES_ADDR=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_CMD_SF=y
CONFIG_CMD_PING=y
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_DM_ETH=y
# CONFIG_EFI_LOADER is not set
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_VIDEO=y
CONFIG_PINCTRL=y
CONFIG_PINCTRL_IMX8=y
CONFIG_POWER_DOMAIN=y
CONFIG_IMX8_POWER_DOMAIN=y
CONFIG_DM_THERMAL=y
CONFIG_IMX_SC_THERMAL=y
CONFIG_ENV_IS_IN_MMC=y
CONFIG_SMC_FUSE=y
CONFIG_CMD_MEMTEST=y

7
include/configs/imx8qxp_arm2.h
View File

@ -322,7 +322,7 @@
/* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board
*/
#ifdef CONFIG_TARGET_IMX8DX_DDR3_ARM2
#ifdef CONFIG_TARGET_IMX8X_17X17_VAL
#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */
#define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */
#define CONFIG_SYS_FSL_USDHC_NUM 1
@ -339,9 +339,8 @@
#define CONFIG_NR_DRAM_BANKS 4
#define PHYS_SDRAM_1 0x80000000
#define PHYS_SDRAM_2 0x880000000
#if defined(CONFIG_TARGET_IMX8QXP_DDR3_ARM2) || defined(CONFIG_TARGET_IMX8DX_DDR3_ARM2)
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB */
/* LPDDR4 board total DDR is 3GB */
#if defined(CONFIG_TARGET_IMX8QXP_DDR3_ARM2) || defined(CONFIG_TARGET_IMX8X_17X17_VAL)
#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB totally */
#define PHYS_SDRAM_2_SIZE 0x00000000
#else
#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */