rockchip: rk3399: init CPU clock when rkclk_init()
Init the CPU and its buses to speed up the boot time. Move rkclk_init() to a place after rk3399_configure_cpu has defined at the same time, or else there will be a warning. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Kever Yang
Philipp Tomsich
parent
6e278a8c1c
commit
9f636a249c
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@ -398,84 +398,6 @@ static int pll_para_config(u32 freq_hz, struct pll_div *div)
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return 0;
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return 0;
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}
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}
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#ifdef CONFIG_SPL_BUILD
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static void rkclk_init(struct rk3399_cru *cru)
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{
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u32 aclk_div;
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u32 hclk_div;
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u32 pclk_div;
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/*
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* some cru registers changed by bootrom, we'd better reset them to
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* reset/default values described in TRM to avoid confusion in kernel.
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* Please consider these three lines as a fix of bootrom bug.
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*/
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rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
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rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
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rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
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/* configure gpll cpll */
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rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
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rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
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/* configure perihp aclk, hclk, pclk */
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aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
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assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
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PERIHP_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
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assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
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PERIHP_ACLK_HZ && (pclk_div < 0x7));
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rk_clrsetreg(&cru->clksel_con[14],
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PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
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ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
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pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
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hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
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ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
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aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
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/* configure perilp0 aclk, hclk, pclk */
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aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
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assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
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PERILP0_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
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assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
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PERILP0_ACLK_HZ && (pclk_div < 0x7));
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rk_clrsetreg(&cru->clksel_con[23],
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PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
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ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
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pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
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hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
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ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
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aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
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/* perilp1 hclk select gpll as source */
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hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
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assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
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GPLL_HZ && (hclk_div < 0x1f));
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pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
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assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
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PERILP1_HCLK_HZ && (hclk_div < 0x7));
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rk_clrsetreg(&cru->clksel_con[25],
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PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
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HCLK_PERILP1_PLL_SEL_MASK,
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pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
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hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
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HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
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}
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#endif
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void rk3399_configure_cpu(struct rk3399_cru *cru,
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void rk3399_configure_cpu(struct rk3399_cru *cru,
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enum apll_l_frequencies apll_l_freq)
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enum apll_l_frequencies apll_l_freq)
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{
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{
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@ -1004,6 +926,85 @@ static struct clk_ops rk3399_clk_ops = {
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.enable = rk3399_clk_enable,
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.enable = rk3399_clk_enable,
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};
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};
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#ifdef CONFIG_SPL_BUILD
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static void rkclk_init(struct rk3399_cru *cru)
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{
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u32 aclk_div;
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u32 hclk_div;
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u32 pclk_div;
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rk3399_configure_cpu(cru, APLL_L_600_MHZ);
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/*
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* some cru registers changed by bootrom, we'd better reset them to
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* reset/default values described in TRM to avoid confusion in kernel.
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* Please consider these three lines as a fix of bootrom bug.
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*/
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rk_clrsetreg(&cru->clksel_con[12], 0xffff, 0x4101);
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rk_clrsetreg(&cru->clksel_con[19], 0xffff, 0x033f);
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rk_clrsetreg(&cru->clksel_con[56], 0x0003, 0x0003);
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/* configure gpll cpll */
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rkclk_set_pll(&cru->gpll_con[0], &gpll_init_cfg);
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rkclk_set_pll(&cru->cpll_con[0], &cpll_init_cfg);
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/* configure perihp aclk, hclk, pclk */
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aclk_div = GPLL_HZ / PERIHP_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERIHP_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = PERIHP_ACLK_HZ / PERIHP_HCLK_HZ - 1;
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assert((hclk_div + 1) * PERIHP_HCLK_HZ ==
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PERIHP_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = PERIHP_ACLK_HZ / PERIHP_PCLK_HZ - 1;
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assert((pclk_div + 1) * PERIHP_PCLK_HZ ==
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PERIHP_ACLK_HZ && (pclk_div < 0x7));
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rk_clrsetreg(&cru->clksel_con[14],
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PCLK_PERIHP_DIV_CON_MASK | HCLK_PERIHP_DIV_CON_MASK |
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ACLK_PERIHP_PLL_SEL_MASK | ACLK_PERIHP_DIV_CON_MASK,
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pclk_div << PCLK_PERIHP_DIV_CON_SHIFT |
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hclk_div << HCLK_PERIHP_DIV_CON_SHIFT |
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ACLK_PERIHP_PLL_SEL_GPLL << ACLK_PERIHP_PLL_SEL_SHIFT |
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aclk_div << ACLK_PERIHP_DIV_CON_SHIFT);
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/* configure perilp0 aclk, hclk, pclk */
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aclk_div = GPLL_HZ / PERILP0_ACLK_HZ - 1;
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assert((aclk_div + 1) * PERILP0_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
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hclk_div = PERILP0_ACLK_HZ / PERILP0_HCLK_HZ - 1;
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assert((hclk_div + 1) * PERILP0_HCLK_HZ ==
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PERILP0_ACLK_HZ && (hclk_div < 0x4));
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pclk_div = PERILP0_ACLK_HZ / PERILP0_PCLK_HZ - 1;
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assert((pclk_div + 1) * PERILP0_PCLK_HZ ==
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PERILP0_ACLK_HZ && (pclk_div < 0x7));
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rk_clrsetreg(&cru->clksel_con[23],
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PCLK_PERILP0_DIV_CON_MASK | HCLK_PERILP0_DIV_CON_MASK |
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ACLK_PERILP0_PLL_SEL_MASK | ACLK_PERILP0_DIV_CON_MASK,
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pclk_div << PCLK_PERILP0_DIV_CON_SHIFT |
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hclk_div << HCLK_PERILP0_DIV_CON_SHIFT |
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ACLK_PERILP0_PLL_SEL_GPLL << ACLK_PERILP0_PLL_SEL_SHIFT |
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aclk_div << ACLK_PERILP0_DIV_CON_SHIFT);
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/* perilp1 hclk select gpll as source */
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hclk_div = GPLL_HZ / PERILP1_HCLK_HZ - 1;
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assert((hclk_div + 1) * PERILP1_HCLK_HZ ==
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GPLL_HZ && (hclk_div < 0x1f));
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pclk_div = PERILP1_HCLK_HZ / PERILP1_HCLK_HZ - 1;
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assert((pclk_div + 1) * PERILP1_HCLK_HZ ==
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PERILP1_HCLK_HZ && (hclk_div < 0x7));
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rk_clrsetreg(&cru->clksel_con[25],
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PCLK_PERILP1_DIV_CON_MASK | HCLK_PERILP1_DIV_CON_MASK |
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HCLK_PERILP1_PLL_SEL_MASK,
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pclk_div << PCLK_PERILP1_DIV_CON_SHIFT |
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hclk_div << HCLK_PERILP1_DIV_CON_SHIFT |
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HCLK_PERILP1_PLL_SEL_GPLL << HCLK_PERILP1_PLL_SEL_SHIFT);
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}
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#endif
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static int rk3399_clk_probe(struct udevice *dev)
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static int rk3399_clk_probe(struct udevice *dev)
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{
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{
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#ifdef CONFIG_SPL_BUILD
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#ifdef CONFIG_SPL_BUILD
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