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i.MX6: add enable_spi_clk() 

add enable_spi_clk(), so board code can enable spi clocks.

Signed-off-by: Heiko Schocher <hs@denx.de>
Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
Cc: Eric Nelson <eric.nelson@boundarydevices.com>
Cc: Stefano Babic <sbabic@denx.de>
This commit is contained in:
Heiko Schocher 2014-07-18 06:07:20 +02:00 committed by Stefano Babic
parent b2f97cf279
commit a0ae0091d7
3 changed files with 20 additions and 0 deletions
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18
arch/arm/cpu/armv7/mx6/clock.c
View File

@ -71,6 +71,24 @@ int enable_i2c_clk(unsigned char enable, unsigned i2c_num)
} }
#endif #endif
/* spi_num can be from 0 - SPI_MAX_NUM */
int enable_spi_clk(unsigned char enable, unsigned spi_num)
{
u32 reg;
u32 mask;
if (spi_num > SPI_MAX_NUM)
return -EINVAL;
mask = MXC_CCM_CCGR_CG_MASK << (spi_num << 1);
reg = __raw_readl(&imx_ccm->CCGR1);
if (enable)
reg |= mask;
else
reg &= ~mask;
__raw_writel(reg, &imx_ccm->CCGR1);
return 0;
}
static u32 decode_pll(enum pll_clocks pll, u32 infreq) static u32 decode_pll(enum pll_clocks pll, u32 infreq)
{ {
u32 div; u32 div;

1
arch/arm/include/asm/arch-mx6/clock.h
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@ -57,6 +57,7 @@ void enable_usboh3_clk(unsigned char enable);
int enable_sata_clock(void); int enable_sata_clock(void);
int enable_pcie_clock(void); int enable_pcie_clock(void);
int enable_i2c_clk(unsigned char enable, unsigned i2c_num); int enable_i2c_clk(unsigned char enable, unsigned i2c_num);
int enable_spi_clk(unsigned char enable, unsigned spi_num);
void enable_ipu_clock(void); void enable_ipu_clock(void);
int enable_fec_anatop_clock(enum enet_freq freq); int enable_fec_anatop_clock(enum enet_freq freq);
#endif /* __ASM_ARCH_CLOCK_H */ #endif /* __ASM_ARCH_CLOCK_H */

1
arch/arm/include/asm/arch-mx6/imx-regs.h
View File

@ -505,6 +505,7 @@ struct cspi_regs {
#define MXC_CSPICTRL_RXOVF (1 << 6) #define MXC_CSPICTRL_RXOVF (1 << 6)
#define MXC_CSPIPERIOD_32KHZ (1 << 15) #define MXC_CSPIPERIOD_32KHZ (1 << 15)
#define MAX_SPI_BYTES 32 #define MAX_SPI_BYTES 32
#define SPI_MAX_NUM 4
/* Bit position inside CTRL register to be associated with SS */ /* Bit position inside CTRL register to be associated with SS */
#define MXC_CSPICTRL_CHAN 18 #define MXC_CSPICTRL_CHAN 18