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imx: imx8mn-beacon: Fix out of spec voltage 

The DDR is configured for LPDDR4 running at 1.6GHz which requires
the voltage on the PMIC to rise a bit before initializing LPDDR4
or it will be running out of spec.

Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
This commit is contained in:
Adam Ford 2022-10-22 08:43:44 -05:00 committed by Stefano Babic
parent 4dbe07f275
commit a5685ea488
1 changed files with 35 additions and 0 deletions
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35
board/beacon/imx8mn/spl.c
View File

@ -74,6 +74,38 @@ static iomux_v3_cfg_t const pwm_pads[] = {
IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL), IMX8MN_PAD_GPIO1_IO01__PWM1_OUT | MUX_PAD_CTRL(PWM1_PAD_CTRL),
}; };
static int power_init_board(void)
{
struct udevice *dev;
int ret;
ret = pmic_get("pmic@4b", &dev);
if (ret == -ENODEV) {
puts("No pmic\n");
return 0;
}
if (ret != 0)
return ret;
/* decrease RESET key long push time from the default 10s to 10ms */
pmic_reg_write(dev, BD718XX_PWRONCONFIG1, 0x0);
/* unlock the PMIC regs */
pmic_reg_write(dev, BD718XX_REGLOCK, 0x1);
/* increase VDD_SOC to typical value 0.85v before first DRAM access */
pmic_reg_write(dev, BD718XX_BUCK1_VOLT_RUN, 0x0f);
/* increase VDD_DRAM to 0.975v for 3Ghz DDR */
pmic_reg_write(dev, BD718XX_1ST_NODVS_BUCK_VOLT, 0x83);
/* lock the PMIC regs */
pmic_reg_write(dev, BD718XX_REGLOCK, 0x11);
return 0;
}
int board_early_init_f(void) int board_early_init_f(void)
{ {
/* Claiming pwm pins prevents LCD flicker during startup*/ /* Claiming pwm pins prevents LCD flicker during startup*/
@ -107,6 +139,9 @@ void board_init_f(ulong dummy)
enable_tzc380(); enable_tzc380();
/* LPDDR4 at 1.6GHz requires a voltage adjustment on the PMIC */
power_init_board();
/* DDR initialization */ /* DDR initialization */
spl_dram_init(); spl_dram_init();