From a726a0c38b67221a8ec41080a71fcbb58230c78c Mon Sep 17 00:00:00 2001 From: Ye Li Date: Sun, 10 Feb 2019 19:17:18 -0800 Subject: [PATCH] MLK-20902 imx8mm_evk: Change VDD_DRAM to 0.975v According to latest datasheet IMX8MMCEC_Rev_0, the typical voltage of VDD_DRAM for 1.5GHz DDR clock is 0.95v. Because BD71847MWV PMIC does not support 0.95v output. We change the voltage to 0.975v as the note in datasheet mentioned it is acceptable and supported. Signed-off-by: Ye Li Reviewed-by: Bai Ping --- board/freescale/imx8mm_evk/spl.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/imx8mm_evk/spl.c b/board/freescale/imx8mm_evk/spl.c index 3a91f47f01..10f00a50d2 100644 --- a/board/freescale/imx8mm_evk/spl.c +++ b/board/freescale/imx8mm_evk/spl.c @@ -180,8 +180,8 @@ int power_init_board(void) /* increase VDD_SOC to typical value 0.85v before first DRAM access */ pmic_reg_write(p, BD71837_BUCK1_VOLT_RUN, 0x0f); - /* increase VDD_DRAM to 0.9v for 3Ghz DDR */ - pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x2); + /* increase VDD_DRAM to 0.975v for 3Ghz DDR */ + pmic_reg_write(p, BD71837_BUCK5_VOLT, 0x83); #ifndef CONFIG_IMX8M_LPDDR4 /* increase NVCC_DRAM_1V2 to 1.2v for DDR4 */