LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ulp_wdog: Update ulp wdog driver for 32bits command 

To use 32bits refresh and unlock command as default, check the CMD32EN
bit to select the corresponding commands.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Alice Guo <alice.guo@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Ye Li 2022-10-21 16:41:15 +08:00 committed by Stefan Roese
parent ddc8d36a74
commit a79f2007d0
1 changed files with 34 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
drivers/watchdog/ulp_wdog.c
View File

@ -28,11 +28,15 @@ struct wdog_regs {
#define UNLOCK_WORD0 0xC520 /* 1st unlock word */ #define UNLOCK_WORD0 0xC520 /* 1st unlock word */
#define UNLOCK_WORD1 0xD928 /* 2nd unlock word */ #define UNLOCK_WORD1 0xD928 /* 2nd unlock word */
#define UNLOCK_WORD 0xD928C520 /* unlock word */
#define REFRESH_WORD 0xB480A602 /* refresh word */
#define WDGCS_WDGE BIT(7) #define WDGCS_WDGE BIT(7)
#define WDGCS_WDGUPDATE BIT(5) #define WDGCS_WDGUPDATE BIT(5)
#define WDGCS_RCS BIT(10) #define WDGCS_RCS BIT(10)
#define WDGCS_ULK BIT(11) #define WDGCS_ULK BIT(11)
#define WDGCS_CMD32EN BIT(13)
#define WDGCS_FLG BIT(14) #define WDGCS_FLG BIT(14)
#define WDG_BUS_CLK (0x0) #define WDG_BUS_CLK (0x0)
@ -52,20 +56,30 @@ void hw_watchdog_reset(void)
{ {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
if (readl(&wdog->cs) & WDGCS_CMD32EN) {
writel(REFRESH_WORD, &wdog->cnt);
} else {
dmb(); dmb();
__raw_writel(REFRESH_WORD0, &wdog->cnt); __raw_writel(REFRESH_WORD0, &wdog->cnt);
__raw_writel(REFRESH_WORD1, &wdog->cnt); __raw_writel(REFRESH_WORD1, &wdog->cnt);
dmb(); dmb();
} }
}
void hw_watchdog_init(void) void hw_watchdog_init(void)
{ {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
u32 cmd32 = 0;
if (readl(&wdog->cs) & WDGCS_CMD32EN) {
writel(UNLOCK_WORD, &wdog->cnt);
cmd32 = WDGCS_CMD32EN;
} else {
dmb(); dmb();
__raw_writel(UNLOCK_WORD0, &wdog->cnt); __raw_writel(UNLOCK_WORD0, &wdog->cnt);
__raw_writel(UNLOCK_WORD1, &wdog->cnt); __raw_writel(UNLOCK_WORD1, &wdog->cnt);
dmb(); dmb();
}
/* Wait WDOG Unlock */ /* Wait WDOG Unlock */
while (!(readl(&wdog->cs) & WDGCS_ULK)) while (!(readl(&wdog->cs) & WDGCS_ULK))
@ -75,7 +89,7 @@ void hw_watchdog_init(void)
writel(0, &wdog->win); writel(0, &wdog->win);
/* setting 1-kHz clock source, enable counter running, and clear interrupt */ /* setting 1-kHz clock source, enable counter running, and clear interrupt */
writel((WDGCS_WDGE | WDGCS_WDGUPDATE |(WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs); writel((cmd32 | WDGCS_WDGE | WDGCS_WDGUPDATE | (WDG_LPO_CLK << 8) | WDGCS_FLG), &wdog->cs);
/* Wait WDOG reconfiguration */ /* Wait WDOG reconfiguration */
while (!(readl(&wdog->cs) & WDGCS_RCS)) while (!(readl(&wdog->cs) & WDGCS_RCS))
@ -87,11 +101,17 @@ void hw_watchdog_init(void)
void reset_cpu(void) void reset_cpu(void)
{ {
struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR; struct wdog_regs *wdog = (struct wdog_regs *)WDOG_BASE_ADDR;
u32 cmd32 = 0;
if (readl(&wdog->cs) & WDGCS_CMD32EN) {
writel(UNLOCK_WORD, &wdog->cnt);
cmd32 = WDGCS_CMD32EN;
} else {
dmb(); dmb();
__raw_writel(UNLOCK_WORD0, &wdog->cnt); __raw_writel(UNLOCK_WORD0, &wdog->cnt);
__raw_writel(UNLOCK_WORD1, &wdog->cnt); __raw_writel(UNLOCK_WORD1, &wdog->cnt);
dmb(); dmb();
}
/* Wait WDOG Unlock */ /* Wait WDOG Unlock */
while (!(readl(&wdog->cs) & WDGCS_ULK)) while (!(readl(&wdog->cs) & WDGCS_ULK))
@ -101,7 +121,7 @@ void reset_cpu(void)
writel(0, &wdog->win); writel(0, &wdog->win);
/* enable counter running */ /* enable counter running */
writel((WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs); writel((cmd32 | WDGCS_WDGE | (WDG_LPO_CLK << 8)), &wdog->cs);
/* Wait WDOG reconfiguration */ /* Wait WDOG reconfiguration */
while (!(readl(&wdog->cs) & WDGCS_RCS)) while (!(readl(&wdog->cs) & WDGCS_RCS))