mtd: nand: omap: remove unused #defines from common omap_gpmc.h
OMAP NAND driver can detect Page-size and OOB-size of NAND device from ONFI params or nand_id[] table. And based on that it defines ECC layout. This patch 1) removes following board configs used for defining NAND ECC layout - GPMC_NAND_ECC_LP_x16_LAYOUT (for large page x16 NAND) - GPMC_NAND_ECC_LP_x8_LAYOUT (for large page x8 NAND) - GPMC_NAND_ECC_SP_x16_LAYOUT (for small page x16 NAND) - GPMC_NAND_ECC_SP_x8_LAYOUT (for small page x8 NAND) 2) removes unused #defines in common omap_gpmc.h depending on above configs Build tested using: ./MAKEALL -s am33xx -s omap3 -s omap4 -s omap5 Signed-off-by: Pekon Gupta <pekon@ti.com>
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				|  | @ -12,53 +12,6 @@ | ||||||
| #define GPMC_BUF_EMPTY	0 | #define GPMC_BUF_EMPTY	0 | ||||||
| #define GPMC_BUF_FULL	1 | #define GPMC_BUF_FULL	1 | ||||||
| 
 | 
 | ||||||
| /* Generic ECC Layouts */ |  | ||||||
| /* Large Page x8 NAND device Layout */ |  | ||||||
| #ifdef GPMC_NAND_ECC_LP_x8_LAYOUT |  | ||||||
| #define GPMC_NAND_HW_ECC_LAYOUT {\ |  | ||||||
| 	.eccbytes = 12,\ |  | ||||||
| 	.eccpos = {1, 2, 3, 4, 5, 6, 7, 8,\ |  | ||||||
| 		9, 10, 11, 12},\ |  | ||||||
| 	.oobfree = {\ |  | ||||||
| 		{.offset = 13,\ |  | ||||||
| 		 .length = 51 } } \ |  | ||||||
| } |  | ||||||
| #endif |  | ||||||
| 
 |  | ||||||
| /* Large Page x16 NAND device Layout */ |  | ||||||
| #ifdef GPMC_NAND_ECC_LP_x16_LAYOUT |  | ||||||
| #define GPMC_NAND_HW_ECC_LAYOUT {\ |  | ||||||
| 	.eccbytes = 12,\ |  | ||||||
| 	.eccpos = {2, 3, 4, 5, 6, 7, 8, 9,\ |  | ||||||
| 		10, 11, 12, 13},\ |  | ||||||
| 	.oobfree = {\ |  | ||||||
| 		{.offset = 14,\ |  | ||||||
| 		 .length = 50 } } \ |  | ||||||
| } |  | ||||||
| #endif |  | ||||||
| 
 |  | ||||||
| /* Small Page x8 NAND device Layout */ |  | ||||||
| #ifdef GPMC_NAND_ECC_SP_x8_LAYOUT |  | ||||||
| #define GPMC_NAND_HW_ECC_LAYOUT {\ |  | ||||||
| 	.eccbytes = 3,\ |  | ||||||
| 	.eccpos = {1, 2, 3},\ |  | ||||||
| 	.oobfree = {\ |  | ||||||
| 		{.offset = 4,\ |  | ||||||
| 		 .length = 12 } } \ |  | ||||||
| } |  | ||||||
| #endif |  | ||||||
| 
 |  | ||||||
| /* Small Page x16 NAND device Layout */ |  | ||||||
| #ifdef GPMC_NAND_ECC_SP_x16_LAYOUT |  | ||||||
| #define GPMC_NAND_HW_ECC_LAYOUT {\ |  | ||||||
| 	.eccbytes = 3,\ |  | ||||||
| 	.eccpos = {2, 3, 4},\ |  | ||||||
| 	.oobfree = {\ |  | ||||||
| 		{.offset = 5,\ |  | ||||||
| 		 .length = 11 } } \ |  | ||||||
| } |  | ||||||
| #endif |  | ||||||
| 
 |  | ||||||
| enum omap_ecc { | enum omap_ecc { | ||||||
| 	/* 1-bit  ECC calculation by Software, Error detection by Software */ | 	/* 1-bit  ECC calculation by Software, Error detection by Software */ | ||||||
| 	OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ | 	OMAP_ECC_HAM1_CODE_SW = 1, /* avoid un-initialized int can be 0x0 */ | ||||||
|  |  | ||||||
|  | @ -404,7 +404,6 @@ | ||||||
| /* NAND support */ | /* NAND support */ | ||||||
| #ifdef CONFIG_NAND | #ifdef CONFIG_NAND | ||||||
| #define CONFIG_CMD_NAND | #define CONFIG_CMD_NAND | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT	1 |  | ||||||
| #if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) | #if !defined(CONFIG_SPI_BOOT) && !defined(CONFIG_NOR_BOOT) | ||||||
| #define MTDIDS_DEFAULT			"nand0=omap2-nand.0" | #define MTDIDS_DEFAULT			"nand0=omap2-nand.0" | ||||||
| #define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:128k(SPL)," \ | #define MTDPARTS_DEFAULT		"mtdparts=omap2-nand.0:128k(SPL)," \ | ||||||
|  |  | ||||||
|  | @ -188,7 +188,6 @@ | ||||||
| #define CONFIG_NAND | #define CONFIG_NAND | ||||||
| #define CONFIG_NAND_OMAP_GPMC | #define CONFIG_NAND_OMAP_GPMC | ||||||
| #define CONFIG_NAND_OMAP_ELM | #define CONFIG_NAND_OMAP_ELM | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT	1 |  | ||||||
| #define CONFIG_SYS_NAND_BASE		(0x08000000)	/* phys address CS0 */ | #define CONFIG_SYS_NAND_BASE		(0x08000000)	/* phys address CS0 */ | ||||||
| #define CONFIG_SYS_MAX_NAND_DEVICE	1 | #define CONFIG_SYS_MAX_NAND_DEVICE	1 | ||||||
| #define CONFIG_SYS_NAND_ONFI_DETECTION	1 | #define CONFIG_SYS_NAND_ONFI_DETECTION	1 | ||||||
|  |  | ||||||
|  | @ -268,7 +268,6 @@ | ||||||
| #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE | #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE | ||||||
| 
 | 
 | ||||||
| #define CONFIG_NAND_OMAP_GPMC | #define CONFIG_NAND_OMAP_GPMC | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT	1 |  | ||||||
| #define CONFIG_ENV_IS_IN_NAND		1 | #define CONFIG_ENV_IS_IN_NAND		1 | ||||||
| #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */ | #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */ | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
|  | @ -277,7 +277,6 @@ | ||||||
| #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE | #define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_FLASH_BASE | ||||||
| 
 | 
 | ||||||
| #define CONFIG_NAND_OMAP_GPMC | #define CONFIG_NAND_OMAP_GPMC | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT	1 |  | ||||||
| #define CONFIG_ENV_IS_IN_NAND		1 | #define CONFIG_ENV_IS_IN_NAND		1 | ||||||
| #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */ | #define SMNAND_ENV_OFFSET		0x260000 /* environment starts here */ | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
|  | @ -156,8 +156,6 @@ | ||||||
| #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | ||||||
| 							/* to access nand at */ | 							/* to access nand at */ | ||||||
| 							/* CS0 */ | 							/* CS0 */ | ||||||
| #define GPMC_NAND_ECC_LP_x8_LAYOUT |  | ||||||
| 
 |  | ||||||
| #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */ | #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */ | ||||||
| 							/* devices */ | 							/* devices */ | ||||||
| /* Environment information */ | /* Environment information */ | ||||||
|  |  | ||||||
|  | @ -116,8 +116,6 @@ | ||||||
| #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | ||||||
| 							/* to access nand at */ | 							/* to access nand at */ | ||||||
| 							/* CS0 */ | 							/* CS0 */ | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT	1 |  | ||||||
| 
 |  | ||||||
| #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */ | #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */ | ||||||
| 							/* devices */ | 							/* devices */ | ||||||
| #define CONFIG_JFFS2_NAND | #define CONFIG_JFFS2_NAND | ||||||
|  |  | ||||||
|  | @ -143,8 +143,6 @@ | ||||||
| #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | ||||||
| 							/* to access nand at */ | 							/* to access nand at */ | ||||||
| 							/* CS0 */ | 							/* CS0 */ | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT |  | ||||||
| 
 |  | ||||||
| #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */ | #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */ | ||||||
| 
 | 
 | ||||||
| #if defined(CONFIG_CMD_NET) | #if defined(CONFIG_CMD_NET) | ||||||
|  |  | ||||||
|  | @ -321,7 +321,6 @@ | ||||||
| #define PISMO1_NAND_SIZE		GPMC_SIZE_128M | #define PISMO1_NAND_SIZE		GPMC_SIZE_128M | ||||||
| 
 | 
 | ||||||
| #define CONFIG_NAND_OMAP_GPMC | #define CONFIG_NAND_OMAP_GPMC | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT |  | ||||||
| #define CONFIG_ENV_IS_IN_NAND | #define CONFIG_ENV_IS_IN_NAND | ||||||
| #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */ | #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */ | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
|  | @ -183,8 +183,6 @@ | ||||||
| #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | ||||||
| 							/* to access nand at */ | 							/* to access nand at */ | ||||||
| 							/* CS0 */ | 							/* CS0 */ | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT	1 |  | ||||||
| 
 |  | ||||||
| #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */ | #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */ | ||||||
| 							/* devices */ | 							/* devices */ | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
|  | @ -208,7 +208,6 @@ | ||||||
| #define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE | #define CONFIG_SYS_FLASH_BASE		PISMO1_NAND_BASE | ||||||
| 
 | 
 | ||||||
| #define CONFIG_NAND_OMAP_GPMC | #define CONFIG_NAND_OMAP_GPMC | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT |  | ||||||
| #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET | #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET | ||||||
| #elif defined(CONFIG_CMD_ONENAND) | #elif defined(CONFIG_CMD_ONENAND) | ||||||
| #define CONFIG_SYS_FLASH_BASE		PISMO1_ONEN_BASE | #define CONFIG_SYS_FLASH_BASE		PISMO1_ONEN_BASE | ||||||
|  |  | ||||||
|  | @ -154,7 +154,6 @@ | ||||||
| 
 | 
 | ||||||
| #ifdef CONFIG_NAND | #ifdef CONFIG_NAND | ||||||
| #define PISMO1_NAND_SIZE		GPMC_SIZE_128M /* Configure the PISMO */ | #define PISMO1_NAND_SIZE		GPMC_SIZE_128M /* Configure the PISMO */ | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT	1 |  | ||||||
| #define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */ | #define CONFIG_ENV_OFFSET		0x260000 /* environment starts here */ | ||||||
| #define CONFIG_ENV_IS_IN_NAND	        1 | #define CONFIG_ENV_IS_IN_NAND	        1 | ||||||
| #define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */ | #define CONFIG_ENV_SIZE			(512 << 10) /* Total Size Environment */ | ||||||
|  |  | ||||||
|  | @ -295,7 +295,6 @@ | ||||||
| 
 | 
 | ||||||
| #if defined(CONFIG_CMD_NAND) | #if defined(CONFIG_CMD_NAND) | ||||||
| #define CONFIG_NAND_OMAP_GPMC | #define CONFIG_NAND_OMAP_GPMC | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT	1 |  | ||||||
| #define CONFIG_ENV_IS_IN_NAND | #define CONFIG_ENV_IS_IN_NAND | ||||||
| #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET | #define CONFIG_ENV_OFFSET		SMNAND_ENV_OFFSET | ||||||
| #endif | #endif | ||||||
|  |  | ||||||
|  | @ -119,8 +119,6 @@ | ||||||
| #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | ||||||
| 							/* to access nand */ | 							/* to access nand */ | ||||||
| 							/* at CS0 */ | 							/* at CS0 */ | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT |  | ||||||
| 
 |  | ||||||
| #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */ | #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */ | ||||||
| 						/* devices */ | 						/* devices */ | ||||||
| #define CONFIG_JFFS2_NAND | #define CONFIG_JFFS2_NAND | ||||||
|  |  | ||||||
|  | @ -131,8 +131,6 @@ | ||||||
| #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | ||||||
| 							/* to access nand */ | 							/* to access nand */ | ||||||
| 							/* at CS0 */ | 							/* at CS0 */ | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT	1 |  | ||||||
| 
 |  | ||||||
| #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */ | #define CONFIG_SYS_MAX_NAND_DEVICE	1	/* Max number of NAND */ | ||||||
| 						/* devices */ | 						/* devices */ | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
|  | @ -138,8 +138,6 @@ | ||||||
| #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | ||||||
| 							/* to access nand at */ | 							/* to access nand at */ | ||||||
| 							/* CS0 */ | 							/* CS0 */ | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT	1 |  | ||||||
| 
 |  | ||||||
| #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */ | #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */ | ||||||
| 							/* devices */ | 							/* devices */ | ||||||
| #define CONFIG_JFFS2_NAND | #define CONFIG_JFFS2_NAND | ||||||
|  |  | ||||||
|  | @ -457,7 +457,6 @@ | ||||||
| 
 | 
 | ||||||
| #define CONFIG_NAND_OMAP_GPMC | #define CONFIG_NAND_OMAP_GPMC | ||||||
| #define CONFIG_NAND_OMAP_ELM | #define CONFIG_NAND_OMAP_ELM | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT	1 |  | ||||||
| #define CONFIG_SYS_NAND_BASE		(0x08000000)	/* physical address */ | #define CONFIG_SYS_NAND_BASE		(0x08000000)	/* physical address */ | ||||||
| 							/* to access nand at */ | 							/* to access nand at */ | ||||||
| 							/* CS0 */ | 							/* CS0 */ | ||||||
|  |  | ||||||
|  | @ -186,7 +186,6 @@ | ||||||
| #define PISMO1_NAND_SIZE		GPMC_SIZE_128M | #define PISMO1_NAND_SIZE		GPMC_SIZE_128M | ||||||
| 
 | 
 | ||||||
| #define CONFIG_NAND_OMAP_GPMC | #define CONFIG_NAND_OMAP_GPMC | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT |  | ||||||
| #define CONFIG_ENV_IS_IN_NAND | #define CONFIG_ENV_IS_IN_NAND | ||||||
| #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */ | #define SMNAND_ENV_OFFSET		0x180000 /* environment starts here */ | ||||||
| 
 | 
 | ||||||
|  |  | ||||||
|  | @ -134,8 +134,6 @@ | ||||||
| #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | #define CONFIG_SYS_NAND_BASE		NAND_BASE	/* physical address */ | ||||||
| 							/* to access nand at */ | 							/* to access nand at */ | ||||||
| 							/* CS0 */ | 							/* CS0 */ | ||||||
| #define GPMC_NAND_ECC_LP_x16_LAYOUT	1 |  | ||||||
| 
 |  | ||||||
| #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */ | #define CONFIG_SYS_MAX_NAND_DEVICE	1		/* Max number of NAND */ | ||||||
| 							/* devices */ | 							/* devices */ | ||||||
| #define CONFIG_BCH | #define CONFIG_BCH | ||||||
|  |  | ||||||
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