ppc: Remove controlcenterd boards
These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. Cc: Mario Six <mario.six@gdsys.cc> Cc: Dirk Eibach <dirk.eibach@gdsys.cc> Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini
parent
7c964c3b93
commit
a84ea228bc
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@ -226,10 +226,6 @@ config TARGET_T4240RDB
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imply CMD_SATA
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imply CMD_SATA
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imply PANIC_HANG
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imply PANIC_HANG
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config TARGET_CONTROLCENTERD
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bool "Support controlcenterd"
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select ARCH_P1022
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config TARGET_KMP204X
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config TARGET_KMP204X
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bool "Support kmp204x"
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bool "Support kmp204x"
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select VENDOR_KM
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select VENDOR_KM
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@ -1395,7 +1391,6 @@ source "board/freescale/t104xrdb/Kconfig"
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source "board/freescale/t208xqds/Kconfig"
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source "board/freescale/t208xqds/Kconfig"
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source "board/freescale/t208xrdb/Kconfig"
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source "board/freescale/t208xrdb/Kconfig"
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source "board/freescale/t4rdb/Kconfig"
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source "board/freescale/t4rdb/Kconfig"
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source "board/gdsys/p1022/Kconfig"
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source "board/keymile/Kconfig"
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source "board/keymile/Kconfig"
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source "board/sbc8548/Kconfig"
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source "board/sbc8548/Kconfig"
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source "board/socrates/Kconfig"
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source "board/socrates/Kconfig"
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@ -1,22 +0,0 @@
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config GDSYS_LEGACY_DRIVERS
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bool
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help
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Enable the gdsys legacy drivers under board/gdsys/common. If this
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option is not set, all relevant DM drivers must be configured for the
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device in question.
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if TARGET_CONTROLCENTERD
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config SYS_BOARD
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default "p1022"
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config SYS_VENDOR
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default "gdsys"
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config SYS_CONFIG_NAME
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default "controlcenterd"
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config GDSYS_LEGACY_DRIVERS
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default y
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endif
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@ -1,9 +0,0 @@
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P1022 BOARD
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M: Dirk Eibach <dirk.eibach@gdsys.cc>
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S: Maintained
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F: board/gdsys/p1022/
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F: include/configs/controlcenterd.h
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F: configs/controlcenterd_36BIT_SDCARD_defconfig
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F: configs/controlcenterd_36BIT_SDCARD_DEVELOP_defconfig
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F: configs/controlcenterd_TRAILBLAZER_defconfig
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F: configs/controlcenterd_TRAILBLAZER_DEVELOP_defconfig
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@ -1,10 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2010 Freescale Semiconductor, Inc.
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obj-y += law.o
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obj-y += ddr.o
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obj-y += tlb.o
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obj-y += sdhc_boot.o
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obj-$(CONFIG_CONTROLCENTERD) += controlcenterd.o controlcenterd-id.o
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obj-$(CONFIG_FSL_DIU_FB) += diu.o
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File diff suppressed because it is too large
Load Diff
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@ -1,15 +0,0 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* (C) Copyright 2013
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* Reinhard Pfau, Guntermann & Drunck GmbH, reinhard.pfau@gdsys.cc
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*/
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#ifndef __CONTROLCENTER_ID_H
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#define __CONTROLCENTER_ID_H
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int ccdm_compute_self_hash(void);
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int startup_ccdm_id_module(void);
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int show_self_hash(void);
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#endif /* __CONTROLCENTER_ID_H */
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@ -1,431 +0,0 @@
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/*
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* (C) Copyright 2013
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* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <env.h>
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#include <image.h>
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#include <init.h>
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#include <net.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/fsl_serdes.h>
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#include <asm/io.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <asm/fsl_law.h>
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#include <netdev.h>
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#include <i2c.h>
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#include <pca9698.h>
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#include <watchdog.h>
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#include "../common/dp501.h"
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#include "controlcenterd-id.h"
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enum {
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HWVER_100 = 0,
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HWVER_110 = 1,
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HWVER_120 = 2,
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};
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struct ihs_fpga {
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u32 reflection_low; /* 0x0000 */
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u32 versions; /* 0x0004 */
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u32 fpga_version; /* 0x0008 */
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u32 fpga_features; /* 0x000c */
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u32 reserved[4]; /* 0x0010 */
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u32 control; /* 0x0020 */
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};
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#ifndef CONFIG_TRAILBLAZER
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static struct pci_device_id hydra_supported[] = {
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{ 0x6d5e, 0xcdc0 },
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{}
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};
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static void hydra_initialize(void);
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#endif
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int board_early_init_f(void)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
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/* Reset eLBC_DIU and SPI_eLBC in case we are booting from SD */
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clrsetbits_be32(&gur->pmuxcr, 0x00600000, 0x80000000);
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/* Set pmuxcr to allow both i2c1 and i2c2 */
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setbits_be32(&gur->pmuxcr, 0x00001000);
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/* Set pmuxcr to enable GPIO 3_11-3_13 */
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setbits_be32(&gur->pmuxcr, 0x00000010);
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/* Set pmuxcr to enable GPIO 2_31,3_9+10 */
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setbits_be32(&gur->pmuxcr, 0x00000020);
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/* Set pmuxcr to enable GPIO 2_28-2_30 */
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setbits_be32(&gur->pmuxcr, 0x000000c0);
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/* Set pmuxcr to enable GPIO 3_20-3_22 */
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setbits_be32(&gur->pmuxcr2, 0x03000000);
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/* Set pmuxcr to enable IRQ0-2 */
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clrbits_be32(&gur->pmuxcr, 0x00000300);
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/* Set pmuxcr to disable IRQ3-11 */
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setbits_be32(&gur->pmuxcr, 0x000000F0);
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/* Read back the register to synchronize the write. */
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in_be32(&gur->pmuxcr);
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/* Set the pin muxing to enable ETSEC2. */
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clrbits_be32(&gur->pmuxcr2, 0x001F8000);
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#ifdef CONFIG_TRAILBLAZER
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/*
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* GPIO3_10 SPERRTRIGGER
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*/
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setbits_be32(&pgpio->gpdir, 0x00200000);
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clrbits_be32(&pgpio->gpdat, 0x00200000);
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udelay(100);
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setbits_be32(&pgpio->gpdat, 0x00200000);
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udelay(100);
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clrbits_be32(&pgpio->gpdat, 0x00200000);
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#endif
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/*
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* GPIO3_11 CPU-TO-FPGA-RESET#
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*/
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setbits_be32(&pgpio->gpdir, 0x00100000);
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clrbits_be32(&pgpio->gpdat, 0x00100000);
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/*
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* GPIO3_21 CPU-STATUS-WATCHDOG-TRIGGER#
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*/
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setbits_be32(&pgpio->gpdir, 0x00000400);
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return 0;
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}
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int checkboard(void)
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{
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printf("Board: ControlCenter DIGITAL\n");
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return 0;
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}
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int misc_init_r(void)
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{
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return 0;
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}
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/*
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* A list of PCI and SATA slots
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*/
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enum slot_id {
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SLOT_PCIE1 = 1,
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SLOT_PCIE2,
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SLOT_PCIE3,
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SLOT_PCIE4,
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SLOT_PCIE5,
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SLOT_SATA1,
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SLOT_SATA2
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};
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/*
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* This array maps the slot identifiers to their names on the P1022DS board.
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*/
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static const char * const slot_names[] = {
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[SLOT_PCIE1] = "Slot 1",
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[SLOT_PCIE2] = "Slot 2",
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[SLOT_PCIE3] = "Slot 3",
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[SLOT_PCIE4] = "Slot 4",
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[SLOT_PCIE5] = "Mini-PCIe",
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[SLOT_SATA1] = "SATA 1",
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[SLOT_SATA2] = "SATA 2",
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};
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/*
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* This array maps a given SERDES configuration and SERDES device to the PCI or
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* SATA slot that it connects to. This mapping is hard-coded in the FPGA.
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*/
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static u8 serdes_dev_slot[][SATA2 + 1] = {
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[0x01] = { [PCIE3] = SLOT_PCIE4, [PCIE2] = SLOT_PCIE5 },
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[0x02] = { [SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x09] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE4,
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[PCIE2] = SLOT_PCIE5 },
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[0x16] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
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[PCIE2] = SLOT_PCIE3,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x17] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE2,
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[PCIE2] = SLOT_PCIE3 },
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[0x1a] = { [PCIE1] = SLOT_PCIE1, [PCIE2] = SLOT_PCIE3,
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[PCIE2] = SLOT_PCIE3,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x1c] = { [PCIE1] = SLOT_PCIE1,
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[SATA1] = SLOT_SATA1, [SATA2] = SLOT_SATA2 },
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[0x1e] = { [PCIE1] = SLOT_PCIE1, [PCIE3] = SLOT_PCIE3 },
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[0x1f] = { [PCIE1] = SLOT_PCIE1 },
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};
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/*
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* Returns the name of the slot to which the PCIe or SATA controller is
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* connected
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*/
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const char *board_serdes_name(enum srds_prtcl device)
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{
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ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
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u32 pordevsr = in_be32(&gur->pordevsr);
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unsigned int srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >>
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MPC85xx_PORDEVSR_IO_SEL_SHIFT;
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enum slot_id slot = serdes_dev_slot[srds_cfg][device];
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const char *name = slot_names[slot];
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if (name)
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return name;
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else
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return "Nothing";
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}
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void hw_watchdog_reset(void)
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{
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
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clrbits_be32(&pgpio->gpdat, 0x00000400);
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setbits_be32(&pgpio->gpdat, 0x00000400);
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}
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#ifdef CONFIG_TRAILBLAZER
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int do_bootd(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
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{
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return run_command(env_get("bootcmd"), flag);
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}
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int board_early_init_r(void)
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{
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
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/*
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* GPIO3_12 PPC_SYSTEMREADY#
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*/
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setbits_be32(&pgpio->gpdir, 0x00080000);
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setbits_be32(&pgpio->gpodr, 0x00080000);
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clrbits_be32(&pgpio->gpdat, 0x00080000);
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return ccdm_compute_self_hash();
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}
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int last_stage_init(void)
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{
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startup_ccdm_id_module();
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return 0;
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}
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#else
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void pci_init_board(void)
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{
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fsl_pcie_init_board(0);
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hydra_initialize();
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}
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int board_early_init_r(void)
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{
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unsigned int k = 0;
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ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO3_ADDR);
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/* wait for FPGA configuration to finish */
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while (!pca9698_get_value(0x22, 11) && (k++ < 30))
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udelay(100000);
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if (k > 30) {
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puts("FPGA configuration timed out.\n");
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} else {
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/* clear FPGA reset */
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udelay(1000);
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setbits_be32(&pgpio->gpdat, 0x00100000);
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}
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/* give time for PCIe link training */
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udelay(100000);
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/*
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* GPIO3_12 PPC_SYSTEMREADY#
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|
||||||
*/
|
|
||||||
setbits_be32(&pgpio->gpdir, 0x00080000);
|
|
||||||
setbits_be32(&pgpio->gpodr, 0x00080000);
|
|
||||||
clrbits_be32(&pgpio->gpdat, 0x00080000);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
int last_stage_init(void)
|
|
||||||
{
|
|
||||||
/* Turn on Parade DP501 */
|
|
||||||
pca9698_direction_output(0x22, 7, 1);
|
|
||||||
udelay(500000);
|
|
||||||
|
|
||||||
dp501_powerup(0x08);
|
|
||||||
|
|
||||||
startup_ccdm_id_module();
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Initialize on-board and/or PCI Ethernet devices
|
|
||||||
*
|
|
||||||
* Returns:
|
|
||||||
* <0, error
|
|
||||||
* 0, no ethernet devices found
|
|
||||||
* >0, number of ethernet devices initialized
|
|
||||||
*/
|
|
||||||
int board_eth_init(struct bd_info *bis)
|
|
||||||
{
|
|
||||||
struct fsl_pq_mdio_info mdio_info;
|
|
||||||
struct tsec_info_struct tsec_info[2];
|
|
||||||
unsigned int num = 0;
|
|
||||||
|
|
||||||
#ifdef CONFIG_TSEC1
|
|
||||||
SET_STD_TSEC_INFO(tsec_info[num], 1);
|
|
||||||
num++;
|
|
||||||
#endif
|
|
||||||
#ifdef CONFIG_TSEC2
|
|
||||||
SET_STD_TSEC_INFO(tsec_info[num], 2);
|
|
||||||
num++;
|
|
||||||
#endif
|
|
||||||
|
|
||||||
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
|
|
||||||
mdio_info.name = DEFAULT_MII_NAME;
|
|
||||||
fsl_pq_mdio_init(bis, &mdio_info);
|
|
||||||
|
|
||||||
return tsec_eth_init(bis, tsec_info, num) + pci_eth_init(bis);
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_OF_BOARD_SETUP
|
|
||||||
int ft_board_setup(void *blob, struct bd_info *bd)
|
|
||||||
{
|
|
||||||
phys_addr_t base;
|
|
||||||
phys_size_t size;
|
|
||||||
|
|
||||||
ft_cpu_setup(blob, bd);
|
|
||||||
|
|
||||||
base = env_get_bootm_low();
|
|
||||||
size = env_get_bootm_size();
|
|
||||||
|
|
||||||
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
|
||||||
|
|
||||||
#ifdef CONFIG_HAS_FSL_DR_USB
|
|
||||||
fsl_fdt_fixup_dr_usb(blob, bd);
|
|
||||||
#endif
|
|
||||||
|
|
||||||
FT_FSL_PCI_SETUP;
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
||||||
static void hydra_initialize(void)
|
|
||||||
{
|
|
||||||
unsigned int i;
|
|
||||||
pci_dev_t devno;
|
|
||||||
|
|
||||||
/* Find and probe all the matching PCI devices */
|
|
||||||
for (i = 0; (devno = pci_find_devices(hydra_supported, i)) >= 0; i++) {
|
|
||||||
u32 val;
|
|
||||||
struct ihs_fpga *fpga;
|
|
||||||
u32 versions;
|
|
||||||
u32 fpga_version;
|
|
||||||
u32 fpga_features;
|
|
||||||
|
|
||||||
unsigned hardware_version;
|
|
||||||
unsigned feature_uart_channels;
|
|
||||||
unsigned feature_sb_channels;
|
|
||||||
|
|
||||||
/* Try to enable I/O accesses and bus-mastering */
|
|
||||||
val = PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
|
|
||||||
pci_write_config_dword(devno, PCI_COMMAND, val);
|
|
||||||
|
|
||||||
/* Make sure it worked */
|
|
||||||
pci_read_config_dword(devno, PCI_COMMAND, &val);
|
|
||||||
if (!(val & PCI_COMMAND_MEMORY)) {
|
|
||||||
puts("Can't enable I/O memory\n");
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
if (!(val & PCI_COMMAND_MASTER)) {
|
|
||||||
puts("Can't enable bus-mastering\n");
|
|
||||||
continue;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* read FPGA details */
|
|
||||||
fpga = pci_map_bar(devno, PCI_BASE_ADDRESS_0,
|
|
||||||
PCI_REGION_MEM);
|
|
||||||
|
|
||||||
/* disable sideband clocks */
|
|
||||||
writel(1, &fpga->control);
|
|
||||||
|
|
||||||
versions = readl(&fpga->versions);
|
|
||||||
fpga_version = readl(&fpga->fpga_version);
|
|
||||||
fpga_features = readl(&fpga->fpga_features);
|
|
||||||
|
|
||||||
hardware_version = versions & 0xf;
|
|
||||||
feature_uart_channels = (fpga_features >> 6) & 0x1f;
|
|
||||||
feature_sb_channels = fpga_features & 0x1f;
|
|
||||||
|
|
||||||
printf("FPGA%d: ", i);
|
|
||||||
|
|
||||||
switch (hardware_version) {
|
|
||||||
case HWVER_100:
|
|
||||||
printf("HW-Ver 1.00\n");
|
|
||||||
break;
|
|
||||||
|
|
||||||
case HWVER_110:
|
|
||||||
printf("HW-Ver 1.10\n");
|
|
||||||
break;
|
|
||||||
|
|
||||||
case HWVER_120:
|
|
||||||
printf("HW-Ver 1.20\n");
|
|
||||||
break;
|
|
||||||
|
|
||||||
default:
|
|
||||||
printf("HW-Ver %d(not supported)\n",
|
|
||||||
hardware_version);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
|
|
||||||
printf(" FPGA V %d.%02d, features:",
|
|
||||||
fpga_version / 100, fpga_version % 100);
|
|
||||||
|
|
||||||
printf(" %d uart channel(s)", feature_uart_channels);
|
|
||||||
printf(" %d sideband channel(s)\n", feature_sb_channels);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,68 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2010 Freescale Semiconductor, Inc.
|
|
||||||
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
|
|
||||||
* Timur Tabi <timur@freescale.com>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <i2c.h>
|
|
||||||
#include <log.h>
|
|
||||||
|
|
||||||
#include <fsl_ddr_sdram.h>
|
|
||||||
#include <fsl_ddr_dimm_params.h>
|
|
||||||
|
|
||||||
void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm,
|
|
||||||
unsigned int ctrl_num)
|
|
||||||
{
|
|
||||||
unsigned int i;
|
|
||||||
|
|
||||||
if (ctrl_num) {
|
|
||||||
printf("Wrong parameter for controller number %d", ctrl_num);
|
|
||||||
return;
|
|
||||||
}
|
|
||||||
if (!pdimm->n_ranks)
|
|
||||||
return;
|
|
||||||
|
|
||||||
/* set odt_rd_cfg and odt_wr_cfg. */
|
|
||||||
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
|
|
||||||
popts->cs_local_opts[i].odt_rd_cfg = 0;
|
|
||||||
popts->cs_local_opts[i].odt_wr_cfg = 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
popts->clk_adjust = 5;
|
|
||||||
popts->cpo_override = 0x1f;
|
|
||||||
popts->write_data_delay = 2;
|
|
||||||
popts->half_strength_driver_enable = 1;
|
|
||||||
|
|
||||||
/* Per AN4039, enable ZQ calibration. */
|
|
||||||
popts->zq_en = 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPD_EEPROM
|
|
||||||
/*
|
|
||||||
* we only have a "fake" SPD-EEPROM here, which has 16 bit addresses
|
|
||||||
*/
|
|
||||||
void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
|
|
||||||
{
|
|
||||||
int ret = i2c_read(i2c_address, 0, 2, (uchar *)spd,
|
|
||||||
sizeof(generic_spd_eeprom_t));
|
|
||||||
|
|
||||||
if (ret) {
|
|
||||||
if (i2c_address ==
|
|
||||||
#ifdef SPD_EEPROM_ADDRESS
|
|
||||||
SPD_EEPROM_ADDRESS
|
|
||||||
#elif defined(SPD_EEPROM_ADDRESS1)
|
|
||||||
SPD_EEPROM_ADDRESS1
|
|
||||||
#endif
|
|
||||||
) {
|
|
||||||
printf("DDR: failed to read SPD from address %u\n",
|
|
||||||
i2c_address);
|
|
||||||
} else {
|
|
||||||
debug("DDR: failed to read SPD from address %u\n",
|
|
||||||
i2c_address);
|
|
||||||
}
|
|
||||||
memset(spd, 0, sizeof(generic_spd_eeprom_t));
|
|
||||||
}
|
|
||||||
}
|
|
||||||
#endif
|
|
||||||
|
|
@ -1,85 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2010-2011 Freescale Semiconductor, Inc.
|
|
||||||
* Authors: Timur Tabi <timur@freescale.com>
|
|
||||||
*
|
|
||||||
* FSL DIU Framebuffer driver
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <clock_legacy.h>
|
|
||||||
#include <command.h>
|
|
||||||
#include <log.h>
|
|
||||||
#include <linux/ctype.h>
|
|
||||||
#include <asm/io.h>
|
|
||||||
#include <stdio_dev.h>
|
|
||||||
#include <video_fb.h>
|
|
||||||
#include <fsl_diu_fb.h>
|
|
||||||
|
|
||||||
#define PMUXCR_ELBCDIU_MASK 0xc0000000
|
|
||||||
#define PMUXCR_ELBCDIU_NOR16 0x80000000
|
|
||||||
#define PMUXCR_ELBCDIU_DIU 0x40000000
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DIU Area Descriptor
|
|
||||||
*
|
|
||||||
* Note that we need to byte-swap the value before it's written to the AD
|
|
||||||
* register. So even though the registers don't look like they're in the same
|
|
||||||
* bit positions as they are on the MPC8610, the same value is written to the
|
|
||||||
* AD register on the MPC8610 and on the P1022.
|
|
||||||
*/
|
|
||||||
#define AD_BYTE_F 0x10000000
|
|
||||||
#define AD_ALPHA_C_SHIFT 25
|
|
||||||
#define AD_BLUE_C_SHIFT 23
|
|
||||||
#define AD_GREEN_C_SHIFT 21
|
|
||||||
#define AD_RED_C_SHIFT 19
|
|
||||||
#define AD_PIXEL_S_SHIFT 16
|
|
||||||
#define AD_COMP_3_SHIFT 12
|
|
||||||
#define AD_COMP_2_SHIFT 8
|
|
||||||
#define AD_COMP_1_SHIFT 4
|
|
||||||
#define AD_COMP_0_SHIFT 0
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Variables used by the DIU/LBC switching code. It's safe to makes these
|
|
||||||
* global, because the DIU requires DDR, so we'll only run this code after
|
|
||||||
* relocation.
|
|
||||||
*/
|
|
||||||
static u32 pmuxcr;
|
|
||||||
|
|
||||||
void diu_set_pixel_clock(unsigned int pixclock)
|
|
||||||
{
|
|
||||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
||||||
unsigned long speed_ccb, temp;
|
|
||||||
u32 pixval;
|
|
||||||
|
|
||||||
speed_ccb = get_bus_freq(0);
|
|
||||||
temp = 1000000000 / pixclock;
|
|
||||||
temp *= 1000;
|
|
||||||
pixval = speed_ccb / temp;
|
|
||||||
debug("DIU pixval = %u\n", pixval);
|
|
||||||
|
|
||||||
/* Modify PXCLK in GUTS CLKDVDR */
|
|
||||||
temp = in_be32(&gur->clkdvdr) & 0x2000FFFF;
|
|
||||||
out_be32(&gur->clkdvdr, temp); /* turn off clock */
|
|
||||||
out_be32(&gur->clkdvdr, temp | 0x80000000 | ((pixval & 0x1F) << 16));
|
|
||||||
}
|
|
||||||
|
|
||||||
int platform_diu_init(unsigned int xres, unsigned int yres, const char *port)
|
|
||||||
{
|
|
||||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
|
||||||
u32 pixel_format;
|
|
||||||
|
|
||||||
pixel_format = cpu_to_le32(AD_BYTE_F | (3 << AD_ALPHA_C_SHIFT) |
|
|
||||||
(0 << AD_BLUE_C_SHIFT) | (1 << AD_GREEN_C_SHIFT) |
|
|
||||||
(2 << AD_RED_C_SHIFT) | (8 << AD_COMP_3_SHIFT) |
|
|
||||||
(8 << AD_COMP_2_SHIFT) | (8 << AD_COMP_1_SHIFT) |
|
|
||||||
(8 << AD_COMP_0_SHIFT) | (3 << AD_PIXEL_S_SHIFT));
|
|
||||||
|
|
||||||
printf("DIU: Switching to %ux%u\n", xres, yres);
|
|
||||||
|
|
||||||
/* Set PMUXCR to switch the muxed pins from the LBC to the DIU */
|
|
||||||
clrsetbits_be32(&gur->pmuxcr, PMUXCR_ELBCDIU_MASK, PMUXCR_ELBCDIU_DIU);
|
|
||||||
pmuxcr = in_be32(&gur->pmuxcr);
|
|
||||||
|
|
||||||
return fsl_diu_init(xres, yres, pixel_format, 0);
|
|
||||||
}
|
|
||||||
|
|
@ -1,16 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2010 Freescale Semiconductor, Inc.
|
|
||||||
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
|
|
||||||
* Timur Tabi <timur@freescale.com>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/fsl_law.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
|
|
||||||
struct law_entry law_table[] = {
|
|
||||||
SET_LAW(CONFIG_SYS_ELBC_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
|
|
||||||
};
|
|
||||||
|
|
||||||
int num_law_entries = ARRAY_SIZE(law_table);
|
|
||||||
|
|
@ -1,63 +0,0 @@
|
||||||
/*
|
|
||||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <mmc.h>
|
|
||||||
#include <malloc.h>
|
|
||||||
|
|
||||||
/*
|
|
||||||
* The environment variables are written to just after the u-boot image
|
|
||||||
* on SDCard, so we must read the MBR to get the start address and code
|
|
||||||
* length of the u-boot image, then calculate the address of the env.
|
|
||||||
*/
|
|
||||||
#define ESDHC_BOOT_IMAGE_SIZE 0x48
|
|
||||||
#define ESDHC_BOOT_IMAGE_ADDR 0x50
|
|
||||||
|
|
||||||
int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr)
|
|
||||||
{
|
|
||||||
u8 *tmp_buf;
|
|
||||||
u32 blklen, code_offset, code_len, n;
|
|
||||||
|
|
||||||
blklen = mmc->read_bl_len;
|
|
||||||
tmp_buf = malloc(blklen);
|
|
||||||
if (!tmp_buf)
|
|
||||||
return 1;
|
|
||||||
|
|
||||||
/* read out the first block, get the config data information */
|
|
||||||
n = mmc->block_dev.block_read(&mmc->block_dev, 0, 1, tmp_buf);
|
|
||||||
if (!n) {
|
|
||||||
free(tmp_buf);
|
|
||||||
return 1;
|
|
||||||
}
|
|
||||||
|
|
||||||
/* Get the Source Address, from offset 0x50 */
|
|
||||||
code_offset = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_ADDR);
|
|
||||||
|
|
||||||
/* Get the code size from offset 0x48 */
|
|
||||||
code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);
|
|
||||||
|
|
||||||
*env_addr = code_offset + code_len;
|
|
||||||
|
|
||||||
free(tmp_buf);
|
|
||||||
|
|
||||||
return 0;
|
|
||||||
}
|
|
||||||
|
|
@ -1,73 +0,0 @@
|
||||||
// SPDX-License-Identifier: GPL-2.0+
|
|
||||||
/*
|
|
||||||
* Copyright 2010 Freescale Semiconductor, Inc.
|
|
||||||
* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
|
|
||||||
* Timur Tabi <timur@freescale.com>
|
|
||||||
*/
|
|
||||||
|
|
||||||
#include <common.h>
|
|
||||||
#include <asm/mmu.h>
|
|
||||||
|
|
||||||
struct fsl_e_tlb_entry tlb_table[] = {
|
|
||||||
/* TLB 0 - for temp stack in cache */
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
|
||||||
CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
|
||||||
CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
|
||||||
CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
|
||||||
|
|
||||||
/* TLB 1 */
|
|
||||||
/* *I*** - Covers boot page */
|
|
||||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
|
|
||||||
0, 0, BOOKE_PAGESZ_4K, 1),
|
|
||||||
|
|
||||||
/* *I*G* - CCSRBAR */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
|
||||||
|
|
||||||
/* *I*G* - eLBC */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_ELBC_BASE, CONFIG_SYS_ELBC_BASE_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 2, BOOKE_PAGESZ_1M, 1),
|
|
||||||
|
|
||||||
#if defined(CONFIG_TRAILBLAZER)
|
|
||||||
/* *I*G - L2SRAM */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 9, BOOKE_PAGESZ_256K, 1),
|
|
||||||
#else
|
|
||||||
/* *I*G* - PCI */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 3, BOOKE_PAGESZ_256M, 1),
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
|
|
||||||
CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 4, BOOKE_PAGESZ_256M, 1),
|
|
||||||
|
|
||||||
/* *I*G* - PCI I/O */
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
|
||||||
0, 5, BOOKE_PAGESZ_256K, 1),
|
|
||||||
|
|
||||||
#ifdef CONFIG_SYS_RAMBOOT
|
|
||||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
|
|
||||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
|
|
||||||
0, 6, BOOKE_PAGESZ_1G, 1),
|
|
||||||
#endif
|
|
||||||
#endif
|
|
||||||
};
|
|
||||||
|
|
||||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
|
||||||
|
|
@ -1,69 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0x11000000
|
|
||||||
CONFIG_ENV_SIZE=0x2000
|
|
||||||
CONFIG_ENV_OFFSET=0x0
|
|
||||||
CONFIG_IDENT_STRING=" controlcenterd 0.01"
|
|
||||||
CONFIG_MPC85xx=y
|
|
||||||
CONFIG_TARGET_CONTROLCENTERD=y
|
|
||||||
CONFIG_PHYS_64BIT=y
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="SDCARD,DEVELOP"
|
|
||||||
CONFIG_BOOTDELAY=10
|
|
||||||
# CONFIG_CONSOLE_MUX is not set
|
|
||||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
|
||||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
|
||||||
CONFIG_BOARD_EARLY_INIT_F=y
|
|
||||||
CONFIG_BOARD_EARLY_INIT_R=y
|
|
||||||
CONFIG_LAST_STAGE_INIT=y
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
CONFIG_CMD_REGINFO=y
|
|
||||||
CONFIG_CMD_EEPROM=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
CONFIG_CMD_MMC=y
|
|
||||||
CONFIG_CMD_PCI=y
|
|
||||||
CONFIG_CMD_SATA=y
|
|
||||||
CONFIG_CMD_SF=y
|
|
||||||
CONFIG_CMD_USB=y
|
|
||||||
CONFIG_CMD_MII=y
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_CMD_BMP=y
|
|
||||||
CONFIG_MP=y
|
|
||||||
# CONFIG_CMD_HASH is not set
|
|
||||||
CONFIG_CMD_TPM=y
|
|
||||||
CONFIG_CMD_EXT2=y
|
|
||||||
CONFIG_CMD_FAT=y
|
|
||||||
CONFIG_ENV_IS_IN_MMC=y
|
|
||||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
||||||
CONFIG_DM=y
|
|
||||||
CONFIG_FSL_SATA=y
|
|
||||||
CONFIG_FSL_ESDHC=y
|
|
||||||
CONFIG_SPI_FLASH=y
|
|
||||||
CONFIG_SF_DEFAULT_MODE=0
|
|
||||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
|
||||||
CONFIG_SPI_FLASH_STMICRO=y
|
|
||||||
CONFIG_PHY_ATHEROS=y
|
|
||||||
CONFIG_PHY_BROADCOM=y
|
|
||||||
CONFIG_PHY_DAVICOM=y
|
|
||||||
CONFIG_PHY_LXT=y
|
|
||||||
CONFIG_PHY_MARVELL=y
|
|
||||||
CONFIG_PHY_NATSEMI=y
|
|
||||||
CONFIG_PHY_REALTEK=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_PHY_VITESSE=y
|
|
||||||
CONFIG_MII=y
|
|
||||||
CONFIG_TSEC_ENET=y
|
|
||||||
CONFIG_CONS_INDEX=2
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_FSL_ESPI=y
|
|
||||||
CONFIG_TPM_AUTH_SESSIONS=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_STORAGE=y
|
|
||||||
CONFIG_VIDEO=y
|
|
||||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
|
||||||
CONFIG_ADDR_MAP=y
|
|
||||||
CONFIG_TPM=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
||||||
|
|
@ -1,69 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0x11000000
|
|
||||||
CONFIG_ENV_SIZE=0x2000
|
|
||||||
CONFIG_ENV_OFFSET=0x0
|
|
||||||
CONFIG_IDENT_STRING=" controlcenterd 0.01"
|
|
||||||
CONFIG_MPC85xx=y
|
|
||||||
CONFIG_TARGET_CONTROLCENTERD=y
|
|
||||||
CONFIG_PHYS_64BIT=y
|
|
||||||
CONFIG_FIT=y
|
|
||||||
CONFIG_FIT_VERBOSE=y
|
|
||||||
CONFIG_OF_BOARD_SETUP=y
|
|
||||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
|
|
||||||
CONFIG_BOOTDELAY=10
|
|
||||||
# CONFIG_CONSOLE_MUX is not set
|
|
||||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
|
||||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
|
||||||
CONFIG_BOARD_EARLY_INIT_F=y
|
|
||||||
CONFIG_BOARD_EARLY_INIT_R=y
|
|
||||||
CONFIG_LAST_STAGE_INIT=y
|
|
||||||
CONFIG_HUSH_PARSER=y
|
|
||||||
CONFIG_CMD_REGINFO=y
|
|
||||||
CONFIG_CMD_EEPROM=y
|
|
||||||
CONFIG_CMD_I2C=y
|
|
||||||
CONFIG_CMD_MMC=y
|
|
||||||
CONFIG_CMD_PCI=y
|
|
||||||
CONFIG_CMD_SATA=y
|
|
||||||
CONFIG_CMD_SF=y
|
|
||||||
CONFIG_CMD_USB=y
|
|
||||||
CONFIG_CMD_MII=y
|
|
||||||
CONFIG_CMD_PING=y
|
|
||||||
CONFIG_CMD_BMP=y
|
|
||||||
CONFIG_MP=y
|
|
||||||
# CONFIG_CMD_HASH is not set
|
|
||||||
CONFIG_CMD_TPM=y
|
|
||||||
CONFIG_CMD_EXT2=y
|
|
||||||
CONFIG_CMD_FAT=y
|
|
||||||
CONFIG_ENV_IS_IN_MMC=y
|
|
||||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
||||||
CONFIG_DM=y
|
|
||||||
CONFIG_FSL_SATA=y
|
|
||||||
CONFIG_FSL_ESDHC=y
|
|
||||||
CONFIG_SPI_FLASH=y
|
|
||||||
CONFIG_SF_DEFAULT_MODE=0
|
|
||||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
|
||||||
CONFIG_SPI_FLASH_STMICRO=y
|
|
||||||
CONFIG_PHY_ATHEROS=y
|
|
||||||
CONFIG_PHY_BROADCOM=y
|
|
||||||
CONFIG_PHY_DAVICOM=y
|
|
||||||
CONFIG_PHY_LXT=y
|
|
||||||
CONFIG_PHY_MARVELL=y
|
|
||||||
CONFIG_PHY_NATSEMI=y
|
|
||||||
CONFIG_PHY_REALTEK=y
|
|
||||||
CONFIG_PHY_SMSC=y
|
|
||||||
CONFIG_PHY_VITESSE=y
|
|
||||||
CONFIG_MII=y
|
|
||||||
CONFIG_TSEC_ENET=y
|
|
||||||
CONFIG_CONS_INDEX=2
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_SPI=y
|
|
||||||
CONFIG_FSL_ESPI=y
|
|
||||||
CONFIG_TPM_AUTH_SESSIONS=y
|
|
||||||
CONFIG_USB=y
|
|
||||||
CONFIG_USB_STORAGE=y
|
|
||||||
CONFIG_VIDEO=y
|
|
||||||
# CONFIG_VIDEO_SW_CURSOR is not set
|
|
||||||
CONFIG_ADDR_MAP=y
|
|
||||||
CONFIG_TPM=y
|
|
||||||
CONFIG_OF_LIBFDT=y
|
|
||||||
|
|
@ -1,36 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0xf8fc0000
|
|
||||||
CONFIG_ENV_SIZE=0x2000
|
|
||||||
CONFIG_IDENT_STRING=" controlcenterd trailblazer 0.01"
|
|
||||||
CONFIG_MPC85xx=y
|
|
||||||
# CONFIG_CMD_ERRATA is not set
|
|
||||||
CONFIG_TARGET_CONTROLCENTERD=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH,DEVELOP"
|
|
||||||
CONFIG_BOOTDELAY=-2
|
|
||||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
|
||||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
|
||||||
CONFIG_BOARD_EARLY_INIT_F=y
|
|
||||||
CONFIG_BOARD_EARLY_INIT_R=y
|
|
||||||
CONFIG_LAST_STAGE_INIT=y
|
|
||||||
# CONFIG_MISC_INIT_R is not set
|
|
||||||
# CONFIG_CMDLINE_EDITING is not set
|
|
||||||
# CONFIG_AUTO_COMPLETE is not set
|
|
||||||
# CONFIG_SYS_LONGHELP is not set
|
|
||||||
# CONFIG_CMD_BOOTM is not set
|
|
||||||
CONFIG_CMD_EEPROM=y
|
|
||||||
CONFIG_CMD_MMC=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_MP=y
|
|
||||||
# CONFIG_CMD_HASH is not set
|
|
||||||
CONFIG_CMD_TPM=y
|
|
||||||
# CONFIG_CMD_IRQ is not set
|
|
||||||
CONFIG_DOS_PARTITION=y
|
|
||||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
||||||
CONFIG_DM=y
|
|
||||||
CONFIG_FSL_ESDHC=y
|
|
||||||
# CONFIG_PCI is not set
|
|
||||||
CONFIG_CONS_INDEX=2
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_TPM_AUTH_SESSIONS=y
|
|
||||||
CONFIG_TPM=y
|
|
||||||
CONFIG_SHA1=y
|
|
||||||
|
|
@ -1,36 +0,0 @@
|
||||||
CONFIG_PPC=y
|
|
||||||
CONFIG_SYS_TEXT_BASE=0xf8fc0000
|
|
||||||
CONFIG_ENV_SIZE=0x2000
|
|
||||||
CONFIG_IDENT_STRING=" controlcenterd trailblazer 0.01"
|
|
||||||
CONFIG_MPC85xx=y
|
|
||||||
# CONFIG_CMD_ERRATA is not set
|
|
||||||
CONFIG_TARGET_CONTROLCENTERD=y
|
|
||||||
CONFIG_SYS_EXTRA_OPTIONS="TRAILBLAZER,SPIFLASH"
|
|
||||||
CONFIG_BOOTDELAY=-2
|
|
||||||
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
|
|
||||||
# CONFIG_DISPLAY_BOARDINFO is not set
|
|
||||||
CONFIG_BOARD_EARLY_INIT_F=y
|
|
||||||
CONFIG_BOARD_EARLY_INIT_R=y
|
|
||||||
CONFIG_LAST_STAGE_INIT=y
|
|
||||||
# CONFIG_MISC_INIT_R is not set
|
|
||||||
# CONFIG_CMDLINE_EDITING is not set
|
|
||||||
# CONFIG_AUTO_COMPLETE is not set
|
|
||||||
# CONFIG_SYS_LONGHELP is not set
|
|
||||||
# CONFIG_CMD_BOOTM is not set
|
|
||||||
CONFIG_CMD_EEPROM=y
|
|
||||||
CONFIG_CMD_MMC=y
|
|
||||||
# CONFIG_CMD_SETEXPR is not set
|
|
||||||
CONFIG_MP=y
|
|
||||||
# CONFIG_CMD_HASH is not set
|
|
||||||
CONFIG_CMD_TPM=y
|
|
||||||
# CONFIG_CMD_IRQ is not set
|
|
||||||
CONFIG_DOS_PARTITION=y
|
|
||||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
|
||||||
CONFIG_DM=y
|
|
||||||
CONFIG_FSL_ESDHC=y
|
|
||||||
# CONFIG_PCI is not set
|
|
||||||
CONFIG_CONS_INDEX=2
|
|
||||||
CONFIG_SYS_NS16550=y
|
|
||||||
CONFIG_TPM_AUTH_SESSIONS=y
|
|
||||||
CONFIG_TPM=y
|
|
||||||
CONFIG_SHA1=y
|
|
||||||
|
|
@ -1,352 +0,0 @@
|
||||||
/*
|
|
||||||
* (C) Copyright 2013
|
|
||||||
* Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
|
|
||||||
*
|
|
||||||
* based on P1022DS.h
|
|
||||||
*
|
|
||||||
* See file CREDITS for list of people who contributed to this
|
|
||||||
* project.
|
|
||||||
*
|
|
||||||
* This program is free software; you can redistribute it and/or
|
|
||||||
* modify it under the terms of the GNU General Public License as
|
|
||||||
* published by the Free Software Foundation; either version 2 of
|
|
||||||
* the License, or (at your option) any later version.
|
|
||||||
*
|
|
||||||
* This program is distributed in the hope that it will be useful,
|
|
||||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
|
||||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
|
||||||
* GNU General Public License for more details.
|
|
||||||
*
|
|
||||||
* You should have received a copy of the GNU General Public License
|
|
||||||
* along with this program; if not, write to the Free Software
|
|
||||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
|
||||||
* MA 02111-1307 USA
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifndef __CONFIG_H
|
|
||||||
#define __CONFIG_H
|
|
||||||
|
|
||||||
#include <linux/stringify.h>
|
|
||||||
|
|
||||||
#ifdef CONFIG_SDCARD
|
|
||||||
#define CONFIG_RAMBOOT_SDCARD
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#ifdef CONFIG_SPIFLASH
|
|
||||||
#define CONFIG_RAMBOOT_SPIFLASH
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/* High Level Configuration Options */
|
|
||||||
#define CONFIG_CONTROLCENTERD
|
|
||||||
|
|
||||||
#define CONFIG_ENABLE_36BIT_PHYS
|
|
||||||
|
|
||||||
#define CONFIG_L2_CACHE
|
|
||||||
#define CONFIG_BTB
|
|
||||||
|
|
||||||
#define CONFIG_SYS_CLK_FREQ 66666600
|
|
||||||
#define CONFIG_DDR_CLK_FREQ 66666600
|
|
||||||
|
|
||||||
#define CONFIG_SYS_RAMBOOT
|
|
||||||
|
|
||||||
#ifdef CONFIG_TRAILBLAZER
|
|
||||||
|
|
||||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Config the L2 Cache
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8fc0000
|
|
||||||
#ifdef CONFIG_PHYS_64BIT
|
|
||||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8fc0000ull
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
|
||||||
#endif
|
|
||||||
#define CONFIG_SYS_L2_SIZE (256 << 10)
|
|
||||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
|
||||||
|
|
||||||
#else /* CONFIG_TRAILBLAZER */
|
|
||||||
|
|
||||||
#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc
|
|
||||||
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
|
|
||||||
|
|
||||||
#endif /* CONFIG_TRAILBLAZER */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
|
|
||||||
#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Memory map
|
|
||||||
*
|
|
||||||
* 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
|
|
||||||
* 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
|
|
||||||
* 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
|
|
||||||
*
|
|
||||||
* Localbus non-cacheable
|
|
||||||
* 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
|
|
||||||
* 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
|
|
||||||
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
|
|
||||||
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_INIT_RAM_LOCK
|
|
||||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
|
|
||||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* used area in RAM */
|
|
||||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
|
||||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
|
||||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
|
||||||
|
|
||||||
#ifdef CONFIG_TRAILBLAZER
|
|
||||||
/* leave CCSRBAR at default, because u-boot expects it to be exactly there */
|
|
||||||
#define CONFIG_SYS_CCSRBAR CONFIG_SYS_CCSRBAR_DEFAULT
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_CCSRBAR 0xffe00000
|
|
||||||
#endif
|
|
||||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
|
||||||
#define CONFIG_SYS_MPC85xx_GPIO3_ADDR (CONFIG_SYS_CCSRBAR+0xf200)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* DDR Setup
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
|
||||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
|
||||||
#define CONFIG_SYS_SDRAM_SIZE 1024
|
|
||||||
#define CONFIG_VERY_BIG_RAM
|
|
||||||
|
|
||||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
|
||||||
#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
|
|
||||||
|
|
||||||
#ifdef CONFIG_TRAILBLAZER
|
|
||||||
#define CONFIG_SPD_EEPROM
|
|
||||||
#define SPD_EEPROM_ADDRESS 0x52
|
|
||||||
/*#define CONFIG_FSL_DDR_INTERACTIVE*/
|
|
||||||
#endif
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Local Bus Definitions
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_SYS_ELBC_BASE 0xe0000000
|
|
||||||
#ifdef CONFIG_PHYS_64BIT
|
|
||||||
#define CONFIG_SYS_ELBC_BASE_PHYS 0xfe0000000ull
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_ELBC_BASE_PHYS CONFIG_SYS_ELBC_BASE
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_UART_BR_PRELIM \
|
|
||||||
(BR_PHYS_ADDR((CONFIG_SYS_ELBC_BASE_PHYS)) | BR_PS_8 | BR_V)
|
|
||||||
#define CONFIG_UART_OR_PRELIM (OR_AM_32KB | 0xff7)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BR0_PRELIM 0 /* CS0 was originally intended for FPGA */
|
|
||||||
#define CONFIG_SYS_OR0_PRELIM 0 /* debugging, was never used */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BR1_PRELIM CONFIG_UART_BR_PRELIM
|
|
||||||
#define CONFIG_SYS_OR1_PRELIM CONFIG_UART_OR_PRELIM
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Serial Port
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_NS16550_SERIAL
|
|
||||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
|
||||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
|
||||||
|
|
||||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
|
||||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
|
|
||||||
|
|
||||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
|
|
||||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* I2C
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_I2C
|
|
||||||
#define CONFIG_SYS_I2C_FSL
|
|
||||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
|
||||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
|
||||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
|
||||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
|
||||||
|
|
||||||
#define CONFIG_PCA9698 /* NXP PCA9698 */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
|
|
||||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
|
|
||||||
|
|
||||||
/*
|
|
||||||
* MMC
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
|
||||||
|
|
||||||
#ifndef CONFIG_TRAILBLAZER
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Video
|
|
||||||
*/
|
|
||||||
#define CONFIG_FSL_DIU_FB
|
|
||||||
#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
|
|
||||||
|
|
||||||
/*
|
|
||||||
* General PCI
|
|
||||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
|
||||||
*/
|
|
||||||
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */
|
|
||||||
#define CONFIG_PCI_INDIRECT_BRIDGE
|
|
||||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
|
||||||
#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
|
|
||||||
|
|
||||||
#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
|
|
||||||
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
|
|
||||||
#ifdef CONFIG_PHYS_64BIT
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
|
|
||||||
#endif
|
|
||||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
|
||||||
#ifdef CONFIG_PHYS_64BIT
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
|
|
||||||
#else
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
|
|
||||||
#endif
|
|
||||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* SATA
|
|
||||||
*/
|
|
||||||
#define CONFIG_LBA48
|
|
||||||
|
|
||||||
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
|
||||||
#define CONFIG_SATA1
|
|
||||||
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
|
|
||||||
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
|
|
||||||
#define CONFIG_SATA2
|
|
||||||
#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
|
|
||||||
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Ethernet
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_TSECV2
|
|
||||||
|
|
||||||
#define CONFIG_TSEC1 1
|
|
||||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
|
||||||
#define CONFIG_TSEC2 1
|
|
||||||
#define CONFIG_TSEC2_NAME "eTSEC2"
|
|
||||||
|
|
||||||
#define TSEC1_PHY_ADDR 0
|
|
||||||
#define TSEC2_PHY_ADDR 1
|
|
||||||
|
|
||||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
||||||
#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
|
||||||
|
|
||||||
#define TSEC1_PHYIDX 0
|
|
||||||
#define TSEC2_PHYIDX 0
|
|
||||||
|
|
||||||
#define CONFIG_ETHPRIME "eTSEC1"
|
|
||||||
|
|
||||||
/*
|
|
||||||
* USB
|
|
||||||
*/
|
|
||||||
|
|
||||||
#define CONFIG_HAS_FSL_DR_USB
|
|
||||||
#define CONFIG_USB_EHCI_FSL
|
|
||||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
|
||||||
|
|
||||||
#endif /* CONFIG_TRAILBLAZER */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment
|
|
||||||
*/
|
|
||||||
#if defined(CONFIG_TRAILBLAZER)
|
|
||||||
#elif defined(CONFIG_RAMBOOT_SDCARD)
|
|
||||||
#define CONFIG_FSL_FIXED_MMC_LOCATION
|
|
||||||
#endif
|
|
||||||
|
|
||||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
|
||||||
|
|
||||||
#ifndef CONFIG_TRAILBLAZER
|
|
||||||
/*
|
|
||||||
* Board initialisation callbacks
|
|
||||||
*/
|
|
||||||
#endif /* CONFIG_TRAILBLAZER */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Miscellaneous configurable options
|
|
||||||
*/
|
|
||||||
#define CONFIG_HW_WATCHDOG
|
|
||||||
#define CONFIG_LOADS_ECHO
|
|
||||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE
|
|
||||||
|
|
||||||
/*
|
|
||||||
* For booting Linux, the board info and command line data
|
|
||||||
* have to be in the first 64 MB of memory, since this is
|
|
||||||
* the maximum mapped by the Linux kernel during initialization.
|
|
||||||
*/
|
|
||||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Linux Memory map */
|
|
||||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Environment Configuration
|
|
||||||
*/
|
|
||||||
|
|
||||||
#ifdef CONFIG_TRAILBLAZER
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
"mp_holdoff=1\0"
|
|
||||||
|
|
||||||
#else
|
|
||||||
|
|
||||||
#define CONFIG_HOSTNAME "controlcenterd"
|
|
||||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
|
||||||
#define CONFIG_BOOTFILE "uImage"
|
|
||||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP */
|
|
||||||
|
|
||||||
#define CONFIG_LOADADDR 1000000
|
|
||||||
|
|
||||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
|
||||||
"netdev=eth0\0" \
|
|
||||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
|
||||||
"ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
|
|
||||||
"tftpflash=tftpboot $loadaddr $uboot && " \
|
|
||||||
"protect off $ubootaddr +$filesize && " \
|
|
||||||
"erase $ubootaddr +$filesize && " \
|
|
||||||
"cp.b $loadaddr $ubootaddr $filesize && " \
|
|
||||||
"protect on $ubootaddr +$filesize && " \
|
|
||||||
"cmp.b $loadaddr $ubootaddr $filesize\0" \
|
|
||||||
"consoledev=ttyS1\0" \
|
|
||||||
"ramdiskaddr=2000000\0" \
|
|
||||||
"ramdiskfile=rootfs.ext2.gz.uboot\0" \
|
|
||||||
"fdtaddr=1e00000\0" \
|
|
||||||
"fdtfile=controlcenterd.dtb\0" \
|
|
||||||
"bdev=sda3\0"
|
|
||||||
|
|
||||||
/* these are used and NUL-terminated in env_default.h */
|
|
||||||
#define CONFIG_NFSBOOTCOMMAND \
|
|
||||||
"setenv bootargs root=/dev/nfs rw " \
|
|
||||||
"nfsroot=$serverip:$rootpath " \
|
|
||||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
|
|
||||||
"tftp $loadaddr $bootfile;" \
|
|
||||||
"tftp $fdtaddr $fdtfile;" \
|
|
||||||
"bootm $loadaddr - $fdtaddr"
|
|
||||||
|
|
||||||
#define CONFIG_RAMBOOTCOMMAND \
|
|
||||||
"setenv bootargs root=/dev/ram rw " \
|
|
||||||
"console=$consoledev,$baudrate $othbootargs $videobootargs;" \
|
|
||||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
|
||||||
"tftp $loadaddr $bootfile;" \
|
|
||||||
"tftp $fdtaddr $fdtfile;" \
|
|
||||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
|
||||||
|
|
||||||
#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
|
|
||||||
|
|
||||||
#endif /* CONFIG_TRAILBLAZER */
|
|
||||||
|
|
||||||
#endif
|
|
||||||
Loading…
Reference in New Issue