Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx
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						ab92d0fd9a
					
				|  | @ -245,6 +245,7 @@ | |||
| #define MxMR_DSx_4_CYCL		0x00c00000 /* 4 cycle Disable Period	   */ | ||||
| #define MxMR_DSx_MSK		0x00c00000 /* Disable Timer Period Mask	   */ | ||||
| #define MxMR_AMx_MSK		0x07000000 /* Addess Multiplex Size Mask   */ | ||||
| #define MxMR_UWPL		0x08000000 /* LUPWAIT Polarity Mask	   */ | ||||
| #define MxMR_OP_NORM		0x00000000 /* Normal Operation		   */ | ||||
| #define MxMR_OP_WARR		0x10000000 /* Write to Array		   */ | ||||
| #define MxMR_OP_RARR		0x20000000 /* Read from Array		   */ | ||||
|  |  | |||
|  | @ -32,6 +32,7 @@ SOBJS	:= $(addprefix $(obj),$(SOBJS)) | |||
| 
 | ||||
| $(LIB):	$(obj).depend $(OBJS) | ||||
| 	$(AR) $(ARFLAGS) $@ $(OBJS) | ||||
| 	@mkimage -T script -C none -n M7_script -d bootscript bootscript.img | ||||
| 
 | ||||
| clean: | ||||
| 	rm -f $(SOBJS) $(OBJS) | ||||
|  |  | |||
|  | @ -29,6 +29,7 @@ | |||
| #include <mpc83xx.h> | ||||
| #include <ns16550.h> | ||||
| #include <nand.h> | ||||
| #include <asm/io.h> | ||||
| 
 | ||||
| DECLARE_GLOBAL_DATA_PTR; | ||||
| 
 | ||||
|  | @ -91,6 +92,40 @@ void pci_init_board(void) | |||
| int misc_init_r(void) | ||||
| { | ||||
| 	int rc = 0; | ||||
| 	immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; | ||||
| 	fsl_lbus_t *lbus = &immap->lbus; | ||||
| 	u32 *mxmr = &lbus->mamr;	/* Pointer to mamr */ | ||||
| 
 | ||||
| 	/* UPM Table Configuration Code */ | ||||
| 	static uint UPMATable[] = { | ||||
| 		/* Read Single-Beat (RSS) */ | ||||
| 		0x0fff0c00, 0x0fffdc00, 0x0fff0c05, 0xfffffc00, | ||||
| 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | ||||
| 		/* Read Burst (RBS) */ | ||||
| 		0x0fff0c00, 0x0ffcdc00, 0x0ffc0c00, 0x0ffc0f0c, | ||||
| 		0x0ffccf0c, 0x0ffc0f0c, 0x0ffcce0c, 0x3ffc0c05, | ||||
| 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | ||||
| 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | ||||
| 		/* Write Single-Beat (WSS) */ | ||||
| 		0x0ffc0c00, 0x0ffcdc00, 0x0ffc0c05, 0xfffffc00, | ||||
| 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | ||||
| 		/* Write Burst (WBS) */ | ||||
| 		0x0ffc0c00, 0x0fffcc0c, 0x0fff0c00, 0x0fffcc00, | ||||
| 		0x0fff1c00, 0x0fffcf0c, 0x0fff0f0c, 0x0fffcf0c, | ||||
| 		0x0fff0c0c, 0x0fffcc0c, 0x0fff0c05, 0xfffffc00, | ||||
| 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | ||||
| 		/* Refresh Timer (RTS) */ | ||||
| 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | ||||
| 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, | ||||
| 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, | ||||
| 		/* Exception Condition (EXS) */ | ||||
| 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01 | ||||
| 	}; | ||||
| 
 | ||||
| 	upmconfig(UPMA, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0])); | ||||
| 
 | ||||
| 	/* Set LUPWAIT to be active low and enabled */ | ||||
| 	out_be32(mxmr, MxMR_UWPL | MxMR_GPL_x4DIS); | ||||
| 
 | ||||
| 	return rc; | ||||
| } | ||||
|  |  | |||
|  | @ -234,7 +234,11 @@ | |||
| #define CONFIG_BOOTP_SEND_HOSTNAME | ||||
| 
 | ||||
| /* USB */ | ||||
| #define CONFIG_SYS_USB_HOST | ||||
| #define CONFIG_USB_EHCI | ||||
| #define CONFIG_USB_EHCI_FSL | ||||
| #define CONFIG_HAS_FSL_DR_USB | ||||
| #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | ||||
| 
 | ||||
| /*
 | ||||
|  * Environment | ||||
|  | @ -267,6 +271,8 @@ | |||
| #define CONFIG_CMD_PCI | ||||
| #define CONFIG_CMD_I2C | ||||
| #define CONFIG_CMD_FPGA | ||||
| #define CONFIG_CMD_USB | ||||
| #define CONFIG_DOS_PARTITION | ||||
| 
 | ||||
| #undef CONFIG_WATCHDOG | ||||
| 
 | ||||
|  |  | |||
|  | @ -126,6 +126,7 @@ | |||
| #else | ||||
| #define CONFIG_SYS_NAND_BASE		0xE2800000 | ||||
| #endif | ||||
| #define CONFIG_SYS_FPGA_BASE		0xFF000000 | ||||
| 
 | ||||
| #define CONFIG_SYS_MAX_NAND_DEVICE	1 | ||||
| #define NAND_MAX_CHIPS			1 | ||||
|  | @ -184,6 +185,16 @@ | |||
| #define CONFIG_SYS_NAND_LBLAWBAR_PRELIM	CONFIG_SYS_LBLAWBAR0_PRELIM | ||||
| #define CONFIG_SYS_NAND_LBLAWAR_PRELIM	CONFIG_SYS_LBLAWAR0_PRELIM | ||||
| 
 | ||||
| #define CONFIG_SYS_BR1_PRELIM		( CONFIG_SYS_FPGA_BASE \ | ||||
| 					| BR_PS_16 \ | ||||
| 					| BR_MS_UPMA \ | ||||
| 					| BR_V ) | ||||
| #define CONFIG_SYS_OR1_PRELIM		( OR_AM_2MB \ | ||||
| 					| OR_UPM_BCTLD) | ||||
| 
 | ||||
| #define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_FPGA_BASE | ||||
| #define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_2MB) | ||||
| 
 | ||||
| /*
 | ||||
|  * JFFS2 configuration | ||||
|  */ | ||||
|  |  | |||
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