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armada100: define CONFIG_SYS_CACHELINE_SIZE 

By default, on Armada100 SoC DCache Lnd ICache line
lengths are 32 bytes long

Signed-off-by: Lei Wen <leiwen@marvell.com>
This commit is contained in:
Lei Wen 2011-11-01 16:25:56 +05:30 committed by Albert ARIBAUD
parent 0caac5f415
commit abbbbdd7e1
1 changed files with 2 additions and 0 deletions
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2
arch/arm/include/asm/arch-armada100/config.h
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@ -33,6 +33,8 @@
#include <asm/arch/armada100.h> #include <asm/arch/armada100.h>
#define CONFIG_ARM926EJS 1 /* Basic Architecture */ #define CONFIG_ARM926EJS 1 /* Basic Architecture */
/* default Dcache Line length for armada100 */
#define CONFIG_SYS_CACHELINE_SIZE 32
#define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */ #define CONFIG_SYS_TCLK (14745600) /* NS16550 clk config */
#define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */ #define CONFIG_SYS_HZ_CLOCK (3250000) /* Timer Freq. 3.25MHZ */