LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge git://git.denx.de/u-boot-sunxi

This commit is contained in:
Tom Rini 2018-04-30 06:52:32 -04:00
parent 8c84287a0f 5ff8e54888
commit abeb9d7897
1 changed files with 20 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

35
drivers/mmc/sunxi_mmc.c
View File

@ -147,19 +147,19 @@ static int mmc_set_mod_clk(struct sunxi_mmc_priv *priv, unsigned int hz)
oclk_dly = 0; oclk_dly = 0;
sclk_dly = 5; sclk_dly = 5;
#ifdef CONFIG_MACH_SUN9I #ifdef CONFIG_MACH_SUN9I
} else if (hz <= 50000000) { } else if (hz <= 52000000) {
oclk_dly = 5; oclk_dly = 5;
sclk_dly = 4; sclk_dly = 4;
} else { } else {
/* hz > 50000000 */ /* hz > 52000000 */
oclk_dly = 2; oclk_dly = 2;
sclk_dly = 4; sclk_dly = 4;
#else #else
} else if (hz <= 50000000) { } else if (hz <= 52000000) {
oclk_dly = 3; oclk_dly = 3;
sclk_dly = 4; sclk_dly = 4;
} else { } else {
/* hz > 50000000 */ /* hz > 52000000 */
oclk_dly = 1; oclk_dly = 1;
sclk_dly = 4; sclk_dly = 4;
#endif #endif
@ -188,15 +188,16 @@ static int mmc_update_clk(struct sunxi_mmc_priv *priv)
{ {
unsigned int cmd; unsigned int cmd;
unsigned timeout_msecs = 2000; unsigned timeout_msecs = 2000;
unsigned long start = get_timer(0);
cmd = SUNXI_MMC_CMD_START | cmd = SUNXI_MMC_CMD_START |
SUNXI_MMC_CMD_UPCLK_ONLY | SUNXI_MMC_CMD_UPCLK_ONLY |
SUNXI_MMC_CMD_WAIT_PRE_OVER; SUNXI_MMC_CMD_WAIT_PRE_OVER;
writel(cmd, &priv->reg->cmd); writel(cmd, &priv->reg->cmd);
while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) { while (readl(&priv->reg->cmd) & SUNXI_MMC_CMD_START) {
if (!timeout_msecs--) if (get_timer(start) > timeout_msecs)
return -1; return -1;
udelay(1000);
} }
/* clock update sets various irq status bits, clear these */ /* clock update sets various irq status bits, clear these */
@ -277,18 +278,21 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
unsigned i; unsigned i;
unsigned *buff = (unsigned int *)(reading ? data->dest : data->src); unsigned *buff = (unsigned int *)(reading ? data->dest : data->src);
unsigned byte_cnt = data->blocksize * data->blocks; unsigned byte_cnt = data->blocksize * data->blocks;
unsigned timeout_usecs = (byte_cnt >> 8) * 1000; unsigned timeout_msecs = byte_cnt >> 8;
if (timeout_usecs < 2000000) unsigned long start;
timeout_usecs = 2000000;
if (timeout_msecs < 2000)
timeout_msecs = 2000;
/* Always read / write data through the CPU */ /* Always read / write data through the CPU */
setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB); setbits_le32(&priv->reg->gctrl, SUNXI_MMC_GCTRL_ACCESS_BY_AHB);
start = get_timer(0);
for (i = 0; i < (byte_cnt >> 2); i++) { for (i = 0; i < (byte_cnt >> 2); i++) {
while (readl(&priv->reg->status) & status_bit) { while (readl(&priv->reg->status) & status_bit) {
if (!timeout_usecs--) if (get_timer(start) > timeout_msecs)
return -1; return -1;
udelay(1);
} }
if (reading) if (reading)
@ -304,16 +308,16 @@ static int mmc_rint_wait(struct sunxi_mmc_priv *priv, struct mmc *mmc,
uint timeout_msecs, uint done_bit, const char *what) uint timeout_msecs, uint done_bit, const char *what)
{ {
unsigned int status; unsigned int status;
unsigned long start = get_timer(0);
do { do {
status = readl(&priv->reg->rint); status = readl(&priv->reg->rint);
if (!timeout_msecs-- || if ((get_timer(start) > timeout_msecs) ||
(status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) {
debug("%s timeout %x\n", what, debug("%s timeout %x\n", what,
status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT);
return -ETIMEDOUT; return -ETIMEDOUT;
} }
udelay(1000);
} while (!(status & done_bit)); } while (!(status & done_bit));
return 0; return 0;
@ -405,15 +409,16 @@ static int sunxi_mmc_send_cmd_common(struct sunxi_mmc_priv *priv,
} }
if (cmd->resp_type & MMC_RSP_BUSY) { if (cmd->resp_type & MMC_RSP_BUSY) {
unsigned long start = get_timer(0);
timeout_msecs = 2000; timeout_msecs = 2000;
do { do {
status = readl(&priv->reg->status); status = readl(&priv->reg->status);
if (!timeout_msecs--) { if (get_timer(start) > timeout_msecs) {
debug("busy timeout\n"); debug("busy timeout\n");
error = -ETIMEDOUT; error = -ETIMEDOUT;
goto out; goto out;
} }
udelay(1000);
} while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY); } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY);
} }