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MLK-16273-1 usb: dwc3: add suspend clock setting interface 

Some dwc3 based USB3 IP may have a wrong default suspend clk
setting, so add an interface to correct it by board setting.

Acked-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Li Jun <jun.li@nxp.com>
(cherry picked from commit 240b636718313e03db505a713e66e3f893cb7727)
This commit is contained in:
Li Jun 2017-08-26 01:49:51 +08:00 committed by Ye Li
parent b81241ee36
commit ac64f46053
3 changed files with 27 additions and 0 deletions
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24
drivers/usb/dwc3/core.c
View File

@ -395,6 +395,25 @@ static void dwc3_phy_setup(struct dwc3 *dwc)
mdelay(100);
}
void dwc3_set_suspend_clk(struct dwc3 *dwc)
{
u32 reg;
/*
* DWC3_GCTL.PWRDNSCALE: The USB3 suspend_clk input replaces
* pipe3_rx_pclk as a clock source to a small part of the USB3
* core that operates when the SS PHY is in its lowest power
* (P3) state, and therefore does not provide a clock.
* The Power Down Scale field specifies how many suspend_clk
* periods fit into a 16 kHz clock period. When performing the
* division, round up the remainder.
*/
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg &= ~(DWC3_GCTL_PWRDNSCALE(0x1fff));
reg |= DWC3_GCTL_PWRDNSCALE(dwc->power_down_scale);
dwc3_writel(dwc->regs, DWC3_GCTL, reg);
}
/**
* dwc3_core_init - Low-level initialization of DWC3 Core
* @dwc: Pointer to our controller context structure
@ -443,6 +462,9 @@ static int dwc3_core_init(struct dwc3 *dwc)
if (ret)
goto err0;
if (dwc->power_down_scale)
dwc3_set_suspend_clk(dwc);
reg = dwc3_readl(dwc->regs, DWC3_GCTL);
reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
@ -672,6 +694,8 @@ int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
if (dwc3_dev->tx_de_emphasis)
tx_de_emphasis = dwc3_dev->tx_de_emphasis;
dwc->power_down_scale = dwc3_dev->power_down_scale;
/* default to superspeed if no maximum_speed passed */
if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
dwc->maximum_speed = USB_SPEED_SUPER;

2
drivers/usb/dwc3/core.h
View File

@ -643,6 +643,7 @@ struct dwc3_scratchpad_array {
* @dr_mode: requested mode of operation
* @dcfg: saved contents of DCFG register
* @gctl: saved contents of GCTL register
* @power_down_scale: 16KHz clock periods for suspend_clk
* @isoch_delay: wValue from Set Isochronous Delay request;
* @u2sel: parameter from Set SEL request.
* @u2pel: parameter from Set SEL request.
@ -763,6 +764,7 @@ struct dwc3 {
enum dwc3_ep0_state ep0state;
enum dwc3_link_state link_state;
u16 power_down_scale;
u16 isoch_delay;
u16 u2sel;
u16 u2pel;

1
include/dwc3-uboot.h
View File

@ -16,6 +16,7 @@ struct dwc3_device {
unsigned long base;
enum usb_dr_mode dr_mode;
u32 maximum_speed;
u16 power_down_scale;
unsigned tx_fifo_resize:1;
unsigned has_lpm_erratum;
u8 lpm_nyet_threshold;