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spl: Add support for enabling d-cache in board_init_r 

This patchset reimplements part of the dropped patchset bd236384ceef
which enables d-cache during SPL execution.

Having the d-cache disabled created a regression that added additional
250 milliseconds to A72 SPL boot time on the J721E platform.

Signed-off-by: Matt Ranostay <mranostay@ti.com>
This commit is contained in:
Matt Ranostay 2022-06-08 06:14:15 -07:00 committed by Anand Gadiyar
parent 23e98f546f
commit ad3d63b199
1 changed files with 6 additions and 0 deletions
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6
common/spl/spl.c
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@ -602,6 +602,12 @@ void board_init_r(gd_t *dummy1, ulong dummy2)
spl_set_bd();
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) && \
(defined(CONFIG_CPU_V7A) || defined(CONFIG_ARM64) || \
defined(CONFIG_CPU_V7R))
enable_caches();
#endif
#if defined(CONFIG_SYS_SPL_MALLOC_START)
mem_malloc_init(CONFIG_SYS_SPL_MALLOC_START,
CONFIG_SYS_SPL_MALLOC_SIZE);