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ARM: uniphier: refactor DDR PHY parameter dump command 

Do not hard-code the number of DX blocks because it is a different
value for LD11 SoC.

Move the macro NR_DATX8_PER_DDRPHY to ddrphy-training.c since it
is the last user.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
This commit is contained in:
Masahiro Yamada 2016-10-27 23:47:08 +09:00
parent 6dd34ae4c4
commit adf55f63ae
3 changed files with 50 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

88
arch/arm/mach-uniphier/dram/cmd_ddrphy.c
View File

@ -11,7 +11,6 @@
#include <linux/sizes.h> #include <linux/sizes.h>
#include "../soc-info.h" #include "../soc-info.h"
#include "ddrphy-init.h"
#include "ddrphy-regs.h" #include "ddrphy-regs.h"
/* Select either decimal or hexadecimal */ /* Select either decimal or hexadecimal */
@ -23,22 +22,29 @@
/* field separator */ /* field separator */
#define FS " " #define FS " "
static unsigned long uniphier_ld4_base[] = { struct phy_param {
0x5bc01000, resource_size_t base;
0x5be01000, unsigned int nr_dx;
0 /* sentinel */
}; };
static unsigned long uniphier_pro4_base[] = { static const struct phy_param uniphier_ld4_phy_param[] = {
0x5bc01000, { .base = 0x5bc01000, .nr_dx = 2, },
0x5be01000, { .base = 0x5be01000, .nr_dx = 2, },
0 /* sentinel */ { /* sentinel */ }
}; };
static unsigned long uniphier_sld8_base[] = { static const struct phy_param uniphier_pro4_phy_param[] = {
0x5bc01000, { .base = 0x5bc01000, .nr_dx = 2, },
0x5be01000, { .base = 0x5bc02000, .nr_dx = 2, },
0 /* sentinel */ { .base = 0x5be01000, .nr_dx = 2, },
{ .base = 0x5be02000, .nr_dx = 2, },
{ /* sentinel */ }
};
static const struct phy_param uniphier_sld8_phy_param[] = {
{ .base = 0x5bc01000, .nr_dx = 2, },
{ .base = 0x5be01000, .nr_dx = 2, },
{ /* sentinel */ }
}; };
static void print_bdl(void __iomem *reg, int n) static void print_bdl(void __iomem *reg, int n)
@ -50,17 +56,17 @@ static void print_bdl(void __iomem *reg, int n)
printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f); printf(FS PRINTF_FORMAT, (val >> i * 6) & 0x3f);
} }
static void dump_loop(unsigned long *base, static void dump_loop(const struct phy_param *phy_param,
void (*callback)(void __iomem *)) void (*callback)(void __iomem *))
{ {
void __iomem *phy_base, *dx_base; void __iomem *phy_base, *dx_base;
int p, dx; int p, dx;
for (p = 0; *base; base++, p++) { for (p = 0; phy_param->base; phy_param++, p++) {
phy_base = ioremap(*base, SZ_4K); phy_base = ioremap(phy_param->base, SZ_4K);
dx_base = phy_base + PHY_DX_BASE; dx_base = phy_base + PHY_DX_BASE;
for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { for (dx = 0; dx < phy_param->nr_dx; dx++) {
printf("PHY%dDX%d:", p, dx); printf("PHY%dDX%d:", p, dx);
(*callback)(dx_base); (*callback)(dx_base);
dx_base += PHY_DX_STRIDE; dx_base += PHY_DX_STRIDE;
@ -80,12 +86,12 @@ static void __wbdl_dump(void __iomem *dx_base)
readl(dx_base + PHY_DX_LCDLR1) & 0xff); readl(dx_base + PHY_DX_LCDLR1) & 0xff);
} }
static void wbdl_dump(unsigned long *base) static void wbdl_dump(const struct phy_param *phy_param)
{ {
printf("\n--- Write Bit Delay Line ---\n"); printf("\n--- Write Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n"); printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM DQS (WDQD)\n");
dump_loop(base, &__wbdl_dump); dump_loop(phy_param, &__wbdl_dump);
} }
static void __rbdl_dump(void __iomem *dx_base) static void __rbdl_dump(void __iomem *dx_base)
@ -97,12 +103,12 @@ static void __rbdl_dump(void __iomem *dx_base)
(readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff); (readl(dx_base + PHY_DX_LCDLR1) >> 8) & 0xff);
} }
static void rbdl_dump(unsigned long *base) static void rbdl_dump(const struct phy_param *phy_param)
{ {
printf("\n--- Read Bit Delay Line ---\n"); printf("\n--- Read Bit Delay Line ---\n");
printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n"); printf(" DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DM (RDQSD)\n");
dump_loop(base, &__rbdl_dump); dump_loop(phy_param, &__rbdl_dump);
} }
static void __wld_dump(void __iomem *dx_base) static void __wld_dump(void __iomem *dx_base)
@ -120,12 +126,12 @@ static void __wld_dump(void __iomem *dx_base)
} }
} }
static void wld_dump(unsigned long *base) static void wld_dump(const struct phy_param *phy_param)
{ {
printf("\n--- Write Leveling Delay ---\n"); printf("\n--- Write Leveling Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n"); printf(" Rank0 Rank1 Rank2 Rank3\n");
dump_loop(base, &__wld_dump); dump_loop(phy_param, &__wld_dump);
} }
static void __dqsgd_dump(void __iomem *dx_base) static void __dqsgd_dump(void __iomem *dx_base)
@ -142,12 +148,12 @@ static void __dqsgd_dump(void __iomem *dx_base)
} }
} }
static void dqsgd_dump(unsigned long *base) static void dqsgd_dump(const struct phy_param *phy_param)
{ {
printf("\n--- DQS Gating Delay ---\n"); printf("\n--- DQS Gating Delay ---\n");
printf(" Rank0 Rank1 Rank2 Rank3\n"); printf(" Rank0 Rank1 Rank2 Rank3\n");
dump_loop(base, &__dqsgd_dump); dump_loop(phy_param, &__dqsgd_dump);
} }
static void __mdl_dump(void __iomem *dx_base) static void __mdl_dump(void __iomem *dx_base)
@ -158,12 +164,12 @@ static void __mdl_dump(void __iomem *dx_base)
printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff); printf(FS PRINTF_FORMAT, (mdl >> (8 * i)) & 0xff);
} }
static void mdl_dump(unsigned long *base) static void mdl_dump(const struct phy_param *phy_param)
{ {
printf("\n--- Master Delay Line ---\n"); printf("\n--- Master Delay Line ---\n");
printf(" IPRD TPRD MDLD\n"); printf(" IPRD TPRD MDLD\n");
dump_loop(base, &__mdl_dump); dump_loop(phy_param, &__mdl_dump);
} }
#define REG_DUMP(x) \ #define REG_DUMP(x) \
@ -178,15 +184,15 @@ static void mdl_dump(unsigned long *base)
printf("%3d: DX%d%-7s: %p : %08x\n", \ printf("%3d: DX%d%-7s: %p : %08x\n", \
ofst >> PHY_REG_SHIFT, (dx), #x, reg, readl(reg)); } ofst >> PHY_REG_SHIFT, (dx), #x, reg, readl(reg)); }
static void reg_dump(unsigned long *base) static void reg_dump(const struct phy_param *phy_param)
{ {
void __iomem *phy_base; void __iomem *phy_base;
int p, dx; int p, dx;
printf("\n--- DDR PHY registers ---\n"); printf("\n--- DDR PHY registers ---\n");
for (p = 0; *base; base++, p++) { for (p = 0; phy_param->base; phy_param++, p++) {
phy_base = ioremap(*base, SZ_4K); phy_base = ioremap(phy_param->base, SZ_4K);
printf("== PHY%d (base: %p) ==\n", p, phy_base); printf("== PHY%d (base: %p) ==\n", p, phy_base);
printf(" No: Name : Address : Data\n"); printf(" No: Name : Address : Data\n");
@ -216,7 +222,7 @@ static void reg_dump(unsigned long *base)
REG_DUMP(MR2); REG_DUMP(MR2);
REG_DUMP(MR3); REG_DUMP(MR3);
for (dx = 0; dx < NR_DATX8_PER_DDRPHY; dx++) { for (dx = 0; dx < phy_param->nr_dx; dx++) {
DX_REG_DUMP(dx, GCR); DX_REG_DUMP(dx, GCR);
DX_REG_DUMP(dx, GTR); DX_REG_DUMP(dx, GTR);
} }
@ -228,17 +234,17 @@ static void reg_dump(unsigned long *base)
static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{ {
char *cmd = argv[1]; char *cmd = argv[1];
unsigned long *base; const struct phy_param *phy_param;
switch (uniphier_get_soc_type()) { switch (uniphier_get_soc_type()) {
case SOC_UNIPHIER_LD4: case SOC_UNIPHIER_LD4:
base = uniphier_ld4_base; phy_param = uniphier_ld4_phy_param;
break; break;
case SOC_UNIPHIER_PRO4: case SOC_UNIPHIER_PRO4:
base = uniphier_pro4_base; phy_param = uniphier_pro4_phy_param;
break; break;
case SOC_UNIPHIER_SLD8: case SOC_UNIPHIER_SLD8:
base = uniphier_sld8_base; phy_param = uniphier_sld8_phy_param;
break; break;
default: default:
printf("unsupported SoC\n"); printf("unsupported SoC\n");
@ -249,22 +255,22 @@ static int do_ddr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
cmd = "all"; cmd = "all";
if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all")) if (!strcmp(cmd, "wbdl") || !strcmp(cmd, "all"))
wbdl_dump(base); wbdl_dump(phy_param);
if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all")) if (!strcmp(cmd, "rbdl") || !strcmp(cmd, "all"))
rbdl_dump(base); rbdl_dump(phy_param);
if (!strcmp(cmd, "wld") || !strcmp(cmd, "all")) if (!strcmp(cmd, "wld") || !strcmp(cmd, "all"))
wld_dump(base); wld_dump(phy_param);
if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all")) if (!strcmp(cmd, "dqsgd") || !strcmp(cmd, "all"))
dqsgd_dump(base); dqsgd_dump(phy_param);
if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all")) if (!strcmp(cmd, "mdl") || !strcmp(cmd, "all"))
mdl_dump(base); mdl_dump(phy_param);
if (!strcmp(cmd, "reg") || !strcmp(cmd, "all")) if (!strcmp(cmd, "reg") || !strcmp(cmd, "all"))
reg_dump(base); reg_dump(phy_param);
return CMD_RET_SUCCESS; return CMD_RET_SUCCESS;
} }

3
arch/arm/mach-uniphier/dram/ddrphy-init.h
View File

@ -10,9 +10,6 @@
#include <linux/compiler.h> #include <linux/compiler.h>
#include <linux/types.h> #include <linux/types.h>
/* for LD4, Pro4, sLD8 */
#define NR_DATX8_PER_DDRPHY 2
int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus); int uniphier_ld4_ddrphy_init(void __iomem *phy_base, int freq, bool ddr3plus);
void ddrphy_prepare_training(void __iomem *phy_base, int rank); void ddrphy_prepare_training(void __iomem *phy_base, int rank);
int ddrphy_training(void __iomem *phy_base); int ddrphy_training(void __iomem *phy_base);

3
arch/arm/mach-uniphier/dram/ddrphy-training.c
View File

@ -12,6 +12,9 @@
#include "ddrphy-init.h" #include "ddrphy-init.h"
#include "ddrphy-regs.h" #include "ddrphy-regs.h"
/* for LD4, Pro4, sLD8 */
#define NR_DATX8_PER_DDRPHY 2
void ddrphy_prepare_training(void __iomem *phy_base, int rank) void ddrphy_prepare_training(void __iomem *phy_base, int rank)
{ {
void __iomem *dx_base = phy_base + PHY_DX_BASE; void __iomem *dx_base = phy_base + PHY_DX_BASE;