video: stm32: stm32_ltdc: add bridge to display controller
Manage a bridge insert between the display controller & a panel. Signed-off-by: Yannick Fertré <yannick.fertre@st.com>
This commit is contained in:
Yannick Fertré
Anatolij Gustschin
parent
7a779ed175
commit
aeaf330649
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@ -7,19 +7,18 @@
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#include <common.h>
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#include <clk.h>
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#include <display.h>
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#include <dm.h>
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#include <panel.h>
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#include <reset.h>
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#include <video.h>
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#include <video_bridge.h>
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#include <asm/io.h>
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#include <asm/arch/gpio.h>
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#include <dm/device-internal.h>
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DECLARE_GLOBAL_DATA_PTR;
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struct stm32_ltdc_priv {
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void __iomem *regs;
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struct display_timing timing;
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enum video_log2_bpp l2bpp;
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u32 bg_col_argb;
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u32 crop_x, crop_y, crop_w, crop_h;
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@ -174,8 +173,8 @@ static u32 stm32_ltdc_get_pixel_format(enum video_log2_bpp l2bpp)
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case VIDEO_BPP2:
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case VIDEO_BPP4:
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default:
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debug("%s: warning %dbpp not supported yet, %dbpp instead\n",
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__func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
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pr_warn("%s: warning %dbpp not supported yet, %dbpp instead\n",
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__func__, VNBITS(l2bpp), VNBITS(VIDEO_BPP16));
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pf = PF_RGB565;
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break;
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}
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@ -209,23 +208,23 @@ static void stm32_ltdc_enable(struct stm32_ltdc_priv *priv)
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setbits_le32(priv->regs + LTDC_GCR, GCR_LTDCEN);
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}
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static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
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static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv,
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struct display_timing *timings)
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{
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void __iomem *regs = priv->regs;
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struct display_timing *timing = &priv->timing;
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u32 hsync, vsync, acc_hbp, acc_vbp, acc_act_w, acc_act_h;
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u32 total_w, total_h;
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u32 val;
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/* Convert video timings to ltdc timings */
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hsync = timing->hsync_len.typ - 1;
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vsync = timing->vsync_len.typ - 1;
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acc_hbp = hsync + timing->hback_porch.typ;
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acc_vbp = vsync + timing->vback_porch.typ;
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acc_act_w = acc_hbp + timing->hactive.typ;
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acc_act_h = acc_vbp + timing->vactive.typ;
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total_w = acc_act_w + timing->hfront_porch.typ;
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total_h = acc_act_h + timing->vfront_porch.typ;
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hsync = timings->hsync_len.typ - 1;
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vsync = timings->vsync_len.typ - 1;
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acc_hbp = hsync + timings->hback_porch.typ;
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acc_vbp = vsync + timings->vback_porch.typ;
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acc_act_w = acc_hbp + timings->hactive.typ;
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acc_act_h = acc_vbp + timings->vactive.typ;
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total_w = acc_act_w + timings->hfront_porch.typ;
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total_h = acc_act_h + timings->vfront_porch.typ;
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/* Synchronization sizes */
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val = (hsync << 16) | vsync;
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@ -247,14 +246,14 @@ static void stm32_ltdc_set_mode(struct stm32_ltdc_priv *priv)
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/* Signal polarities */
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val = 0;
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debug("%s: timing->flags 0x%08x\n", __func__, timing->flags);
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if (timing->flags & DISPLAY_FLAGS_HSYNC_HIGH)
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debug("%s: timing->flags 0x%08x\n", __func__, timings->flags);
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if (timings->flags & DISPLAY_FLAGS_HSYNC_HIGH)
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val |= GCR_HSPOL;
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if (timing->flags & DISPLAY_FLAGS_VSYNC_HIGH)
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if (timings->flags & DISPLAY_FLAGS_VSYNC_HIGH)
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val |= GCR_VSPOL;
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if (timing->flags & DISPLAY_FLAGS_DE_HIGH)
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if (timings->flags & DISPLAY_FLAGS_DE_HIGH)
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val |= GCR_DEPOL;
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if (timing->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
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if (timings->flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE)
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val |= GCR_PCPOL;
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clrsetbits_le32(regs + LTDC_GCR,
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GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val);
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@ -330,96 +329,120 @@ static int stm32_ltdc_probe(struct udevice *dev)
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struct video_uc_platdata *uc_plat = dev_get_uclass_platdata(dev);
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struct video_priv *uc_priv = dev_get_uclass_priv(dev);
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struct stm32_ltdc_priv *priv = dev_get_priv(dev);
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struct udevice *panel;
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struct udevice *bridge = NULL;
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struct udevice *panel = NULL;
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struct display_timing timings;
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struct clk pclk;
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struct reset_ctl rst;
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int rate, ret;
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int ret;
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priv->regs = (void *)dev_read_addr(dev);
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if ((fdt_addr_t)priv->regs == FDT_ADDR_T_NONE) {
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debug("%s: ltdc dt register address error\n", __func__);
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dev_err(dev, "ltdc dt register address error\n");
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return -EINVAL;
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}
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ret = clk_get_by_index(dev, 0, &pclk);
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if (ret) {
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debug("%s: peripheral clock get error %d\n", __func__, ret);
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dev_err(dev, "peripheral clock get error %d\n", ret);
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return ret;
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}
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ret = clk_enable(&pclk);
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if (ret) {
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debug("%s: peripheral clock enable error %d\n",
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__func__, ret);
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dev_err(dev, "peripheral clock enable error %d\n", ret);
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return ret;
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}
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ret = uclass_first_device_err(UCLASS_PANEL, &panel);
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if (ret) {
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if (ret != -ENODEV)
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dev_err(dev, "panel device error %d\n", ret);
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return ret;
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}
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ret = panel_get_display_timing(panel, &timings);
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if (ret) {
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ret = fdtdec_decode_display_timing(gd->fdt_blob,
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dev_of_offset(panel),
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0, &timings);
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if (ret) {
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dev_err(dev, "decode display timing error %d\n", ret);
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return ret;
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}
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}
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ret = clk_set_rate(&pclk, timings.pixelclock.typ);
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if (ret)
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dev_warn(dev, "fail to set pixel clock %d hz\n",
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timings.pixelclock.typ);
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debug("%s: Set pixel clock req %d hz get %ld hz\n", __func__,
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timings.pixelclock.typ, clk_get_rate(&pclk));
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ret = reset_get_by_index(dev, 0, &rst);
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if (ret) {
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debug("%s: missing ltdc hardware reset\n", __func__);
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return -ENODEV;
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dev_err(dev, "missing ltdc hardware reset\n");
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return ret;
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}
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/* Reset */
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reset_deassert(&rst);
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ret = uclass_first_device(UCLASS_PANEL, &panel);
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if (ret) {
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debug("%s: panel device error %d\n", __func__, ret);
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return ret;
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}
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if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
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ret = uclass_get_device(UCLASS_VIDEO_BRIDGE, 0, &bridge);
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if (ret)
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debug("No video bridge, or no backlight on bridge\n");
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ret = panel_enable_backlight(panel);
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if (ret) {
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debug("%s: panel %s enable backlight error %d\n",
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__func__, panel->name, ret);
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return ret;
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if (bridge) {
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ret = video_bridge_attach(bridge);
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if (ret) {
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dev_err(dev, "fail to attach bridge\n");
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return ret;
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}
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}
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}
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ret = fdtdec_decode_display_timing(gd->fdt_blob,
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dev_of_offset(dev), 0,
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&priv->timing);
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if (ret) {
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debug("%s: decode display timing error %d\n",
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__func__, ret);
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return -EINVAL;
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}
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rate = clk_set_rate(&pclk, priv->timing.pixelclock.typ);
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if (rate < 0) {
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debug("%s: fail to set pixel clock %d hz %d hz\n",
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__func__, priv->timing.pixelclock.typ, rate);
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return rate;
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}
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debug("%s: Set pixel clock req %d hz get %d hz\n", __func__,
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priv->timing.pixelclock.typ, rate);
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/* TODO Below parameters are hard-coded for the moment... */
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priv->l2bpp = VIDEO_BPP16;
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priv->bg_col_argb = 0xFFFFFFFF; /* white no transparency */
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priv->crop_x = 0;
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priv->crop_y = 0;
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priv->crop_w = priv->timing.hactive.typ;
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priv->crop_h = priv->timing.vactive.typ;
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priv->crop_w = timings.hactive.typ;
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priv->crop_h = timings.vactive.typ;
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priv->alpha = 0xFF;
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debug("%s: %dx%d %dbpp frame buffer at 0x%lx\n", __func__,
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priv->timing.hactive.typ, priv->timing.vactive.typ,
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timings.hactive.typ, timings.vactive.typ,
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VNBITS(priv->l2bpp), uc_plat->base);
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debug("%s: crop %d,%d %dx%d bg 0x%08x alpha %d\n", __func__,
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priv->crop_x, priv->crop_y, priv->crop_w, priv->crop_h,
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priv->bg_col_argb, priv->alpha);
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/* Configure & start LTDC */
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stm32_ltdc_set_mode(priv);
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stm32_ltdc_set_mode(priv, &timings);
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stm32_ltdc_set_layer1(priv, uc_plat->base);
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stm32_ltdc_enable(priv);
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uc_priv->xsize = priv->timing.hactive.typ;
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uc_priv->ysize = priv->timing.vactive.typ;
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uc_priv->xsize = timings.hactive.typ;
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uc_priv->ysize = timings.vactive.typ;
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uc_priv->bpix = priv->l2bpp;
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if (!bridge) {
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ret = panel_enable_backlight(panel);
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if (ret) {
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dev_err(dev, "panel %s enable backlight error %d\n",
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panel->name, ret);
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return ret;
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}
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} else if (IS_ENABLED(CONFIG_VIDEO_BRIDGE)) {
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ret = video_bridge_set_backlight(bridge, 80);
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if (ret) {
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dev_err(dev, "fail to set backlight\n");
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return ret;
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}
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}
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video_set_flush_dcache(dev, true);
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return 0;
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