dma: ti: k3-udma: Introduce udma_chan_config struct
Encapsulate channel configuration in a separate struct so as to ease resetting of these fields with memset() and also to increase readability of the code. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
This commit is contained in:
Vignesh Raghavendra
Lokesh Vutla
parent
b3f95997ce
commit
af374c24d9
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@ -137,6 +137,26 @@ struct udma_dev {
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u32 ch_count;
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};
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struct udma_chan_config {
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u32 psd_size; /* size of Protocol Specific Data */
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u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */
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u32 hdesc_size; /* Size of a packet descriptor in packet mode */
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int remote_thread_id;
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u32 atype;
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u32 src_thread;
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u32 dst_thread;
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enum psil_endpoint_type ep_type;
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enum udma_tp_level channel_tpl; /* Channel Throughput Level */
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enum dma_direction dir;
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unsigned int pkt_mode:1; /* TR or packet */
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unsigned int needs_epib:1; /* EPIB is needed for the communication or not */
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unsigned int enable_acc32:1;
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unsigned int enable_burst:1;
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unsigned int notdpkt:1; /* Suppress sending TDC packet */
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};
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struct udma_chan {
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struct udma_dev *ud;
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char name[20];
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@ -149,20 +169,11 @@ struct udma_chan {
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u32 bcnt; /* number of bytes completed since the start of the channel */
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bool pkt_mode; /* TR or packet */
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bool needs_epib; /* EPIB is needed for the communication or not */
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u32 psd_size; /* size of Protocol Specific Data */
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u32 metadata_size; /* (needs_epib ? 16:0) + psd_size */
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int slave_thread_id;
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u32 src_thread;
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u32 dst_thread;
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u32 static_tr_type;
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struct udma_chan_config config;
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u32 id;
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enum dma_direction dir;
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struct cppi5_host_desc_t *desc_tx;
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u32 hdesc_size;
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bool in_use;
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void *desc_rx;
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u32 num_rx_bufs;
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@ -288,7 +299,7 @@ static inline bool udma_is_chan_running(struct udma_chan *uc)
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u32 trt_ctl = 0;
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u32 rrt_ctl = 0;
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switch (uc->dir) {
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switch (uc->config.dir) {
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case DMA_DEV_TO_MEM:
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rrt_ctl = udma_rchanrt_read(uc->rchan, UDMA_RCHAN_RT_CTL_REG);
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pr_debug("%s: rrt_ctl: 0x%08x (peer: 0x%08x)\n",
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@ -322,7 +333,7 @@ static int udma_pop_from_ring(struct udma_chan *uc, dma_addr_t *addr)
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struct k3_nav_ring *ring = NULL;
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int ret = -ENOENT;
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switch (uc->dir) {
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switch (uc->config.dir) {
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case DMA_DEV_TO_MEM:
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ring = uc->rchan->r_ring;
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break;
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@ -347,7 +358,7 @@ static void udma_reset_rings(struct udma_chan *uc)
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struct k3_nav_ring *ring1 = NULL;
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struct k3_nav_ring *ring2 = NULL;
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switch (uc->dir) {
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switch (uc->config.dir) {
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case DMA_DEV_TO_MEM:
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ring1 = uc->rchan->fd_ring;
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ring2 = uc->rchan->r_ring;
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@ -409,7 +420,7 @@ static inline int udma_stop_hard(struct udma_chan *uc)
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{
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pr_debug("%s: ENTER (chan%d)\n", __func__, uc->id);
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switch (uc->dir) {
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switch (uc->config.dir) {
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case DMA_DEV_TO_MEM:
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udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_PEER_RT_EN_REG, 0);
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udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG, 0);
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@ -435,9 +446,8 @@ static int udma_start(struct udma_chan *uc)
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if (udma_is_chan_running(uc))
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goto out;
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pr_debug("%s: chan:%d dir:%s (static_tr_type: %d)\n",
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__func__, uc->id, udma_get_dir_text(uc->dir),
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uc->static_tr_type);
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pr_debug("%s: chan:%d dir:%s\n",
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__func__, uc->id, udma_get_dir_text(uc->config.dir));
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/* Make sure that we clear the teardown bit, if it is set */
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udma_stop_hard(uc);
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@ -445,7 +455,7 @@ static int udma_start(struct udma_chan *uc)
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/* Reset all counters */
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udma_reset_counters(uc);
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switch (uc->dir) {
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switch (uc->config.dir) {
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case DMA_DEV_TO_MEM:
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udma_rchanrt_write(uc->rchan, UDMA_RCHAN_RT_CTL_REG,
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UDMA_CHAN_RT_CTL_EN);
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@ -547,10 +557,10 @@ static inline void udma_stop_dev2mem(struct udma_chan *uc, bool sync)
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static inline int udma_stop(struct udma_chan *uc)
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{
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pr_debug("%s: chan:%d dir:%s\n",
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__func__, uc->id, udma_get_dir_text(uc->dir));
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__func__, uc->id, udma_get_dir_text(uc->config.dir));
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udma_reset_counters(uc);
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switch (uc->dir) {
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switch (uc->config.dir) {
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case DMA_DEV_TO_MEM:
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udma_stop_dev2mem(uc, true);
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break;
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@ -851,7 +861,7 @@ static int udma_alloc_rx_resources(struct udma_chan *uc)
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return ret;
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/* For MEM_TO_MEM we don't need rflow or rings */
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if (uc->dir == DMA_MEM_TO_MEM)
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if (uc->config.dir == DMA_MEM_TO_MEM)
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return 0;
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ret = udma_get_rflow(uc, uc->rchan->id);
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@ -913,7 +923,7 @@ static int udma_alloc_tchan_sci_req(struct udma_chan *uc)
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u32 mode;
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int ret;
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if (uc->pkt_mode)
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if (uc->config.pkt_mode)
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mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
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else
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mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
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@ -924,11 +934,11 @@ static int udma_alloc_tchan_sci_req(struct udma_chan *uc)
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req.nav_id = tisci_rm->tisci_dev_id;
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req.index = uc->tchan->id;
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req.tx_chan_type = mode;
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if (uc->dir == DMA_MEM_TO_MEM)
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if (uc->config.dir == DMA_MEM_TO_MEM)
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req.tx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
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else
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req.tx_fetch_size = cppi5_hdesc_calc_size(uc->needs_epib,
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uc->psd_size,
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req.tx_fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
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uc->config.psd_size,
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0) >> 2;
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req.txcq_qnum = tc_ring;
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@ -951,7 +961,7 @@ static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
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u32 mode;
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int ret;
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if (uc->pkt_mode)
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if (uc->config.pkt_mode)
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mode = TI_SCI_RM_UDMAP_CHAN_TYPE_PKT_PBRR;
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else
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mode = TI_SCI_RM_UDMAP_CHAN_TYPE_3RDP_BCOPY_PBRR;
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@ -964,16 +974,16 @@ static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
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req.nav_id = tisci_rm->tisci_dev_id;
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req.index = uc->rchan->id;
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req.rx_chan_type = mode;
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if (uc->dir == DMA_MEM_TO_MEM) {
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if (uc->config.dir == DMA_MEM_TO_MEM) {
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req.rx_fetch_size = sizeof(struct cppi5_desc_hdr_t) >> 2;
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req.rxcq_qnum = tc_ring;
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} else {
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req.rx_fetch_size = cppi5_hdesc_calc_size(uc->needs_epib,
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uc->psd_size,
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req.rx_fetch_size = cppi5_hdesc_calc_size(uc->config.needs_epib,
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uc->config.psd_size,
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0) >> 2;
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req.rxcq_qnum = rx_ring;
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}
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if (uc->rflow->id != uc->rchan->id && uc->dir != DMA_MEM_TO_MEM) {
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if (uc->rflow->id != uc->rchan->id && uc->config.dir != DMA_MEM_TO_MEM) {
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req.flowid_start = uc->rflow->id;
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req.flowid_cnt = 1;
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}
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@ -984,7 +994,7 @@ static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
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uc->rchan->id, ret);
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return ret;
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}
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if (uc->dir == DMA_MEM_TO_MEM)
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if (uc->config.dir == DMA_MEM_TO_MEM)
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return ret;
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flow_req.valid_params =
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@ -1006,12 +1016,12 @@ static int udma_alloc_rchan_sci_req(struct udma_chan *uc)
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flow_req.nav_id = tisci_rm->tisci_dev_id;
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flow_req.flow_index = uc->rflow->id;
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if (uc->needs_epib)
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if (uc->config.needs_epib)
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flow_req.rx_einfo_present = 1;
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else
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flow_req.rx_einfo_present = 0;
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if (uc->psd_size)
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if (uc->config.psd_size)
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flow_req.rx_psinfo_present = 1;
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else
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flow_req.rx_psinfo_present = 0;
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@ -1044,11 +1054,12 @@ static int udma_alloc_chan_resources(struct udma_chan *uc)
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int ret;
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pr_debug("%s: chan:%d as %s\n",
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__func__, uc->id, udma_get_dir_text(uc->dir));
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__func__, uc->id, udma_get_dir_text(uc->config.dir));
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switch (uc->dir) {
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switch (uc->config.dir) {
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case DMA_MEM_TO_MEM:
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/* Non synchronized - mem to mem type of transfer */
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uc->config.pkt_mode = false;
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ret = udma_get_chan_pair(uc);
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if (ret)
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return ret;
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@ -1061,8 +1072,8 @@ static int udma_alloc_chan_resources(struct udma_chan *uc)
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if (ret)
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goto err_free_res;
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uc->src_thread = ud->psil_base + uc->tchan->id;
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uc->dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
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uc->config.src_thread = ud->psil_base + uc->tchan->id;
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uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
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break;
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case DMA_MEM_TO_DEV:
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/* Slave transfer synchronized - mem to dev (TX) trasnfer */
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@ -1070,10 +1081,9 @@ static int udma_alloc_chan_resources(struct udma_chan *uc)
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if (ret)
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goto err_free_res;
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uc->src_thread = ud->psil_base + uc->tchan->id;
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uc->dst_thread = uc->slave_thread_id;
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if (!(uc->dst_thread & 0x8000))
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uc->dst_thread |= 0x8000;
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uc->config.src_thread = ud->psil_base + uc->tchan->id;
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uc->config.dst_thread = uc->config.remote_thread_id;
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uc->config.dst_thread |= 0x8000;
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break;
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case DMA_DEV_TO_MEM:
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@ -1082,19 +1092,19 @@ static int udma_alloc_chan_resources(struct udma_chan *uc)
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if (ret)
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goto err_free_res;
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uc->src_thread = uc->slave_thread_id;
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uc->dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
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uc->config.src_thread = uc->config.remote_thread_id;
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uc->config.dst_thread = (ud->psil_base + uc->rchan->id) | 0x8000;
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break;
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default:
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/* Can not happen */
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pr_debug("%s: chan:%d invalid direction (%u)\n",
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__func__, uc->id, uc->dir);
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__func__, uc->id, uc->config.dir);
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return -EINVAL;
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}
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/* We have channel indexes and rings */
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if (uc->dir == DMA_MEM_TO_MEM) {
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if (uc->config.dir == DMA_MEM_TO_MEM) {
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ret = udma_alloc_tchan_sci_req(uc);
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if (ret)
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goto err_free_res;
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@ -1104,7 +1114,7 @@ static int udma_alloc_chan_resources(struct udma_chan *uc)
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goto err_free_res;
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} else {
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/* Slave transfer */
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if (uc->dir == DMA_MEM_TO_DEV) {
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if (uc->config.dir == DMA_MEM_TO_DEV) {
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ret = udma_alloc_tchan_sci_req(uc);
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if (ret)
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goto err_free_res;
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@ -1125,7 +1135,7 @@ static int udma_alloc_chan_resources(struct udma_chan *uc)
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}
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/* PSI-L pairing */
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ret = udma_navss_psil_pair(ud, uc->src_thread, uc->dst_thread);
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ret = udma_navss_psil_pair(ud, uc->config.src_thread, uc->config.dst_thread);
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if (ret) {
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dev_err(ud->dev, "k3_nav_psil_request_link fail\n");
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goto err_free_res;
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@ -1136,7 +1146,7 @@ static int udma_alloc_chan_resources(struct udma_chan *uc)
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err_free_res:
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udma_free_tx_resources(uc);
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udma_free_rx_resources(uc);
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uc->slave_thread_id = -1;
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uc->config.remote_thread_id = -1;
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return ret;
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}
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@ -1145,15 +1155,15 @@ static void udma_free_chan_resources(struct udma_chan *uc)
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/* Some configuration to UDMA-P channel: disable, reset, whatever */
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/* Release PSI-L pairing */
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udma_navss_psil_unpair(uc->ud, uc->src_thread, uc->dst_thread);
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udma_navss_psil_unpair(uc->ud, uc->config.src_thread, uc->config.dst_thread);
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/* Reset the rings for a new start */
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udma_reset_rings(uc);
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udma_free_tx_resources(uc);
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udma_free_rx_resources(uc);
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uc->slave_thread_id = -1;
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uc->dir = DMA_MEM_TO_MEM;
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uc->config.remote_thread_id = -1;
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uc->config.dir = DMA_MEM_TO_MEM;
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}
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static int udma_get_mmrs(struct udevice *dev)
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@ -1377,10 +1387,10 @@ static int udma_probe(struct udevice *dev)
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uc->ud = ud;
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uc->id = i;
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uc->slave_thread_id = -1;
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uc->config.remote_thread_id = -1;
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uc->tchan = NULL;
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uc->rchan = NULL;
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uc->dir = DMA_MEM_TO_MEM;
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uc->config.dir = DMA_MEM_TO_MEM;
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sprintf(uc->name, "UDMA chan%d\n", i);
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if (!i)
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uc->in_use = true;
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@ -1527,6 +1537,7 @@ static int udma_transfer(struct udevice *dev, int direction,
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static int udma_request(struct dma *dma)
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{
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struct udma_dev *ud = dev_get_priv(dma->dev);
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struct udma_chan_config *ucc;
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struct udma_chan *uc;
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unsigned long dummy;
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int ret;
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@ -1537,30 +1548,27 @@ static int udma_request(struct dma *dma)
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}
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uc = &ud->channels[dma->id];
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ucc = &uc->config;
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ret = udma_alloc_chan_resources(uc);
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if (ret) {
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dev_err(dma->dev, "alloc dma res failed %d\n", ret);
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return -EINVAL;
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}
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uc->hdesc_size = cppi5_hdesc_calc_size(uc->needs_epib,
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uc->psd_size, 0);
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uc->hdesc_size = ALIGN(uc->hdesc_size, ARCH_DMA_MINALIGN);
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if (uc->dir == DMA_MEM_TO_DEV) {
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uc->desc_tx = dma_alloc_coherent(uc->hdesc_size, &dummy);
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memset(uc->desc_tx, 0, uc->hdesc_size);
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if (uc->config.dir == DMA_MEM_TO_DEV) {
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uc->desc_tx = dma_alloc_coherent(ucc->hdesc_size, &dummy);
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memset(uc->desc_tx, 0, ucc->hdesc_size);
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} else {
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uc->desc_rx = dma_alloc_coherent(
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uc->hdesc_size * UDMA_RX_DESC_NUM, &dummy);
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memset(uc->desc_rx, 0, uc->hdesc_size * UDMA_RX_DESC_NUM);
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ucc->hdesc_size * UDMA_RX_DESC_NUM, &dummy);
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memset(uc->desc_rx, 0, ucc->hdesc_size * UDMA_RX_DESC_NUM);
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}
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uc->in_use = true;
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uc->desc_rx_cur = 0;
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uc->num_rx_bufs = 0;
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if (uc->dir == DMA_DEV_TO_MEM) {
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if (uc->config.dir == DMA_DEV_TO_MEM) {
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uc->cfg_data.flow_id_base = uc->rflow->id;
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uc->cfg_data.flow_id_cnt = 1;
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}
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@ -1645,7 +1653,7 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata)
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}
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uc = &ud->channels[dma->id];
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if (uc->dir != DMA_MEM_TO_DEV)
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if (uc->config.dir != DMA_MEM_TO_DEV)
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return -EINVAL;
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tc_ring_id = k3_nav_ringacc_get_ring_id(uc->tchan->tc_ring);
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@ -1655,8 +1663,8 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata)
|
|||
cppi5_hdesc_reset_hbdesc(desc_tx);
|
||||
|
||||
cppi5_hdesc_init(desc_tx,
|
||||
uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
|
||||
uc->psd_size);
|
||||
uc->config.needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
|
||||
uc->config.psd_size);
|
||||
cppi5_hdesc_set_pktlen(desc_tx, len);
|
||||
cppi5_hdesc_attach_buf(desc_tx, dma_src, len, dma_src, len);
|
||||
cppi5_desc_set_pktids(&desc_tx->hdr, uc->id, 0x3fff);
|
||||
|
|
@ -1669,7 +1677,7 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata)
|
|||
ALIGN((unsigned long)dma_src + len,
|
||||
ARCH_DMA_MINALIGN));
|
||||
flush_dcache_range((unsigned long)desc_tx,
|
||||
ALIGN((unsigned long)desc_tx + uc->hdesc_size,
|
||||
ALIGN((unsigned long)desc_tx + uc->config.hdesc_size,
|
||||
ARCH_DMA_MINALIGN));
|
||||
|
||||
ret = udma_push_to_ring(uc->tchan->t_ring, uc->desc_tx);
|
||||
|
|
@ -1687,6 +1695,7 @@ static int udma_send(struct dma *dma, void *src, size_t len, void *metadata)
|
|||
static int udma_receive(struct dma *dma, void **dst, void *metadata)
|
||||
{
|
||||
struct udma_dev *ud = dev_get_priv(dma->dev);
|
||||
struct udma_chan_config *ucc;
|
||||
struct cppi5_host_desc_t *desc_rx;
|
||||
dma_addr_t buf_dma;
|
||||
struct udma_chan *uc;
|
||||
|
|
@ -1699,8 +1708,9 @@ static int udma_receive(struct dma *dma, void **dst, void *metadata)
|
|||
return -EINVAL;
|
||||
}
|
||||
uc = &ud->channels[dma->id];
|
||||
ucc = &uc->config;
|
||||
|
||||
if (uc->dir != DMA_DEV_TO_MEM)
|
||||
if (uc->config.dir != DMA_DEV_TO_MEM)
|
||||
return -EINVAL;
|
||||
if (!uc->num_rx_bufs)
|
||||
return -EINVAL;
|
||||
|
|
@ -1715,7 +1725,7 @@ static int udma_receive(struct dma *dma, void **dst, void *metadata)
|
|||
|
||||
/* invalidate cache data */
|
||||
invalidate_dcache_range((ulong)desc_rx,
|
||||
(ulong)(desc_rx + uc->hdesc_size));
|
||||
(ulong)(desc_rx + ucc->hdesc_size));
|
||||
|
||||
cppi5_hdesc_get_obuf(desc_rx, &buf_dma, &buf_dma_len);
|
||||
pkt_len = cppi5_hdesc_get_pktlen(desc_rx);
|
||||
|
|
@ -1734,6 +1744,7 @@ static int udma_receive(struct dma *dma, void **dst, void *metadata)
|
|||
|
||||
static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args)
|
||||
{
|
||||
struct udma_chan_config *ucc;
|
||||
struct udma_dev *ud = dev_get_priv(dma->dev);
|
||||
struct udma_chan *uc = &ud->channels[0];
|
||||
struct psil_endpoint_config *ep_config;
|
||||
|
|
@ -1748,32 +1759,40 @@ static int udma_of_xlate(struct dma *dma, struct ofnode_phandle_args *args)
|
|||
if (val == ud->ch_count)
|
||||
return -EBUSY;
|
||||
|
||||
uc->slave_thread_id = args->args[0];
|
||||
if (uc->slave_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)
|
||||
uc->dir = DMA_MEM_TO_DEV;
|
||||
ucc = &uc->config;
|
||||
ucc->remote_thread_id = args->args[0];
|
||||
if (ucc->remote_thread_id & K3_PSIL_DST_THREAD_ID_OFFSET)
|
||||
ucc->dir = DMA_MEM_TO_DEV;
|
||||
else
|
||||
uc->dir = DMA_DEV_TO_MEM;
|
||||
ucc->dir = DMA_DEV_TO_MEM;
|
||||
|
||||
ep_config = psil_get_ep_config(uc->slave_thread_id);
|
||||
ep_config = psil_get_ep_config(ucc->remote_thread_id);
|
||||
if (IS_ERR(ep_config)) {
|
||||
dev_err(ud->dev, "No configuration for psi-l thread 0x%04x\n",
|
||||
uc->slave_thread_id);
|
||||
uc->dir = DMA_MEM_TO_MEM;
|
||||
uc->slave_thread_id = -1;
|
||||
uc->config.remote_thread_id);
|
||||
ucc->dir = DMA_MEM_TO_MEM;
|
||||
ucc->remote_thread_id = -1;
|
||||
return false;
|
||||
}
|
||||
|
||||
uc->pkt_mode = ep_config->pkt_mode;
|
||||
ucc->pkt_mode = ep_config->pkt_mode;
|
||||
ucc->channel_tpl = ep_config->channel_tpl;
|
||||
ucc->notdpkt = ep_config->notdpkt;
|
||||
ucc->ep_type = ep_config->ep_type;
|
||||
|
||||
uc->needs_epib = ep_config->needs_epib;
|
||||
uc->psd_size = ep_config->psd_size;
|
||||
uc->metadata_size = (uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + uc->psd_size;
|
||||
ucc->needs_epib = ep_config->needs_epib;
|
||||
ucc->psd_size = ep_config->psd_size;
|
||||
ucc->metadata_size = (ucc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_SIZE : 0) + ucc->psd_size;
|
||||
|
||||
ucc->hdesc_size = cppi5_hdesc_calc_size(ucc->needs_epib,
|
||||
ucc->psd_size, 0);
|
||||
ucc->hdesc_size = ALIGN(ucc->hdesc_size, ARCH_DMA_MINALIGN);
|
||||
|
||||
dma->id = uc->id;
|
||||
pr_debug("Allocated dma chn:%lu epib:%d psdata:%u meta:%u thread_id:%x\n",
|
||||
dma->id, uc->needs_epib,
|
||||
uc->psd_size, uc->metadata_size,
|
||||
uc->slave_thread_id);
|
||||
dma->id, ucc->needs_epib,
|
||||
ucc->psd_size, ucc->metadata_size,
|
||||
ucc->remote_thread_id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -1792,26 +1811,26 @@ int udma_prepare_rcv_buf(struct dma *dma, void *dst, size_t size)
|
|||
}
|
||||
uc = &ud->channels[dma->id];
|
||||
|
||||
if (uc->dir != DMA_DEV_TO_MEM)
|
||||
if (uc->config.dir != DMA_DEV_TO_MEM)
|
||||
return -EINVAL;
|
||||
|
||||
if (uc->num_rx_bufs >= UDMA_RX_DESC_NUM)
|
||||
return -EINVAL;
|
||||
|
||||
desc_num = uc->desc_rx_cur % UDMA_RX_DESC_NUM;
|
||||
desc_rx = uc->desc_rx + (desc_num * uc->hdesc_size);
|
||||
desc_rx = uc->desc_rx + (desc_num * uc->config.hdesc_size);
|
||||
dma_dst = (dma_addr_t)dst;
|
||||
|
||||
cppi5_hdesc_reset_hbdesc(desc_rx);
|
||||
|
||||
cppi5_hdesc_init(desc_rx,
|
||||
uc->needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
|
||||
uc->psd_size);
|
||||
uc->config.needs_epib ? CPPI5_INFO0_HDESC_EPIB_PRESENT : 0,
|
||||
uc->config.psd_size);
|
||||
cppi5_hdesc_set_pktlen(desc_rx, size);
|
||||
cppi5_hdesc_attach_buf(desc_rx, dma_dst, size, dma_dst, size);
|
||||
|
||||
flush_dcache_range((unsigned long)desc_rx,
|
||||
ALIGN((unsigned long)desc_rx + uc->hdesc_size,
|
||||
ALIGN((unsigned long)desc_rx + uc->config.hdesc_size,
|
||||
ARCH_DMA_MINALIGN));
|
||||
|
||||
udma_push_to_ring(uc->rchan->fd_ring, desc_rx);
|
||||
|
|
|
|||
Loading…
Reference in New Issue