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MLK-18044-1: crypto: caam: Add CAAM support to i.MX8M platforms 

This patch enable CAAM support for i.MX8M platforms.

Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
(cherry picked from commit 1fc92e6e34b06bdee81240ce06326aca1d9c02d8)
This commit is contained in:
Aymen Sghaier 2018-05-01 11:37:22 +02:00 committed by Ye Li
parent 5d797db35d
commit b0f889b77b
5 changed files with 27 additions and 6 deletions
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3
arch/arm/Kconfig
View File

@ -611,6 +611,9 @@ config ARCH_IMX8
config ARCH_IMX8M
bool "NXP i.MX8M platform"
select ARM64
select SYS_FSL_HAS_SEC if SECURE_BOOT
select SYS_FSL_SEC_COMPAT_4
select SYS_FSL_SEC_LE
select DM
select SUPPORT_SPL

12
arch/arm/include/asm/arch-imx8m/imx-regs.h
View File

@ -1,5 +1,5 @@
/*
* Copyright 2017 NXP
* Copyright 2017-2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -129,6 +129,16 @@
#define DDRC_IPS_BASE_ADDR(X) (0x3d400000 + ((X) * 0x2000000))
#define DDR_CSD1_BASE_ADDR 0x40000000
#define CAAM_ARB_BASE_ADDR (0x00100000)
#define CAAM_ARB_END_ADDR (0x00107FFF)
#define CAAM_IPS_BASE_ADDR (0x30900000)
#define CONFIG_SYS_FSL_SEC_OFFSET (0)
#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \
CONFIG_SYS_FSL_SEC_OFFSET)
#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000)
#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \
CONFIG_SYS_FSL_JR0_OFFSET)
#define CONFIG_SYS_FSL_MAX_NUM_OF_SEC 1
#if !defined(__ASSEMBLY__)
#include <asm/types.h>
#include <linux/bitops.h>

1
arch/arm/mach-imx/imx8m/Kconfig
View File

@ -2,6 +2,7 @@ if ARCH_IMX8M
config IMX8M
bool
select HAS_CAAM
select ROM_UNIFIED_SECTIONS
choice

4
drivers/crypto/fsl/jobdesc.c
View File

@ -3,6 +3,7 @@
* Basic job descriptor construction
*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*
@ -14,7 +15,8 @@
#include "jobdesc.h"
#include "rsa_caam.h"
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP) || \
defined(CONFIG_IMX8M)
/*!
* Secure memory run command
*

13
include/fsl_sec.h
View File

@ -2,6 +2,7 @@
* Common internal memory map for some Freescale SoCs
*
* Copyright 2014 Freescale Semiconductor, Inc.
* Copyright 2018 NXP
*
* SPDX-License-Identifier: GPL-2.0+
*/
@ -152,7 +153,8 @@ typedef struct ccsr_sec {
struct jr_regs {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP))
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
u32 irba_l;
u32 irba_h;
#else
@ -166,7 +168,8 @@ struct jr_regs {
u32 rsvd3;
u32 irja;
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP))
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
u32 orba_l;
u32 orba_h;
#else
@ -199,7 +202,8 @@ struct jr_regs {
*/
struct sg_entry {
#if defined(CONFIG_SYS_FSL_SEC_LE) && \
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP))
!(defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M))
uint32_t addr_lo; /* Memory Address - lo */
uint32_t addr_hi; /* Memory Address of start of buffer - hi */
#else
@ -220,7 +224,8 @@ struct sg_entry {
#define BLOB_SIZE(x) ((x) + 32 + 16) /* Blob buffer size */
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
#if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \
defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M)
/* Job Ring Base Address */
#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1))
/* Secure Memory Offset varies accross versions */