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85xx: Use common LSDMR defines from asm/fsl_lbc.h 

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Kumar Gala 2009-03-26 01:34:38 -05:00
parent 0088c298f0
commit b0fe93eda6
13 changed files with 91 additions and 271 deletions
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14
board/freescale/mpc8541cds/mpc8541cds.c
View File

@ -372,21 +372,21 @@ sdram_init(void)
cpu_board_rev = get_cpu_board_revision(); cpu_board_rev = get_cpu_board_revision();
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617; lsdmr_common |= LSDMR_BSMA1617;
} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; lsdmr_common |= LSDMR_BSMA1516;
} else { } else {
/* /*
* Assume something unable to identify itself is * Assume something unable to identify itself is
* really old, and likely has lines 16/17 mapped. * really old, and likely has lines 16/17 mapped.
*/ */
lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617; lsdmr_common |= LSDMR_BSMA1617;
} }
/* /*
* Issue PRECHARGE ALL command. * Issue PRECHARGE ALL command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -396,7 +396,7 @@ sdram_init(void)
* Issue 8 AUTO REFRESH commands. * Issue 8 AUTO REFRESH commands.
*/ */
for (idx = 0; idx < 8; idx++) { for (idx = 0; idx < 8; idx++) {
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -406,7 +406,7 @@ sdram_init(void)
/* /*
* Issue 8 MODE-set command. * Issue 8 MODE-set command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -415,7 +415,7 @@ sdram_init(void)
/* /*
* Issue NORMAL OP command. * Issue NORMAL OP command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);

10
board/freescale/mpc8548cds/mpc8548cds.c
View File

@ -185,12 +185,12 @@ sdram_init(void)
*/ */
cpu_board_rev = get_cpu_board_revision(); cpu_board_rev = get_cpu_board_revision();
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; lsdmr_common |= LSDMR_BSMA1516;
/* /*
* Issue PRECHARGE ALL command. * Issue PRECHARGE ALL command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -200,7 +200,7 @@ sdram_init(void)
* Issue 8 AUTO REFRESH commands. * Issue 8 AUTO REFRESH commands.
*/ */
for (idx = 0; idx < 8; idx++) { for (idx = 0; idx < 8; idx++) {
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -210,7 +210,7 @@ sdram_init(void)
/* /*
* Issue 8 MODE-set command. * Issue 8 MODE-set command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -219,7 +219,7 @@ sdram_init(void)
/* /*
* Issue NORMAL OP command. * Issue NORMAL OP command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);

14
board/freescale/mpc8555cds/mpc8555cds.c
View File

@ -371,21 +371,21 @@ sdram_init(void)
cpu_board_rev = get_cpu_board_revision(); cpu_board_rev = get_cpu_board_revision();
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) { if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617; lsdmr_common |= LSDMR_BSMA1617;
} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) { } else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; lsdmr_common |= LSDMR_BSMA1516;
} else { } else {
/* /*
* Assume something unable to identify itself is * Assume something unable to identify itself is
* really old, and likely has lines 16/17 mapped. * really old, and likely has lines 16/17 mapped.
*/ */
lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617; lsdmr_common |= LSDMR_BSMA1617;
} }
/* /*
* Issue PRECHARGE ALL command. * Issue PRECHARGE ALL command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -395,7 +395,7 @@ sdram_init(void)
* Issue 8 AUTO REFRESH commands. * Issue 8 AUTO REFRESH commands.
*/ */
for (idx = 0; idx < 8; idx++) { for (idx = 0; idx < 8; idx++) {
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -405,7 +405,7 @@ sdram_init(void)
/* /*
* Issue 8 MODE-set command. * Issue 8 MODE-set command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -414,7 +414,7 @@ sdram_init(void)
/* /*
* Issue NORMAL OP command. * Issue NORMAL OP command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);

1
board/freescale/mpc8560ads/mpc8560ads.c
View File

@ -36,6 +36,7 @@
#include <miiphy.h> #include <miiphy.h>
#include <libfdt.h> #include <libfdt.h>
#include <fdt_support.h> #include <fdt_support.h>
#include <asm/fsl_lbc.h>
#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
extern void ddr_enable_ecc(unsigned int dram_size); extern void ddr_enable_ecc(unsigned int dram_size);

10
board/freescale/mpc8568mds/mpc8568mds.c
View File

@ -243,12 +243,12 @@ sdram_init(void)
* MPC8568 uses "new" 15-16 style addressing. * MPC8568 uses "new" 15-16 style addressing.
*/ */
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; lsdmr_common |= LSDMR_BSMA1516;
/* /*
* Issue PRECHARGE ALL command. * Issue PRECHARGE ALL command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -258,7 +258,7 @@ sdram_init(void)
* Issue 8 AUTO REFRESH commands. * Issue 8 AUTO REFRESH commands.
*/ */
for (idx = 0; idx < 8; idx++) { for (idx = 0; idx < 8; idx++) {
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -268,7 +268,7 @@ sdram_init(void)
/* /*
* Issue 8 MODE-set command. * Issue 8 MODE-set command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -277,7 +277,7 @@ sdram_init(void)
/* /*
* Issue NORMAL OP command. * Issue NORMAL OP command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);

10
board/sbc8548/sbc8548.c
View File

@ -184,12 +184,12 @@ sdram_init(void)
* MPC8548 uses "new" 15-16 style addressing. * MPC8548 uses "new" 15-16 style addressing.
*/ */
lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON; lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516; lsdmr_common |= LSDMR_BSMA1516;
/* /*
* Issue PRECHARGE ALL command. * Issue PRECHARGE ALL command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL; lbc->lsdmr = lsdmr_common | LSDMR_OP_PCHALL;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -199,7 +199,7 @@ sdram_init(void)
* Issue 8 AUTO REFRESH commands. * Issue 8 AUTO REFRESH commands.
*/ */
for (idx = 0; idx < 8; idx++) { for (idx = 0; idx < 8; idx++) {
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH; lbc->lsdmr = lsdmr_common | LSDMR_OP_ARFRSH;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -209,7 +209,7 @@ sdram_init(void)
/* /*
* Issue 8 MODE-set command. * Issue 8 MODE-set command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW; lbc->lsdmr = lsdmr_common | LSDMR_OP_MRW;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);
@ -218,7 +218,7 @@ sdram_init(void)
/* /*
* Issue NORMAL OP command. * Issue NORMAL OP command.
*/ */
lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL; lbc->lsdmr = lsdmr_common | LSDMR_OP_NORMAL;
asm("sync;msync"); asm("sync;msync");
*sdram_addr = 0xff; *sdram_addr = 0xff;
ppcDcbf((unsigned long) sdram_addr); ppcDcbf((unsigned long) sdram_addr);

59
include/configs/MPC8540ADS.h
View File

@ -197,57 +197,24 @@
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
/* #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
* LSDMR masks | LSDMR_RFCR5 \
*/ | LSDMR_PRETOACT3 \
#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1)) | LSDMR_ACTTORW3 \
#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) | LSDMR_BL8 \
#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) | LSDMR_WRC2 \
#define CONFIG_SYS_LBC_LSDMR_RFCR5 (3 << (31 - 16)) | LSDMR_CL3 \
#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16)) | LSDMR_RFEN \
#define CONFIG_SYS_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
#define CONFIG_SYS_LBC_LSDMR_WRC2 (2 << (31 - 27))
#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
#define CONFIG_SYS_LBC_LSDMR_BUFCMD (1 << (31 - 29))
#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_BSMA1516 \
| CONFIG_SYS_LBC_LSDMR_RFCR5 \
| CONFIG_SYS_LBC_LSDMR_PRETOACT3 \
| CONFIG_SYS_LBC_LSDMR_ACTTORW3 \
| CONFIG_SYS_LBC_LSDMR_BL8 \
| CONFIG_SYS_LBC_LSDMR_WRC2 \
| CONFIG_SYS_LBC_LSDMR_CL3 \
| CONFIG_SYS_LBC_LSDMR_RFEN \
) )
/* /*
* SDRAM Controller configuration sequence. * SDRAM Controller configuration sequence.
*/ */
#define CONFIG_SYS_LBC_LSDMR_1 ( CONFIG_SYS_LBC_LSDMR_COMMON \ #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
| CONFIG_SYS_LBC_LSDMR_OP_PCHALL) #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_2 ( CONFIG_SYS_LBC_LSDMR_COMMON \ #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH) #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_3 ( CONFIG_SYS_LBC_LSDMR_COMMON \ #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4 ( CONFIG_SYS_LBC_LSDMR_COMMON \
| CONFIG_SYS_LBC_LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5 ( CONFIG_SYS_LBC_LSDMR_COMMON \
| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
/* /*

37
include/configs/MPC8541CDS.h
View File

@ -206,42 +206,19 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
*/
#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1))
#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16))
#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
/* /*
* Common settings for all Local Bus SDRAM commands. * Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1) * At run time, either BSMA1516 (for CPU 1.1)
* or BSMA1617 (for CPU 1.0) (old) * or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too. * is OR'ed in too.
*/ */
#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \ #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
| CONFIG_SYS_LBC_LSDMR_PRETOACT7 \ | LSDMR_PRETOACT7 \
| CONFIG_SYS_LBC_LSDMR_ACTTORW7 \ | LSDMR_ACTTORW7 \
| CONFIG_SYS_LBC_LSDMR_BL8 \ | LSDMR_BL8 \
| CONFIG_SYS_LBC_LSDMR_WRC4 \ | LSDMR_WRC4 \
| CONFIG_SYS_LBC_LSDMR_CL3 \ | LSDMR_CL3 \
| CONFIG_SYS_LBC_LSDMR_RFEN \ | LSDMR_RFEN \
) )
/* /*

37
include/configs/MPC8548CDS.h
View File

@ -228,42 +228,19 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
*/
#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1))
#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16))
#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
/* /*
* Common settings for all Local Bus SDRAM commands. * Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1) * At run time, either BSMA1516 (for CPU 1.1)
* or BSMA1617 (for CPU 1.0) (old) * or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too. * is OR'ed in too.
*/ */
#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \ #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
| CONFIG_SYS_LBC_LSDMR_PRETOACT7 \ | LSDMR_PRETOACT7 \
| CONFIG_SYS_LBC_LSDMR_ACTTORW7 \ | LSDMR_ACTTORW7 \
| CONFIG_SYS_LBC_LSDMR_BL8 \ | LSDMR_BL8 \
| CONFIG_SYS_LBC_LSDMR_WRC4 \ | LSDMR_WRC4 \
| CONFIG_SYS_LBC_LSDMR_CL3 \ | LSDMR_CL3 \
| CONFIG_SYS_LBC_LSDMR_RFEN \ | LSDMR_RFEN \
) )
/* /*

37
include/configs/MPC8555CDS.h
View File

@ -204,42 +204,19 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
*/
#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1))
#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16))
#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
/* /*
* Common settings for all Local Bus SDRAM commands. * Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1) * At run time, either BSMA1516 (for CPU 1.1)
* or BSMA1617 (for CPU 1.0) (old) * or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too. * is OR'ed in too.
*/ */
#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \ #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
| CONFIG_SYS_LBC_LSDMR_PRETOACT7 \ | LSDMR_PRETOACT7 \
| CONFIG_SYS_LBC_LSDMR_ACTTORW7 \ | LSDMR_ACTTORW7 \
| CONFIG_SYS_LBC_LSDMR_BL8 \ | LSDMR_BL8 \
| CONFIG_SYS_LBC_LSDMR_WRC4 \ | LSDMR_WRC4 \
| CONFIG_SYS_LBC_LSDMR_CL3 \ | LSDMR_CL3 \
| CONFIG_SYS_LBC_LSDMR_RFEN \ | LSDMR_RFEN \
) )
/* /*

59
include/configs/MPC8560ADS.h
View File

@ -193,57 +193,24 @@
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
/* #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
* LSDMR masks | LSDMR_RFCR5 \
*/ | LSDMR_PRETOACT3 \
#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1)) | LSDMR_ACTTORW3 \
#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) | LSDMR_BL8 \
#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) | LSDMR_WRC2 \
#define CONFIG_SYS_LBC_LSDMR_RFCR5 (3 << (31 - 16)) | LSDMR_CL3 \
#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16)) | LSDMR_RFEN \
#define CONFIG_SYS_LBC_LSDMR_PRETOACT3 (3 << (31 - 19))
#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW3 (3 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
#define CONFIG_SYS_LBC_LSDMR_WRC2 (2 << (31 - 27))
#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
#define CONFIG_SYS_LBC_LSDMR_BUFCMD (1 << (31 - 29))
#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_BSMA1516 \
| CONFIG_SYS_LBC_LSDMR_RFCR5 \
| CONFIG_SYS_LBC_LSDMR_PRETOACT3 \
| CONFIG_SYS_LBC_LSDMR_ACTTORW3 \
| CONFIG_SYS_LBC_LSDMR_BL8 \
| CONFIG_SYS_LBC_LSDMR_WRC2 \
| CONFIG_SYS_LBC_LSDMR_CL3 \
| CONFIG_SYS_LBC_LSDMR_RFEN \
) )
/* /*
* SDRAM Controller configuration sequence. * SDRAM Controller configuration sequence.
*/ */
#define CONFIG_SYS_LBC_LSDMR_1 ( CONFIG_SYS_LBC_LSDMR_COMMON \ #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
| CONFIG_SYS_LBC_LSDMR_OP_PCHALL) #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_2 ( CONFIG_SYS_LBC_LSDMR_COMMON \ #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH) #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_3 ( CONFIG_SYS_LBC_LSDMR_COMMON \ #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
| CONFIG_SYS_LBC_LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4 ( CONFIG_SYS_LBC_LSDMR_COMMON \
| CONFIG_SYS_LBC_LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5 ( CONFIG_SYS_LBC_LSDMR_COMMON \
| CONFIG_SYS_LBC_LSDMR_OP_NORMAL)
/* /*

37
include/configs/MPC8568MDS.h
View File

@ -187,42 +187,19 @@ extern unsigned long get_clock_freq(void);
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
*/
#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1))
#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16))
#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
/* /*
* Common settings for all Local Bus SDRAM commands. * Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1) * At run time, either BSMA1516 (for CPU 1.1)
* or BSMA1617 (for CPU 1.0) (old) * or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too. * is OR'ed in too.
*/ */
#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \ #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
| CONFIG_SYS_LBC_LSDMR_PRETOACT7 \ | LSDMR_PRETOACT7 \
| CONFIG_SYS_LBC_LSDMR_ACTTORW7 \ | LSDMR_ACTTORW7 \
| CONFIG_SYS_LBC_LSDMR_BL8 \ | LSDMR_BL8 \
| CONFIG_SYS_LBC_LSDMR_WRC4 \ | LSDMR_WRC4 \
| CONFIG_SYS_LBC_LSDMR_CL3 \ | LSDMR_CL3 \
| CONFIG_SYS_LBC_LSDMR_RFEN \ | LSDMR_RFEN \
) )
/* /*

37
include/configs/sbc8548.h
View File

@ -241,42 +241,19 @@
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
/*
* LSDMR masks
*/
#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1))
#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10))
#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10))
#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16))
#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22))
#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23))
#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27))
#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31))
#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4))
#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4))
/* /*
* Common settings for all Local Bus SDRAM commands. * Common settings for all Local Bus SDRAM commands.
* At run time, either BSMA1516 (for CPU 1.1) * At run time, either BSMA1516 (for CPU 1.1)
* or BSMA1617 (for CPU 1.0) (old) * or BSMA1617 (for CPU 1.0) (old)
* is OR'ed in too. * is OR'ed in too.
*/ */
#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \ #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
| CONFIG_SYS_LBC_LSDMR_PRETOACT7 \ | LSDMR_PRETOACT7 \
| CONFIG_SYS_LBC_LSDMR_ACTTORW7 \ | LSDMR_ACTTORW7 \
| CONFIG_SYS_LBC_LSDMR_BL8 \ | LSDMR_BL8 \
| CONFIG_SYS_LBC_LSDMR_WRC4 \ | LSDMR_WRC4 \
| CONFIG_SYS_LBC_LSDMR_CL3 \ | LSDMR_CL3 \
| CONFIG_SYS_LBC_LSDMR_RFEN \ | LSDMR_RFEN \
) )
#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_LOCK 1