From b1f61bad65780d4520910052675899bac9859ce7 Mon Sep 17 00:00:00 2001 From: Rene Straub Date: Fri, 27 Sep 2019 11:40:31 +0200 Subject: [PATCH] nrhw24: add pmic reset reason detection --- board/nm/common/da9063.h | 5 ++- board/nm/nrhw24/board.c | 55 ++++++++++++++++++++++++++++++++- include/configs/am335x_nrhw24.h | 9 ++++-- 3 files changed, 65 insertions(+), 4 deletions(-) diff --git a/board/nm/common/da9063.h b/board/nm/common/da9063.h index d0bde44d07..ee8ceb635b 100644 --- a/board/nm/common/da9063.h +++ b/board/nm/common/da9063.h @@ -19,7 +19,10 @@ TODO: Add include for uint32_t (stdtypes.h) #define CONFIG_PMIC_I2C_BUS 0 #define CONFIG_PMIC_I2C_ADDR 0x58 /* Pages 0 and 1, Pages 2 and 3 -> 0x59 */ -#define PMIC_REG_STATUS_A 0x01 /* Status of ON_KEY, WAKE, COMP1V2, DVC */ +#define PMIC_REG_STATUS_A 0x01 /* Status of ON_KEY, WAKE, COMP1V2, DVC */ +#define PMIC_REG_FAULT_LOG 0x05 /* PMIC fault log register, holding reset reason */ +#define PMIC_FAULT_TWD_ERROR_MASK 0x01 /* Watchdog timeout detected */ + #define PMIC_REG_CONTROL_D 0x11 /* Control register for blink/watchdog */ #define PMIC_REG_GPIO14_15 0x1C /* Configuration of GPIO14/15 (mode, wake) */ #define PMIC_REG_GPIO_MODE0_7 0x1D /* Control register for GPIOs 0..7 */ diff --git a/board/nm/nrhw24/board.c b/board/nm/nrhw24/board.c index 81e7be67f0..74c6fed09e 100644 --- a/board/nm/nrhw24/board.c +++ b/board/nm/nrhw24/board.c @@ -338,7 +338,58 @@ static void init_pmic_spl(void) /* Enable charging of RTC backup capacitor (1mA, 3.1V) */ (void)da9063_set_reg(PMIC_REG_BBAT_CONT, 0xAF); - /* TODO: Check documentation 1 mA correct ? */ + + da9063_release_i2c_bus(bus); +} + +struct reset_registers { + uint32_t value; + uint32_t value_crc; +}; + +/* TODO: Move ethernet crc to dedicated file */ +static uint32_t ether_crc(size_t len, uint8_t const *p) +{ + uint32_t crc; + unsigned i; + + crc = ~0; + while (len--) { + crc ^= *p++; + for (i = 0; i < 8; i++) + crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0); + } + + /* an reverse the bits, cuz of way they arrive -- last-first */ + crc = (crc >> 16) | (crc << 16); + crc = (crc >> 8 & 0x00ff00ff) | (crc << 8 & 0xff00ff00); + crc = (crc >> 4 & 0x0f0f0f0f) | (crc << 4 & 0xf0f0f0f0); + crc = (crc >> 2 & 0x33333333) | (crc << 2 & 0xcccccccc); + crc = (crc >> 1 & 0x55555555) | (crc << 1 & 0xaaaaaaaa); + + return crc; +} + +void check_pmic_reset_reason(unsigned int reset_reason_shm_location) +{ + volatile struct reset_registers* reset_regs = (struct reset_registers*)reset_reason_shm_location; + uint8_t state = 0x00; + int bus; + int ret; + + bus = da9063_claim_i2c_bus(); + + ret = da9063_get_reg(PMIC_REG_FAULT_LOG, &state); + if ((ret == 0) && (state != 0)) { + if (state & PMIC_FAULT_TWD_ERROR_MASK) { + reset_regs->value = EXTERNAL_WATCHDOG_PATTERN; + reset_regs->value_crc = ether_crc(sizeof(reset_regs->value), + (const uint8_t*)&(reset_regs->value)); + } + + /* clear pmic fault log by writing back all bits currently set */ + da9063_set_reg(PMIC_REG_FAULT_LOG, state); + } da9063_release_i2c_bus(bus); } @@ -364,6 +415,8 @@ void am33xx_spl_board_init(void) /* Set MPU Frequency to what we detected now that voltages are set */ do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100); + check_pmic_reset_reason(RESET_REASON_SHM_LOCATION); + /* Debugger can place marker at end of SRAM to stop boot here */ if (is_jtag_boot(CONFIG_JTAG_MARKER_SPL)) { diff --git a/include/configs/am335x_nrhw24.h b/include/configs/am335x_nrhw24.h index 8a6ad544a7..63ea15ce9c 100644 --- a/include/configs/am335x_nrhw24.h +++ b/include/configs/am335x_nrhw24.h @@ -71,7 +71,8 @@ int eth_phy_timeout(void); * 0x84000000 126MB RD_ADDR (ramdisk_addr_r), ramdisc loading address * 0x8BE00000 2MB PXE_ADDR (pxefile_addr_r), pxe configuration file (pxe get command) * 0x8C000000 1MB LOAD_ADDR (load_addr), loading address for generic files - * 0x8C100000 63MB KERNEL_ADDR_R (kernel_addr_r), kernel loading address (will be relocated to kernel_addr) + * 0x8C100000 31MB KERNEL_ADDR_R (kernel_addr_r), kernel loading address (will be relocated to kernel_addr) + * 0x8E000000 4B NRSW reset reason * 0x90000000 256MB <>, Free space 512MB systems * 0xA0000000 512MB <>, Free space, 1GB systems only * 0xC0000000 End of RAM @@ -290,7 +291,7 @@ int eth_phy_timeout(void); #define CONFIG_SYS_MEMTEST_START 0x84000000 #define CONFIG_SYS_MEMTEST_END 0x87900000 -/* Enable for NRSW support +/* TODO: Enable for NRSW support #define CONFIG_NM_LOGIN #define CONFIG_CRYPT */ @@ -302,6 +303,10 @@ int eth_phy_timeout(void); #define CONFIG_JTAG_MARKER_SPL 0x402FFF00 #define CONFIG_JTAG_MARKER_UBOOT 0x807FFF00 +/* TODO: NRSW PMIC Reset Reason */ +#define RESET_REASON_SHM_LOCATION 0x8e000000 +#define EXTERNAL_WATCHDOG_PATTERN 0x781f9ce2 + /* SPL command is not needed */ #undef CONFIG_CMD_SPL