gdsys: mpc8308: Migrate SYS_FPGA{0, 1}_{BASE, SIZE} to Kconfig
Move CONFIG_SYS_FPGA0_BASE, CONFIG_SYS_FPGA0_SIZE, CONFIG_SYS_FPGA1_BASE, and CONFIG_SYS_FPGA1_SIZE to Kconfig. Signed-off-by: Mario Six <mario.six@gdsys.cc>
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					@ -4,6 +4,28 @@ config GDSYS_LEGACY_OSD_CMDS
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	  Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by
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						  Use the 'osdw', 'osdp', and 'osdsize' legacy commands required by
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	  gdsys devices.
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						  gdsys devices.
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					config SYS_FPGA0_BASE
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						hex
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						default E0600000
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						help
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						  The base address of the first FPGA's register map.
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					config SYS_FPGA0_SIZE
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						hex
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						default 1
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						help
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						  The base address of the first FPGA's register map.
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					config SYS_FPGA1_BASE
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						hex
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						help
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						  The base address of the second FPGA's register map.
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					config SYS_FPGA1_SIZE
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						hex
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						help
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						  The base address of the second FPGA's register map.
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if TARGET_HRCON
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					if TARGET_HRCON
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config SYS_BOARD
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					config SYS_BOARD
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					@ -129,14 +129,6 @@
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#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
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					#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
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					#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
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/*
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 * FPGA
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 */
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#define CONFIG_SYS_FPGA0_BASE		0xE0600000
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#define CONFIG_SYS_FPGA0_SIZE		1 /* FPGA size is 1M */
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#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
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#define CONFIG_SYS_FPGA_DONE(k)		0x0010
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					#define CONFIG_SYS_FPGA_DONE(k)		0x0010
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#define CONFIG_SYS_FPGA_COUNT		1
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					#define CONFIG_SYS_FPGA_COUNT		1
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					@ -127,14 +127,6 @@
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#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
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					#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
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#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
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					#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */
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/*
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 * FPGA
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 */
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#define CONFIG_SYS_FPGA0_BASE		0xE0600000
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#define CONFIG_SYS_FPGA0_SIZE		1 /* FPGA size is 1M */
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#define CONFIG_SYS_FPGA_BASE(k)		CONFIG_SYS_FPGA0_BASE
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#define CONFIG_SYS_FPGA_DONE(k)		0x0010
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					#define CONFIG_SYS_FPGA_DONE(k)		0x0010
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#define CONFIG_SYS_FPGA_COUNT		1
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					#define CONFIG_SYS_FPGA_COUNT		1
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