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arm: socfpga: soc64: Show reset state in SPL 

Print reset state (warm/cold) together with the
source (watchdog/MPU) which has triggered the warm
reset on S10 & Agilex.

Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
This commit is contained in:
Chee Hong Ang 2020-08-05 21:15:57 +08:00 committed by Ley Foon Tan
parent d7a1ff40d6
commit b3e2d9fccb
4 changed files with 25 additions and 0 deletions
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1
arch/arm/mach-socfpga/include/mach/reset_manager_soc64.h
View File

@ -8,6 +8,7 @@
void reset_deassert_peripherals_handoff(void);
int cpu_has_been_warmreset(void);
void print_reset_info(void);
void socfpga_bridges_reset(int enable);
#define RSTMGR_SOC64_STATUS 0x00

22
arch/arm/mach-socfpga/reset_manager_s10.c
View File

@ -104,3 +104,25 @@ int cpu_has_been_warmreset(void)
return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
RSTMGR_L4WD_MPU_WARMRESET_MASK;
}
void print_reset_info(void)
{
bool iswd;
int n;
u32 stat = cpu_has_been_warmreset();
printf("Reset state: %s%s", stat ? "Warm " : "Cold",
(stat & RSTMGR_STAT_SDMWARMRST) ? "[from SDM] " : "");
stat &= ~RSTMGR_STAT_SDMWARMRST;
if (!stat) {
puts("\n");
return;
}
n = generic_ffs(stat) - 1;
iswd = (n >= RSTMGR_STAT_L4WD0RST_BITPOS);
printf("(Triggered by %s %d)\n", iswd ? "Watchdog" : "MPU",
iswd ? (n - RSTMGR_STAT_L4WD0RST_BITPOS) :
(n - RSTMGR_STAT_MPU0RST_BITPOS));
}

1
arch/arm/mach-socfpga/spl_agilex.c
View File

@ -76,6 +76,7 @@ void board_init_f(ulong dummy)
}
preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();

1
arch/arm/mach-socfpga/spl_s10.c
View File

@ -81,6 +81,7 @@ void board_init_f(ulong dummy)
#endif
preloader_console_init();
print_reset_info();
cm_print_clock_quick_summary();
firewall_setup();