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arm: Remove SANSA_FUZE_PLUS board 

This board has not been converted to CONFIG_DM_MMC by the deadline.
Remove it.

Cc: Marek Vasut <marek.vasut@gmail.com>
Signed-off-by: Tom Rini <trini@konsulko.com>
This commit is contained in:
Tom Rini 2021-02-20 20:05:40 -05:00
parent 539fba2c10
commit b40186fc7e
8 changed files with 0 additions and 650 deletions
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4
arch/arm/mach-imx/mxs/Kconfig
View File

@ -16,9 +16,6 @@ config TARGET_MX23EVK
bool "Support mx23evk" bool "Support mx23evk"
select BOARD_EARLY_INIT_F select BOARD_EARLY_INIT_F
config TARGET_SANSA_FUZE_PLUS
bool "Support sansa_fuze_plus"
config TARGET_XFI3 config TARGET_XFI3
bool "Support xfi3" bool "Support xfi3"
@ -29,7 +26,6 @@ config SYS_SOC
source "board/olimex/mx23_olinuxino/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig"
source "board/freescale/mx23evk/Kconfig" source "board/freescale/mx23evk/Kconfig"
source "board/sandisk/sansa_fuze_plus/Kconfig"
endif endif

15
board/sandisk/sansa_fuze_plus/Kconfig
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@ -1,15 +0,0 @@
if TARGET_SANSA_FUZE_PLUS
config SYS_BOARD
default "sansa_fuze_plus"
config SYS_VENDOR
default "sandisk"
config SYS_SOC
default "mxs"
config SYS_CONFIG_NAME
default "sansa_fuze_plus"
endif

6
board/sandisk/sansa_fuze_plus/MAINTAINERS
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@ -1,6 +0,0 @@
SANSA_FUZE_PLUS BOARD
M: Marek Vasut <marek.vasut@gmail.com>
S: Maintained
F: board/sandisk/sansa_fuze_plus/
F: include/configs/sansa_fuze_plus.h
F: configs/sansa_fuze_plus_defconfig

10
board/sandisk/sansa_fuze_plus/Makefile
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@ -1,10 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# (C) Copyright 2000-2006
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
ifndef CONFIG_SPL_BUILD
obj-y := sfp.o
else
obj-y := spl_boot.o
endif

391
board/sandisk/sansa_fuze_plus/sfp.c
View File

@ -1,391 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* SanDisk Sansa Fuze Plus board
*
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
*
* Hardware investigation done by:
*
* Amaury Pouly <amaury.pouly@gmail.com>
*/
#include <common.h>
#include <errno.h>
#include <init.h>
#include <net.h>
#include <asm/global_data.h>
#include <asm/gpio.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx23.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/clock.h>
#include <asm/arch/sys_proto.h>
#include <linux/delay.h>
DECLARE_GLOBAL_DATA_PTR;
/*
* Functions
*/
int board_early_init_f(void)
{
/* IO0 clock at 480MHz */
mxs_set_ioclk(MXC_IOCLK0, 480000);
/* SSP0 clock at 96MHz */
mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
return 0;
}
int dram_init(void)
{
return mxs_dram_init();
}
#ifdef CONFIG_CMD_MMC
static int xfi3_mmc_cd(int id)
{
switch (id) {
case 0:
/* The SSP_DETECT is inverted on this board. */
return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
case 1:
/* Internal eMMC always present */
return 1;
default:
return 0;
}
}
int board_mmc_init(struct bd_info *bis)
{
int ret;
/* MicroSD slot */
gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
gpio_direction_output(MX23_PAD_GPMI_D08__GPIO_0_8, 0);
ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
if (ret)
return ret;
/* Internal eMMC */
gpio_direction_output(MX23_PAD_PWM3__GPIO_1_29, 0);
ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
return ret;
}
#endif
#ifdef CONFIG_VIDEO_MXS
#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
const iomux_cfg_t iomux_lcd_gpio[] = {
MX23_PAD_LCD_D00__GPIO_1_0 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D01__GPIO_1_1 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D02__GPIO_1_2 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D03__GPIO_1_3 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D04__GPIO_1_4 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D05__GPIO_1_5 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D06__GPIO_1_6 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D07__GPIO_1_7 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D08__GPIO_1_8 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D09__GPIO_1_9 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D10__GPIO_1_10 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D11__GPIO_1_11 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D12__GPIO_1_12 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D13__GPIO_1_13 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D14__GPIO_1_14 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D15__GPIO_1_15 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D16__GPIO_1_16 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D17__GPIO_1_17 | MUX_CONFIG_LCD,
MX23_PAD_LCD_RESET__GPIO_1_18 | MUX_CONFIG_LCD,
MX23_PAD_LCD_RS__GPIO_1_19 | MUX_CONFIG_LCD,
MX23_PAD_LCD_WR__GPIO_1_20 | MUX_CONFIG_LCD,
MX23_PAD_LCD_CS__GPIO_1_21 | MUX_CONFIG_LCD,
MX23_PAD_LCD_ENABLE__GPIO_1_23 | MUX_CONFIG_LCD,
};
const iomux_cfg_t iomux_lcd_lcd[] = {
MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD,
MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
};
static int mxsfb_read_register(uint32_t reg, uint32_t *value)
{
iomux_cfg_t mux;
uint32_t val = 0;
int i;
/* Mangle the register offset. */
reg = ((reg & 0xff) << 1) | (((reg >> 8) & 0xff) << 10);
/*
* The SmartLCD interface on MX233 can only do WRITE operation
* via the LCDIF controller. Implement the READ operation by
* fiddling with bits.
*/
mxs_iomux_setup_multiple_pads(iomux_lcd_gpio,
ARRAY_SIZE(iomux_lcd_gpio));
gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1);
gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1);
gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1);
gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1);
for (i = 0; i < 18; i++) {
mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO);
gpio_direction_output(mux, 0);
}
udelay(2);
gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 0);
udelay(1);
gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 0);
udelay(1);
gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 0);
udelay(1);
for (i = 0; i < 18; i++) {
mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO);
gpio_direction_output(mux, (reg >> i) & 1);
}
udelay(1);
gpio_direction_output(MX23_PAD_LCD_WR__GPIO_1_20, 1);
udelay(3);
for (i = 0; i < 18; i++) {
mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO);
gpio_direction_input(mux);
}
udelay(2);
gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0);
udelay(1);
gpio_direction_output(MX23_PAD_LCD_RS__GPIO_1_19, 1);
udelay(1);
gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1);
udelay(3);
gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 0);
udelay(2);
for (i = 0; i < 18; i++) {
mux = MXS_IOMUX_PAD_NAKED(1, i, PAD_MUXSEL_GPIO);
val |= !!gpio_get_value(mux) << i;
}
udelay(1);
gpio_direction_output(MX23_PAD_LCD_ENABLE__GPIO_1_23, 1);
udelay(1);
gpio_direction_output(MX23_PAD_LCD_CS__GPIO_1_21, 1);
udelay(1);
mxs_iomux_setup_multiple_pads(iomux_lcd_lcd,
ARRAY_SIZE(iomux_lcd_lcd));
/* Demangle the register value. */
*value = ((val >> 1) & 0xff) | ((val >> 2) & 0xff00);
writel(val, 0x2000);
return 0;
}
static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
{
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
const unsigned int timeout = 0x10000;
/* What is going on here I do not know. FIXME */
payload = ((payload & 0xff) << 1) | (((payload >> 8) & 0xff) << 10);
if (mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
timeout))
return -ETIMEDOUT;
writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
(1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
&regs->hw_lcdif_transfer_count);
writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
&regs->hw_lcdif_ctrl_clr);
if (data)
writel(LCDIF_CTRL_DATA_SELECT, &regs->hw_lcdif_ctrl_set);
writel(LCDIF_CTRL_RUN, &regs->hw_lcdif_ctrl_set);
if (mxs_wait_mask_clr(&regs->hw_lcdif_lcdif_stat_reg, 1 << 29,
timeout))
return -ETIMEDOUT;
writel(payload, &regs->hw_lcdif_data);
return mxs_wait_mask_clr(&regs->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
timeout);
}
static void mxsfb_write_register(uint32_t reg, uint32_t data)
{
mxsfb_write_byte(reg, 0);
mxsfb_write_byte(data, 1);
}
static const struct {
uint8_t reg;
uint8_t delay;
uint16_t val;
} lcd_regs[] = {
{ 0xe5, 0 , 0x78f0 },
{ 0xe3, 0 , 0x3008 },
{ 0xe7, 0 , 0x0012 },
{ 0xef, 0 , 0x1231 },
{ 0x00, 0 , 0x0001 },
{ 0x01, 0 , 0x0100 },
{ 0x02, 0 , 0x0700 },
{ 0x03, 0 , 0x1030 },
{ 0x04, 0 , 0x0000 },
{ 0x08, 0 , 0x0207 },
{ 0x09, 0 , 0x0000 },
{ 0x0a, 0 , 0x0000 },
{ 0x0c, 0 , 0x0000 },
{ 0x0d, 0 , 0x0000 },
{ 0x0f, 0 , 0x0000 },
{ 0x10, 0 , 0x0000 },
{ 0x11, 0 , 0x0007 },
{ 0x12, 0 , 0x0000 },
{ 0x13, 20 , 0x0000 },
/* Wait 20 mS here. */
{ 0x10, 0 , 0x1290 },
{ 0x11, 50 , 0x0007 },
/* Wait 50 mS here. */
{ 0x12, 50 , 0x0019 },
/* Wait 50 mS here. */
{ 0x13, 0 , 0x1700 },
{ 0x29, 50 , 0x0014 },
/* Wait 50 mS here. */
{ 0x20, 0 , 0x0000 },
{ 0x21, 0 , 0x0000 },
{ 0x30, 0 , 0x0504 },
{ 0x31, 0 , 0x0007 },
{ 0x32, 0 , 0x0006 },
{ 0x35, 0 , 0x0106 },
{ 0x36, 0 , 0x0202 },
{ 0x37, 0 , 0x0504 },
{ 0x38, 0 , 0x0500 },
{ 0x39, 0 , 0x0706 },
{ 0x3c, 0 , 0x0204 },
{ 0x3d, 0 , 0x0202 },
{ 0x50, 0 , 0x0000 },
{ 0x51, 0 , 0x00ef },
{ 0x52, 0 , 0x0000 },
{ 0x53, 0 , 0x013f },
{ 0x60, 0 , 0xa700 },
{ 0x61, 0 , 0x0001 },
{ 0x6a, 0 , 0x0000 },
{ 0x2b, 50 , 0x000d },
/* Wait 50 mS here. */
{ 0x90, 0 , 0x0011 },
{ 0x92, 0 , 0x0600 },
{ 0x93, 0 , 0x0003 },
{ 0x95, 0 , 0x0110 },
{ 0x97, 0 , 0x0000 },
{ 0x98, 0 , 0x0000 },
{ 0x07, 0 , 0x0173 },
};
void board_mxsfb_system_setup(void)
{
struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
uint32_t id;
int i;
/* Switch the LCDIF into System-Mode */
writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
LCDIF_CTRL_BYPASS_COUNT, &regs->hw_lcdif_ctrl_clr);
/* To program the LCD, switch to 18bit bus + 18bit data. */
clrsetbits_le32(&regs->hw_lcdif_ctrl,
LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK,
LCDIF_CTRL_WORD_LENGTH_18BIT |
LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT);
mxsfb_read_register(0, &id);
writel(id, 0x2004);
/* Restart the SmartLCD controller */
mdelay(50);
writel(1, &regs->hw_lcdif_ctrl1_set);
mdelay(50);
writel(1, &regs->hw_lcdif_ctrl1_clr);
mdelay(50);
writel(1, &regs->hw_lcdif_ctrl1_set);
mdelay(50);
/* Program the SmartLCD controller */
writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, &regs->hw_lcdif_ctrl1_set);
writel((0x02 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
(0x02 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
(0x02 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
(0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET),
&regs->hw_lcdif_timing);
/*
* ILI9325 init and configuration sequence.
*/
for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
if (lcd_regs[i].delay)
mdelay(lcd_regs[i].delay);
}
/* Turn on Framebuffer Upload Mode */
mxsfb_write_byte(0x22, 0);
writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
&regs->hw_lcdif_ctrl_set);
/* Operate the framebuffer in 16bit mode. */
clrsetbits_le32(&regs->hw_lcdif_ctrl,
LCDIF_CTRL_WORD_LENGTH_MASK | LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK,
LCDIF_CTRL_WORD_LENGTH_16BIT |
LCDIF_CTRL_LCD_DATABUS_WIDTH_18BIT);
}
#endif
int board_init(void)
{
/* Adress of boot parameters */
gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
/* Turn on PWM backlight */
gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
return 0;
}
int board_eth_init(struct bd_info *bis)
{
usb_eth_initialize(bis);
return 0;
}

139
board/sandisk/sansa_fuze_plus/spl_boot.c
View File

@ -1,139 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* SanDisk Sansa Fuze Plus setup
*
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
*/
#include <common.h>
#include <config.h>
#include <asm/io.h>
#include <asm/arch/iomux-mx23.h>
#include <asm/arch/imx-regs.h>
#include <asm/arch/sys_proto.h>
#define MUX_CONFIG_EMI (MXS_PAD_1V8 | MXS_PAD_12MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_SSP (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_PULLUP)
#define MUX_CONFIG_LCD (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL)
const iomux_cfg_t iomux_setup[] = {
/* EMI */
MX23_PAD_EMI_D00__EMI_D00 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D01__EMI_D01 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D02__EMI_D02 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D03__EMI_D03 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D04__EMI_D04 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D05__EMI_D05 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D06__EMI_D06 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D07__EMI_D07 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D08__EMI_D08 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D09__EMI_D09 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D10__EMI_D10 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D11__EMI_D11 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D12__EMI_D12 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D13__EMI_D13 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D14__EMI_D14 | MUX_CONFIG_EMI,
MX23_PAD_EMI_D15__EMI_D15 | MUX_CONFIG_EMI,
MX23_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI,
MX23_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI,
MX23_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI,
MX23_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI,
MX23_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI,
MX23_PAD_EMI_CLKN__EMI_CLKN | MUX_CONFIG_EMI,
MX23_PAD_EMI_A00__EMI_A00 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A01__EMI_A01 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A02__EMI_A02 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A03__EMI_A03 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A04__EMI_A04 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A05__EMI_A05 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A06__EMI_A06 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A07__EMI_A07 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A08__EMI_A08 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A09__EMI_A09 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A10__EMI_A10 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A11__EMI_A11 | MUX_CONFIG_EMI,
MX23_PAD_EMI_A12__EMI_A12 | MUX_CONFIG_EMI,
MX23_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI,
MX23_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI,
MX23_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI,
MX23_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI,
MX23_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI,
MX23_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI,
MX23_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI,
MX23_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI,
MX23_PAD_LCD_D00__LCD_D00 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D01__LCD_D01 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D02__LCD_D02 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D03__LCD_D03 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D04__LCD_D04 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D05__LCD_D05 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D06__LCD_D06 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D07__LCD_D07 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D08__LCD_D08 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D09__LCD_D09 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D10__LCD_D10 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D11__LCD_D11 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D12__LCD_D12 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D13__LCD_D13 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D14__LCD_D14 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D15__LCD_D15 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D16__LCD_D16 | MUX_CONFIG_LCD,
MX23_PAD_LCD_D17__LCD_D17 | MUX_CONFIG_LCD,
MX23_PAD_LCD_RESET__LCD_RESET | MUX_CONFIG_LCD,
MX23_PAD_LCD_RS__LCD_RS | MUX_CONFIG_LCD,
MX23_PAD_LCD_WR__LCD_WR | MUX_CONFIG_LCD,
MX23_PAD_LCD_CS__LCD_CS | MUX_CONFIG_LCD,
MX23_PAD_LCD_ENABLE__LCD_ENABLE | MUX_CONFIG_LCD,
MX23_PAD_LCD_VSYNC__LCD_VSYNC | MUX_CONFIG_LCD,
MX23_PAD_SSP1_CMD__SSP1_CMD | MUX_CONFIG_SSP,
MX23_PAD_SSP1_DETECT__GPIO_2_1 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_DATA0__SSP1_DATA0 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_DATA1__SSP1_DATA1 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_DATA2__SSP1_DATA2 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_DATA3__SSP1_DATA3 | MUX_CONFIG_SSP,
MX23_PAD_SSP1_SCK__SSP1_SCK | MUX_CONFIG_SSP,
MX23_PAD_GPMI_D08__GPIO_0_8 | MUX_CONFIG_SSP,
MX23_PAD_GPMI_D00__SSP2_DATA0 | MUX_CONFIG_SSP,
MX23_PAD_GPMI_D01__SSP2_DATA1 | MUX_CONFIG_SSP,
MX23_PAD_GPMI_D02__SSP2_DATA2 | MUX_CONFIG_SSP,
MX23_PAD_GPMI_D03__SSP2_DATA3 | MUX_CONFIG_SSP,
MX23_PAD_GPMI_D04__SSP2_DATA4 | MUX_CONFIG_SSP,
MX23_PAD_GPMI_D05__SSP2_DATA5 | MUX_CONFIG_SSP,
MX23_PAD_GPMI_D06__SSP2_DATA6 | MUX_CONFIG_SSP,
MX23_PAD_GPMI_D07__SSP2_DATA7 | MUX_CONFIG_SSP,
MX23_PAD_GPMI_RDY1__SSP2_CMD | MUX_CONFIG_SSP,
MX23_PAD_GPMI_WRN__SSP2_SCK |
(MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL),
MX23_PAD_PWM3__GPIO_1_29 | MUX_CONFIG_SSP,
/* PWM -- FIXME */
MX23_PAD_PWM2__GPIO_1_28 | MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_PULLUP,
};
void mxs_adjust_memory_params(uint32_t *dram_vals)
{
/* mDDR configuration values */
const uint32_t regs[] = {
0x01010001, 0x00010000, 0x01000000, 0x00000001,
0x00010101, 0x00000001, 0x00010000, 0x01000001,
0x01010000, 0x00000001, 0x07000200, 0x04070203,
0x02020002, 0x06070a02, 0x0d000201, 0x0305000d,
0x02080800, 0x19330f0a, 0x1f1f1c00, 0x020a1313,
0x03061323, 0x0000000a, 0x00080008, 0x00200020,
0x00200020, 0x00200020, 0x000003f7, 0x00000000,
0x00000000, 0x00000000, 0x00000020, 0x00000000,
0x001023cd, 0x20410010, 0x00006665, 0x00000000,
0x00000101, 0x00000001, 0x00000000, 0x00000000,
};
memcpy(dram_vals, regs, sizeof(regs));
}
void board_init_ll(const uint32_t arg, const uint32_t *resptr)
{
mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup));
}

46
configs/sansa_fuze_plus_defconfig
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@ -1,46 +0,0 @@
CONFIG_ARM=y
CONFIG_ARCH_MX23=y
CONFIG_SYS_TEXT_BASE=0x40002000
CONFIG_SPL_GPIO_SUPPORT=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=1
CONFIG_SYS_MEMTEST_START=0x40000000
CONFIG_SYS_MEMTEST_END=0x40400000
CONFIG_ENV_SIZE=0x4000
CONFIG_SPL_TEXT_BASE=0x00001000
CONFIG_TARGET_SANSA_FUZE_PLUS=y
CONFIG_SPL_SERIAL_SUPPORT=y
CONFIG_SPL=y
CONFIG_BOOTDELAY=3
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttyAMA0,115200n8 "
CONFIG_SYS_CONSOLE_IS_IN_ENV=y
# CONFIG_DISPLAY_BOARDINFO is not set
CONFIG_ARCH_MISC_INIT=y
CONFIG_BOARD_EARLY_INIT_F=y
# CONFIG_SPL_FRAMEWORK is not set
CONFIG_HUSH_PARSER=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_GPIO=y
CONFIG_CMD_MMC=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_PING=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_FAT=y
CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_VERSION_VARIABLE=y
CONFIG_NETCONSOLE=y
CONFIG_MXS_GPIO=y
CONFIG_MMC_MXS=y
CONFIG_CONS_INDEX=0
CONFIG_USB=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_GADGET=y
CONFIG_CI_UDC=y
CONFIG_USB_ETHER=y
CONFIG_USB_ETH_CDC=y
CONFIG_OF_LIBFDT=y

39
include/configs/sansa_fuze_plus.h
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@ -1,39 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013 Marek Vasut <marex@denx.de>
*/
#ifndef __CONFIGS_SANSA_FUZE_PLUS_H__
#define __CONFIGS_SANSA_FUZE_PLUS_H__
/* U-Boot Commands */
/* Memory configuration */
#define PHYS_SDRAM_1 0x40000000 /* Base address */
#define PHYS_SDRAM_1_SIZE 0x08000000 /* Max 128 MB RAM */
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
/* Environment */
/* Booting Linux */
#define CONFIG_BOOTFILE "uImage"
#define CONFIG_LOADADDR 0x42000000
#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
/* LCD */
#ifdef CONFIG_VIDEO
#define CONFIG_VIDEO_FONT_4X6
#define CONFIG_VIDEO_MXS_MODE_SYSTEM
#define CONFIG_SYS_BLACK_IN_WRITE
#define LCD_BPP LCD_COLOR16
#endif
/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_EHCI_MXS_PORT0
#define CONFIG_USB_MAX_CONTROLLER_COUNT 1
#endif
/* The rest of the configuration is shared */
#include <configs/mxs.h>
#endif /* __CONFIGS_SANSA_FUZE_PLUS_H__ */