arm: dts: introduce j784s4 dtbs from linux kernel
Introduce the basic j784s4 SoC dtbs from the linux kernel along with the new j784s4 specific pinmux definitions that we will use to generate the dtbs for the u-boot-spl and u-boot binaries. The dtbs are taken from v6.3 kernel repository. Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Hari Nagalla <hnagalla@ti.com>
This commit is contained in:
Hari Nagalla
Udit Kumar
parent
d670b22bce
commit
b4b077edc8
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
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*
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* EVM Board Schematics: https://www.ti.com/lit/zip/sprr458
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*/
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/dts-v1/;
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#include <dt-bindings/net/ti-dp83867.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "k3-j784s4.dtsi"
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/ {
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compatible = "ti,j784s4-evm", "ti,j784s4";
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model = "Texas Instruments J784S4 EVM";
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chosen {
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stdout-path = "serial2:115200n8";
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};
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aliases {
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serial2 = &main_uart8;
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mmc1 = &main_sdhci1;
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i2c0 = &main_i2c0;
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};
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memory@80000000 {
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device_type = "memory";
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/* 32G RAM */
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reg = <0x00 0x80000000 0x00 0x80000000>,
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<0x08 0x80000000 0x07 0x80000000>;
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};
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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secure_ddr: optee@9e800000 {
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reg = <0x00 0x9e800000 0x00 0x01800000>;
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no-map;
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};
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};
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evm_12v0: regulator-evm12v0 {
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/* main supply */
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compatible = "regulator-fixed";
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regulator-name = "evm_12v0";
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regulator-min-microvolt = <12000000>;
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regulator-max-microvolt = <12000000>;
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regulator-always-on;
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regulator-boot-on;
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};
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vsys_3v3: regulator-vsys3v3 {
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/* Output of LM5140 */
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compatible = "regulator-fixed";
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regulator-name = "vsys_3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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vin-supply = <&evm_12v0>;
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regulator-always-on;
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regulator-boot-on;
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};
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vsys_5v0: regulator-vsys5v0 {
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/* Output of LM5140 */
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compatible = "regulator-fixed";
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regulator-name = "vsys_5v0";
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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vin-supply = <&evm_12v0>;
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regulator-always-on;
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regulator-boot-on;
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};
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vdd_mmc1: regulator-sd {
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/* Output of TPS22918 */
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compatible = "regulator-fixed";
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regulator-name = "vdd_mmc1";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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enable-active-high;
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vin-supply = <&vsys_3v3>;
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gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
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};
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vdd_sd_dv: regulator-TLV71033 {
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/* Output of TLV71033 */
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compatible = "regulator-gpio";
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regulator-name = "tlv71033";
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pinctrl-names = "default";
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pinctrl-0 = <&vdd_sd_dv_pins_default>;
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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vin-supply = <&vsys_5v0>;
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gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>;
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states = <1800000 0x0>,
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<3300000 0x1>;
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};
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};
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&main_pmx0 {
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main_uart8_pins_default: main-uart8-pins-default {
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pinctrl-single,pins = <
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J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */
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J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */
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J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */
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J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */
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>;
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};
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main_i2c0_pins_default: main-i2c0-pins-default {
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pinctrl-single,pins = <
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J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */
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J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */
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>;
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};
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main_mmc1_pins_default: main-mmc1-pins-default {
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pinctrl-single,pins = <
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J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */
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J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */
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J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */
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J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */
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J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */
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J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */
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J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */
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J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */
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>;
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};
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vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
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pinctrl-single,pins = <
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J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */
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>;
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};
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};
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&main_uart8 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_uart8_pins_default>;
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};
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&main_i2c0 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&main_i2c0_pins_default>;
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clock-frequency = <400000>;
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exp1: gpio@20 {
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compatible = "ti,tca6416";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ",
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"PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ",
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"PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#",
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"PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3",
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"AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ";
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};
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exp2: gpio@22 {
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compatible = "ti,tca6424";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN",
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"USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0",
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"GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#",
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"ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ",
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"USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1",
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"CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ",
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"ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ",
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"USER_INPUT1", "USER_LED1", "USER_LED2";
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};
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};
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&main_sdhci1 {
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/* SD card */
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status = "okay";
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pinctrl-0 = <&main_mmc1_pins_default>;
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pinctrl-names = "default";
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disable-wp;
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vmmc-supply = <&vdd_mmc1>;
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vqmmc-supply = <&vdd_sd_dv>;
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};
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&main_gpio0 {
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status = "okay";
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};
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,311 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Device Tree Source for J784S4 SoC Family MCU/WAKEUP Domain peripherals
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*
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* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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&cbass_mcu_wakeup {
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sms: system-controller@44083000 {
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compatible = "ti,k2g-sci";
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ti,host-id = <12>;
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mbox-names = "rx", "tx";
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mboxes = <&secure_proxy_main 11>,
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<&secure_proxy_main 13>;
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reg-names = "debug_messages";
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reg = <0x00 0x44083000 0x00 0x1000>;
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k3_pds: power-controller {
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compatible = "ti,sci-pm-domain";
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#power-domain-cells = <2>;
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};
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k3_clks: clock-controller {
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compatible = "ti,k2g-sci-clk";
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#clock-cells = <2>;
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};
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k3_reset: reset-controller {
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compatible = "ti,sci-reset";
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#reset-cells = <2>;
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};
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};
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chipid@43000014 {
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compatible = "ti,am654-chipid";
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reg = <0x00 0x43000014 0x00 0x4>;
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};
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mcu_ram: sram@41c00000 {
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compatible = "mmio-sram";
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reg = <0x00 0x41c00000 0x00 0x100000>;
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ranges = <0x00 0x00 0x41c00000 0x100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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wkup_pmx0: pinctrl@4301c000 {
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compatible = "pinctrl-single";
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/* Proxy 0 addressing */
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reg = <0x00 0x4301c000 0x00 0x178>;
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#pinctrl-cells = <1>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0xffffffff>;
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};
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wkup_gpio_intr: interrupt-controller@42200000 {
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compatible = "ti,sci-intr";
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reg = <0x00 0x42200000 0x00 0x400>;
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ti,intr-trigger-type = <1>;
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interrupt-controller;
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interrupt-parent = <&gic500>;
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#interrupt-cells = <1>;
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ti,sci = <&sms>;
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ti,sci-dev-id = <177>;
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ti,interrupt-ranges = <16 928 16>;
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};
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mcu_conf: syscon@40f00000 {
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compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
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reg = <0x00 0x40f00000 0x00 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x00 0x00 0x40f00000 0x20000>;
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phy_gmii_sel: phy@4040 {
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compatible = "ti,am654-phy-gmii-sel";
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reg = <0x4040 0x4>;
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#phy-cells = <1>;
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};
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};
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wkup_uart0: serial@42300000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x42300000 0x00 0x200>;
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interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
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current-speed = <115200>;
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clocks = <&k3_clks 397 0>;
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clock-names = "fclk";
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power-domains = <&k3_pds 397 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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mcu_uart0: serial@40a00000 {
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compatible = "ti,j721e-uart", "ti,am654-uart";
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reg = <0x00 0x40a00000 0x00 0x200>;
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interrupts = <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>;
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current-speed = <115200>;
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clocks = <&k3_clks 149 0>;
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clock-names = "fclk";
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power-domains = <&k3_pds 149 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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wkup_gpio0: gpio@42110000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x00 0x42110000 0x00 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&wkup_gpio_intr>;
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interrupts = <103>, <104>, <105>, <106>, <107>, <108>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <89>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 167 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 167 0>;
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clock-names = "gpio";
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status = "disabled";
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};
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wkup_gpio1: gpio@42100000 {
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compatible = "ti,j721e-gpio", "ti,keystone-gpio";
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reg = <0x00 0x42100000 0x00 0x100>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-parent = <&wkup_gpio_intr>;
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interrupts = <112>, <113>, <114>, <115>, <116>, <117>;
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interrupt-controller;
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#interrupt-cells = <2>;
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ti,ngpio = <89>;
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ti,davinci-gpio-unbanked = <0>;
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power-domains = <&k3_pds 168 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 168 0>;
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clock-names = "gpio";
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status = "disabled";
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};
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wkup_i2c0: i2c@42120000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x00 0x42120000 0x00 0x100>;
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interrupts = <GIC_SPI 896 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 279 2>;
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clock-names = "fck";
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power-domains = <&k3_pds 279 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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mcu_i2c0: i2c@40b00000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x00 0x40b00000 0x00 0x100>;
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interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 277 2>;
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clock-names = "fck";
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power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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mcu_i2c1: i2c@40b10000 {
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compatible = "ti,j721e-i2c", "ti,omap4-i2c";
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reg = <0x00 0x40b10000 0x00 0x100>;
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interrupts = <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&k3_clks 278 2>;
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clock-names = "fck";
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power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;
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status = "disabled";
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};
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mcu_mcan0: can@40528000 {
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compatible = "bosch,m_can";
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reg = <0x00 0x40528000 0x00 0x200>,
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<0x00 0x40500000 0x00 0x8000>;
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reg-names = "m_can", "message_ram";
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power-domains = <&k3_pds 263 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 263 6>, <&k3_clks 263 1>;
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clock-names = "hclk", "cclk";
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interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
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status = "disabled";
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};
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mcu_mcan1: can@40568000 {
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compatible = "bosch,m_can";
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reg = <0x00 0x40568000 0x00 0x200>,
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<0x00 0x40540000 0x00 0x8000>;
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reg-names = "m_can", "message_ram";
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power-domains = <&k3_pds 264 TI_SCI_PD_EXCLUSIVE>;
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clocks = <&k3_clks 264 6>, <&k3_clks 264 1>;
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clock-names = "hclk", "cclk";
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interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "int0", "int1";
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bosch,mram-cfg = <0x00 128 64 64 64 64 32 32>;
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status = "disabled";
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};
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mcu_navss: bus@28380000{
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compatible = "simple-bus";
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#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>;
|
||||
dma-coherent;
|
||||
dma-ranges;
|
||||
|
||||
mcu_ringacc: ringacc@2b800000 {
|
||||
compatible = "ti,am654-navss-ringacc";
|
||||
reg = <0x00 0x2b800000 0x00 0x400000>,
|
||||
<0x00 0x2b000000 0x00 0x400000>,
|
||||
<0x00 0x28590000 0x00 0x100>,
|
||||
<0x00 0x2a500000 0x00 0x40000>;
|
||||
reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
|
||||
ti,num-rings = <286>;
|
||||
ti,sci-rm-range-gp-rings = <0x1>;
|
||||
ti,sci = <&sms>;
|
||||
ti,sci-dev-id = <328>;
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
};
|
||||
|
||||
mcu_udmap: dma-controller@285c0000 {
|
||||
compatible = "ti,j721e-navss-mcu-udmap";
|
||||
reg = <0x00 0x285c0000 0x00 0x100>,
|
||||
<0x00 0x2a800000 0x00 0x40000>,
|
||||
<0x00 0x2aa00000 0x00 0x40000>;
|
||||
reg-names = "gcfg", "rchanrt", "tchanrt";
|
||||
msi-parent = <&main_udmass_inta>;
|
||||
#dma-cells = <1>;
|
||||
|
||||
ti,sci = <&sms>;
|
||||
ti,sci-dev-id = <329>;
|
||||
ti,ringacc = <&mcu_ringacc>;
|
||||
ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
|
||||
<0x0f>; /* TX_HCHAN */
|
||||
ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
|
||||
<0x0b>; /* RX_HCHAN */
|
||||
ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
|
||||
};
|
||||
};
|
||||
|
||||
mcu_cpsw: ethernet@46000000 {
|
||||
compatible = "ti,j721e-cpsw-nuss";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
reg = <0x00 0x46000000 0x00 0x200000>;
|
||||
reg-names = "cpsw_nuss";
|
||||
ranges = <0x00 0x00 0x00 0x46000000 0x00 0x200000>;
|
||||
dma-coherent;
|
||||
clocks = <&k3_clks 63 0>;
|
||||
clock-names = "fck";
|
||||
power-domains = <&k3_pds 63 TI_SCI_PD_EXCLUSIVE>;
|
||||
|
||||
dmas = <&mcu_udmap 0xf000>,
|
||||
<&mcu_udmap 0xf001>,
|
||||
<&mcu_udmap 0xf002>,
|
||||
<&mcu_udmap 0xf003>,
|
||||
<&mcu_udmap 0xf004>,
|
||||
<&mcu_udmap 0xf005>,
|
||||
<&mcu_udmap 0xf006>,
|
||||
<&mcu_udmap 0xf007>,
|
||||
<&mcu_udmap 0x7000>;
|
||||
dma-names = "tx0", "tx1", "tx2", "tx3",
|
||||
"tx4", "tx5", "tx6", "tx7",
|
||||
"rx";
|
||||
status = "disabled";
|
||||
|
||||
ethernet-ports {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
mcu_cpsw_port1: port@1 {
|
||||
reg = <1>;
|
||||
ti,mac-only;
|
||||
label = "port1";
|
||||
ti,syscon-efuse = <&mcu_conf 0x200>;
|
||||
phys = <&phy_gmii_sel 1>;
|
||||
};
|
||||
};
|
||||
|
||||
davinci_mdio: mdio@f00 {
|
||||
compatible = "ti,cpsw-mdio","ti,davinci_mdio";
|
||||
reg = <0x00 0xf00 0x00 0x100>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
clocks = <&k3_clks 63 0>;
|
||||
clock-names = "fck";
|
||||
bus_freq = <1000000>;
|
||||
};
|
||||
|
||||
cpts@3d000 {
|
||||
compatible = "ti,am65-cpts";
|
||||
reg = <0x00 0x3d000 0x00 0x400>;
|
||||
clocks = <&k3_clks 63 3>;
|
||||
clock-names = "cpts";
|
||||
assigned-clocks = <&k3_clks 63 3>; /* CPTS_RFT_CLK */
|
||||
assigned-clock-parents = <&k3_clks 63 5>; /* MAIN_0_HSDIV6_CLK */
|
||||
interrupts-extended = <&gic500 GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "cpts";
|
||||
ti,cpts-ext-ts-inputs = <4>;
|
||||
ti,cpts-periodic-outputs = <2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
@ -0,0 +1,287 @@
|
|||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Device Tree Source for J784S4 SoC Family
|
||||
*
|
||||
* TRM (SPRUJ43 JULY 2022) : http://www.ti.com/lit/zip/spruj52
|
||||
*
|
||||
* Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
|
||||
*
|
||||
*/
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/pinctrl/k3.h>
|
||||
#include <dt-bindings/soc/ti,sci_pm_domain.h>
|
||||
|
||||
/ {
|
||||
model = "Texas Instruments K3 J784S4 SoC";
|
||||
compatible = "ti,j784s4";
|
||||
interrupt-parent = <&gic500>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
cpu-map {
|
||||
cluster0: cluster0 {
|
||||
core0 {
|
||||
cpu = <&cpu0>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu1>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&cpu2>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&cpu3>;
|
||||
};
|
||||
};
|
||||
|
||||
cluster1: cluster1 {
|
||||
core0 {
|
||||
cpu = <&cpu4>;
|
||||
};
|
||||
|
||||
core1 {
|
||||
cpu = <&cpu5>;
|
||||
};
|
||||
|
||||
core2 {
|
||||
cpu = <&cpu6>;
|
||||
};
|
||||
|
||||
core3 {
|
||||
cpu = <&cpu7>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
cpu0: cpu@0 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x000>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu1: cpu@1 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x001>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu2: cpu@2 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x002>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu3: cpu@3 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x003>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_0>;
|
||||
};
|
||||
|
||||
cpu4: cpu@100 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x100>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu5: cpu@101 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x101>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu6: cpu@102 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x102>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
|
||||
cpu7: cpu@103 {
|
||||
compatible = "arm,cortex-a72";
|
||||
reg = <0x103>;
|
||||
device_type = "cpu";
|
||||
enable-method = "psci";
|
||||
i-cache-size = <0xc000>;
|
||||
i-cache-line-size = <64>;
|
||||
i-cache-sets = <256>;
|
||||
d-cache-size = <0x8000>;
|
||||
d-cache-line-size = <64>;
|
||||
d-cache-sets = <256>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
};
|
||||
|
||||
L2_0: l2-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
next-level-cache = <&msmc_l3>;
|
||||
};
|
||||
|
||||
L2_1: l2-cache1 {
|
||||
compatible = "cache";
|
||||
cache-level = <2>;
|
||||
cache-unified;
|
||||
cache-size = <0x200000>;
|
||||
cache-line-size = <64>;
|
||||
cache-sets = <1024>;
|
||||
next-level-cache = <&msmc_l3>;
|
||||
};
|
||||
|
||||
msmc_l3: l3-cache0 {
|
||||
compatible = "cache";
|
||||
cache-level = <3>;
|
||||
cache-unified;
|
||||
};
|
||||
|
||||
firmware {
|
||||
optee {
|
||||
compatible = "linaro,optee-tz";
|
||||
method = "smc";
|
||||
};
|
||||
|
||||
psci: psci {
|
||||
compatible = "arm,psci-1.0";
|
||||
method = "smc";
|
||||
};
|
||||
};
|
||||
|
||||
a72_timer0: timer-cl0-cpu0 {
|
||||
compatible = "arm,armv8-timer";
|
||||
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */
|
||||
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */
|
||||
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */
|
||||
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */
|
||||
};
|
||||
|
||||
pmu: pmu {
|
||||
compatible = "arm,cortex-a72-pmu";
|
||||
/* Recommendation from GIC500 TRM Table A.3 */
|
||||
interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
cbass_main: bus@100000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
|
||||
<0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
|
||||
<0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
|
||||
<0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
|
||||
<0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
|
||||
<0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */
|
||||
<0x00 0x64800000 0x00 0x64800000 0x00 0x0070c000>, /* C71_1 */
|
||||
<0x00 0x65800000 0x00 0x65800000 0x00 0x0070c000>, /* C71_2 */
|
||||
<0x00 0x66800000 0x00 0x66800000 0x00 0x0070c000>, /* C71_3 */
|
||||
<0x00 0x67800000 0x00 0x67800000 0x00 0x0070c000>, /* C71_4 */
|
||||
<0x00 0x6f000000 0x00 0x6f000000 0x00 0x00310000>, /* A72 PERIPHBASE */
|
||||
<0x00 0x70000000 0x00 0x70000000 0x00 0x00400000>, /* MSMC RAM */
|
||||
<0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>, /* MAIN NAVSS */
|
||||
<0x41 0x00000000 0x41 0x00000000 0x01 0x00000000>, /* PCIe1 DAT1 */
|
||||
<0x4e 0x20000000 0x4e 0x20000000 0x00 0x00080000>, /* GPU */
|
||||
|
||||
/* MCUSS_WKUP Range */
|
||||
<0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>,
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>,
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>,
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>,
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>,
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>,
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>,
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>,
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>,
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>,
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>;
|
||||
|
||||
cbass_mcu_wakeup: bus@28380000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS*/
|
||||
<0x00 0x40200000 0x00 0x40200000 0x00 0x00998400>, /* First peripheral window */
|
||||
<0x00 0x40f00000 0x00 0x40f00000 0x00 0x00020000>, /* CTRL_MMR0 */
|
||||
<0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
|
||||
<0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
|
||||
<0x00 0x41c00000 0x00 0x41c00000 0x00 0x00100000>, /* MCU SRAM */
|
||||
<0x00 0x42040000 0x00 0x42040000 0x00 0x03ac2400>, /* WKUP peripheral window */
|
||||
<0x00 0x45100000 0x00 0x45100000 0x00 0x00c24000>, /* MMRs, remaining NAVSS */
|
||||
<0x00 0x46000000 0x00 0x46000000 0x00 0x00200000>, /* CPSW */
|
||||
<0x00 0x47000000 0x00 0x47000000 0x00 0x00068400>, /* OSPI register space */
|
||||
<0x00 0x50000000 0x00 0x50000000 0x00 0x10000000>, /* FSS OSPI0/1 data region 0 */
|
||||
<0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS OSPI0 data region 3 */
|
||||
<0x07 0x00000000 0x07 0x00000000 0x01 0x00000000>; /* FSS OSPI1 data region 3*/
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/* Now include peripherals from each bus segment */
|
||||
#include "k3-j784s4-main.dtsi"
|
||||
#include "k3-j784s4-mcu-wakeup.dtsi"
|
||||
|
|
@ -47,4 +47,7 @@
|
|||
#define AM62AX_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define AM62AX_MCU_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#define J784S4_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
#define J784S4_WKUP_IOPAD(pa, val, muxmode) (((pa) & 0x1fff)) ((val) | (muxmode))
|
||||
|
||||
#endif
|
||||
|
|
|
|||
Loading…
Reference in New Issue