From b5c9636a96d4a26cc7584261dd8c8642ff23a7f9 Mon Sep 17 00:00:00 2001 From: Ye Li Date: Wed, 30 Jan 2019 21:21:35 -0800 Subject: [PATCH] MLK-20886-1 misc: MU: Add MU driver to communicate with M4 Add a common iMX MU driver in misc uclass to communicate with M4. The MU message format is defined to use 4 words as below, the driver will use all 4 TR/RR in MU to pass one message |WORD 0 | WORD 1 | WORD 2 | WORD 3 | |SEQ | TYPE | PAYLOAD ADDRESS | PAYLOAD LENGTH | - SEQ: A sequence id starts from 0 and increases for each request message - TYPE: 0x1: Request. Message sent from AP will set to this value. 0x2: Response. Message responded from M4 set to this value. 0x3: MU A side is ready. 0x4: MU B side is ready. - PAYLOAD ADDRESS: A pointer to the memory address where the uplayer message is stored - PAYLOAD LENGTH: The uplayer message length Signed-off-by: Ye Li (cherry picked from commit aba0e51cc397e1d98be950f9c15619de06ebf782) --- drivers/misc/Kconfig | 7 ++ drivers/misc/Makefile | 1 + drivers/misc/imx_m4_mu.c | 241 +++++++++++++++++++++++++++++++++++++++ include/imx_m4_mu.h | 26 +++++ 4 files changed, 275 insertions(+) create mode 100644 drivers/misc/imx_m4_mu.c create mode 100644 include/imx_m4_mu.h diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index d774569cbc..0b49d964bb 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -119,6 +119,13 @@ config MXC_OCOTP Programmable memory pages that are stored on the some Freescale i.MX processors. +config IMX_M4_MU + bool "Enable i.MX MU Driver to communicate with Cortex M4" + depends on MISC + help + If you say Y here to enable Message Unit driver to work with + Cortex M4 core on AMP Freescale i.MX processors. + config NUVOTON_NCT6102D bool "Enable Nuvoton NCT6102D Super I/O driver" help diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index e8d598cd47..f56aaa2d29 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_CROS_EC_LPC) += cros_ec_lpc.o obj-$(CONFIG_CROS_EC_I2C) += cros_ec_i2c.o obj-$(CONFIG_CROS_EC_SANDBOX) += cros_ec_sandbox.o obj-$(CONFIG_CROS_EC_SPI) += cros_ec_spi.o +obj-$(CONFIG_IMX_M4_MU) += imx_m4_mu.o endif obj-$(CONFIG_FSL_IIM) += fsl_iim.o obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o diff --git a/drivers/misc/imx_m4_mu.c b/drivers/misc/imx_m4_mu.c new file mode 100644 index 0000000000..237ab33425 --- /dev/null +++ b/drivers/misc/imx_m4_mu.c @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +DECLARE_GLOBAL_DATA_PTR; + +struct mu_type { + u32 tr[4]; + u32 rr[4]; + u32 sr; + u32 cr; +}; + +struct imx_m4_mu { + struct mu_type *base; +}; + +#define MU_CR_GIE_MASK 0xF0000000u +#define MU_CR_RIE_MASK 0xF000000u +#define MU_CR_GIR_MASK 0xF0000u +#define MU_CR_TIE_MASK 0xF00000u +#define MU_CR_F_MASK 0x7u +#define MU_SR_TE0_MASK BIT(23) +#define MU_SR_RF0_MASK BIT(27) +#define MU_TR_COUNT 4 +#define MU_RR_COUNT 4 + +static inline void mu_hal_init(struct mu_type *base) +{ + /* Clear GIEn, RIEn, TIEn, GIRn and ABFn. */ + clrbits_le32(&base->cr, MU_CR_GIE_MASK | MU_CR_RIE_MASK | + MU_CR_TIE_MASK | MU_CR_GIR_MASK | MU_CR_F_MASK); +} + +static int mu_hal_sendmsg(struct mu_type *base, u32 reg_index, u32 msg) +{ + u32 mask = MU_SR_TE0_MASK >> reg_index; + u32 val; + int ret; + + assert(reg_index < MU_TR_COUNT); + + debug("sendmsg sr 0x%x\n", readl(&base->sr)); + + /* Wait TX register to be empty. */ + ret = readl_poll_timeout(&base->sr, val, val & mask, 10000); + if (ret < 0) { + debug("%s timeout\n", __func__); + return -ETIMEDOUT; + } + + debug("tr[%d] 0x%x\n",reg_index, msg); + + writel(msg, &base->tr[reg_index]); + + return 0; +} + +static int mu_hal_receivemsg(struct mu_type *base, u32 reg_index, u32 *msg) +{ + u32 mask = MU_SR_RF0_MASK >> reg_index; + u32 val; + int ret; + + assert(reg_index < MU_TR_COUNT); + + debug("receivemsg sr 0x%x\n", readl(&base->sr)); + + /* Wait RX register to be full. */ + ret = readl_poll_timeout(&base->sr, val, val & mask, 10000); + if (ret < 0) { + debug("%s timeout\n", __func__); + return -ETIMEDOUT; + } + + *msg = readl(&base->rr[reg_index]); + + debug("rr[%d] 0x%x\n",reg_index, *msg); + + return 0; +} + +static int mu_hal_poll_receive(struct mu_type *base, ulong rx_timeout) +{ + u32 mask = MU_SR_RF0_MASK; + u32 val; + int ret; + + debug("receivemsg sr 0x%x\n", readl(&base->sr)); + + /* Wait RX register to be full. */ + ret = readl_poll_timeout(&base->sr, val, val & mask, rx_timeout); + if (ret < 0) { + debug("%s timeout\n", __func__); + return -ETIMEDOUT; + } + + return 0; +} + +static int imx_m4_mu_read(struct mu_type *base, void *data) +{ + union imx_m4_msg *msg = (union imx_m4_msg *)data; + int ret; + u8 count = 0; + + if (!msg) + return -EINVAL; + + /* Read 4 words */ + while (count < 4) { + ret = mu_hal_receivemsg(base, count % MU_RR_COUNT, + &msg->data[count]); + if (ret) + return ret; + count++; + } + + return 0; +} + +static int imx_m4_mu_write(struct mu_type *base, void *data) +{ + union imx_m4_msg *msg = (union imx_m4_msg *)data; + int ret; + u8 count = 0; + + if (!msg) + return -EINVAL; + + /* Write 4 words */ + while (count < 4) { + ret = mu_hal_sendmsg(base, count % MU_TR_COUNT, + msg->data[count]); + if (ret) + return ret; + count++; + } + + return 0; +} + +/* + * Note the function prototype use msgid as the 2nd parameter, here + * we take it as no_resp. + */ +static int imx_m4_mu_call(struct udevice *dev, int resp_timeout, void *tx_msg, + int tx_size, void *rx_msg, int rx_size) +{ + struct imx_m4_mu *priv = dev_get_priv(dev); + int ret; + + if (resp_timeout < 0) + return -EINVAL; + + if (tx_msg) { + ret = imx_m4_mu_write(priv->base, tx_msg); + if (ret) + return ret; + } + + if (rx_msg) { + if (resp_timeout) { + ret = mu_hal_poll_receive(priv->base, resp_timeout); + if (ret) + return ret; + } + + ret = imx_m4_mu_read(priv->base, rx_msg); + if (ret) + return ret; + } + + return 0; +} + +static int imx_m4_mu_probe(struct udevice *dev) +{ + struct imx_m4_mu *priv = dev_get_priv(dev); + fdt_addr_t addr; + + debug("%s(dev=%p) (priv=%p)\n", __func__, dev, priv); + + addr = devfdt_get_addr(dev); + if (addr == FDT_ADDR_T_NONE) + return -EINVAL; + + priv->base = (struct mu_type *)addr; + + debug("mu base 0x%lx\n", (ulong)priv->base); + + /* U-Boot not enable interrupts, so need to enable RX interrupts */ + mu_hal_init(priv->base); + + return 0; +} + +static int imx_m4_mu_remove(struct udevice *dev) +{ + return 0; +} + +static int imx_m4_mu_bind(struct udevice *dev) +{ + debug("%s(dev=%p)\n", __func__, dev); + + return 0; +} + +static struct misc_ops imx_m4_mu_ops = { + .call = imx_m4_mu_call, +}; + +static const struct udevice_id imx_m4_mu_ids[] = { + { .compatible = "fsl,imx-m4-mu" }, + { } +}; + +U_BOOT_DRIVER(imx_m4_mu) = { + .name = "imx_m4_mu", + .id = UCLASS_MISC, + .of_match = imx_m4_mu_ids, + .probe = imx_m4_mu_probe, + .bind = imx_m4_mu_bind, + .remove = imx_m4_mu_remove, + .ops = &imx_m4_mu_ops, + .priv_auto_alloc_size = sizeof(struct imx_m4_mu), +}; diff --git a/include/imx_m4_mu.h b/include/imx_m4_mu.h new file mode 100644 index 0000000000..b53e9e8b23 --- /dev/null +++ b/include/imx_m4_mu.h @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2019 NXP + * + */ + +#ifndef __IMX_M4_MU_H__ +#define __IMX_M4_MU_H__ + +enum imx_m4_msg_type { + MU_MSG_REQ = 0x1, /* request message sent from A side */ + MU_MSG_RESP = 0x2, /* response message from B side for request */ + MU_MSG_READY_A = 0x3, /* A side notifies ready */ + MU_MSG_READY_B = 0x4, /* B side notifies ready */ +}; + +union imx_m4_msg { + struct { + u32 seq; + u32 type; + u32 buffer; + u32 size; + } format; + u32 data[4]; +}; +#endif