From d584c68ce0f5bf2f430ccfb2ba00bd506206fb91 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 5 Jan 2016 17:02:52 -0200 Subject: [PATCH 1/8] phy: atheros: Use ar8035_config for AR8031 Commit 08ad9b068afb88 (" ar8031: modify the config func of ar8031 to ar8021_config") selected 'ar8021_config' as the configuration function for AR8031. The correct would be to use 'ar8035_config' instead as AR8031/AR8035 have the same programming model and even share the same phy driver in the linux kernel: drivers/net/phy/at803x.c. Tested on a mx6qsabresd and wandboard, which now can work without any PHY setup code in the board files. Signed-off-by: Fabio Estevam Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index d509e30d35..ba57b1a4b9 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -51,7 +51,7 @@ static struct phy_driver AR8031_driver = { .uid = 0x4dd074, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = ar8021_config, + .config = ar8035_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; From a307760ab48b428f4c2ac8b5676b29c56eee9f82 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 5 Jan 2016 17:02:53 -0200 Subject: [PATCH 2/8] mx6sabresd: Simplify the Ethernet PHY configuration As per the AR8031 datasheet: "For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied." So do as suggested and also add a 100us delay after deasserting the reset line to guarantee that the PHY ID can be read correctly and the Atheros 8031 PHY driver can be loaded automatically. This results in a simpler code. Signed-off-by: Fabio Estevam Acked-by: Joe Hershberger --- board/freescale/mx6sabresd/mx6sabresd.c | 36 ++----------------------- 1 file changed, 2 insertions(+), 34 deletions(-) diff --git a/board/freescale/mx6sabresd/mx6sabresd.c b/board/freescale/mx6sabresd/mx6sabresd.c index 581c9d5560..d20953d2ca 100644 --- a/board/freescale/mx6sabresd/mx6sabresd.c +++ b/board/freescale/mx6sabresd/mx6sabresd.c @@ -94,8 +94,9 @@ static void setup_iomux_enet(void) /* Reset AR8031 PHY */ gpio_direction_output(IMX_GPIO_NR(1, 25) , 0); - udelay(500); + mdelay(10); gpio_set_value(IMX_GPIO_NR(1, 25), 1); + udelay(100); } static iomux_v3_cfg_t const usdhc2_pads[] = { @@ -340,39 +341,6 @@ int board_mmc_init(bd_t *bis) } #endif -int mx6_rgmii_rework(struct phy_device *phydev) -{ - unsigned short val; - - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - mx6_rgmii_rework(phydev); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - #if defined(CONFIG_VIDEO_IPUV3) static void disable_lvds(struct display_info_t const *dev) { From 59a6ca54f5db0f3d99ca3bc581ccadc6019e5034 Mon Sep 17 00:00:00 2001 From: Fabio Estevam Date: Tue, 5 Jan 2016 17:02:54 -0200 Subject: [PATCH 3/8] wandboard: Simplify the Ethernet PHY configuration As per the AR8031 datasheet: "For a reliable power on reset, suggest to keep asserting the reset low long enough (10ms) to ensure the clock is stable and clock-to-reset 1ms requirement is satisfied." So do as suggested and also add a 100us delay after deasserting the reset line to guarantee that the PHY ID can be read correctly and the Atheros 8031 PHY driver can be loaded automatically. This results in a simpler code. Signed-off-by: Fabio Estevam Acked-by: Joe Hershberger --- board/wandboard/wandboard.c | 36 ++---------------------------------- 1 file changed, 2 insertions(+), 34 deletions(-) diff --git a/board/wandboard/wandboard.c b/board/wandboard/wandboard.c index 0af63d291f..ac001edf3a 100644 --- a/board/wandboard/wandboard.c +++ b/board/wandboard/wandboard.c @@ -121,8 +121,9 @@ static void setup_iomux_enet(void) /* Reset AR8031 PHY */ gpio_direction_output(ETH_PHY_RESET, 0); - udelay(500); + mdelay(10); gpio_set_value(ETH_PHY_RESET, 1); + udelay(100); } static struct fsl_esdhc_cfg usdhc_cfg[2] = { @@ -187,39 +188,6 @@ int board_mmc_init(bd_t *bis) return 0; } -static int mx6_rgmii_rework(struct phy_device *phydev) -{ - unsigned short val; - - /* To enable AR8031 ouput a 125MHz clk from CLK_25M */ - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - - val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - val &= 0xffe3; - val |= 0x18; - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); - - /* introduce tx clock delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); - val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - val |= 0x0100; - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); - - return 0; -} - -int board_phy_config(struct phy_device *phydev) -{ - mx6_rgmii_rework(phydev); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - #if defined(CONFIG_VIDEO_IPUV3) struct i2c_pads_info mx6q_i2c2_pad_info = { .scl = { From 7ea191aa10c43b5497d171ab6f48e633e6779468 Mon Sep 17 00:00:00 2001 From: "Ye.Li" Date: Mon, 4 Jan 2016 15:26:30 +0800 Subject: [PATCH 4/8] pfuze: Fix unsigned variable for less-than-zero comparison According to the Coverity result, a unsigned int variable is used fo less- than-zero comparison, the result is never true. Need to fix the variable type to signed int. Signed-off-by: Ye.Li Signed-off-by: Peng Fan Cc: Przemyslaw Marczak Cc: Stefano Babic Reviewed-by: Stefano Babic --- board/freescale/common/pfuze.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/board/freescale/common/pfuze.c b/board/freescale/common/pfuze.c index 783c46d882..69afa83562 100644 --- a/board/freescale/common/pfuze.c +++ b/board/freescale/common/pfuze.c @@ -13,7 +13,8 @@ int pfuze_mode_init(struct pmic *p, u32 mode) { unsigned char offset, i, switch_num; - u32 id, ret; + u32 id; + int ret; pmic_reg_read(p, PFUZE100_DEVICEID, &id); id = id & 0xf; From ce2190f52523f36e42b702a5b59eb202aae565b2 Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 4 Jan 2016 12:19:14 +0800 Subject: [PATCH 5/8] imx: mx6ul: disable VIDEO for SPL With DEBUG macro enabled, SPL build failure: " arch/arm/cpu/armv7/built-in.o: In function `reset_misc': ~/uboot/arch/arm/cpu/armv7/mx6/soc.c:406: undefined reference to `lcdif_power_down' scripts/Makefile.spl:244: recipe for target 'spl/u-boot-spl' failed " Wrap VIDEO settings with ifndef CONFIG_SPL_BUILD Signed-off-by: Peng Fan Cc: Stefano Babic Reviewed-by: Stefano Babic --- include/configs/mx6ul_14x14_evk.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index 2712b27fd1..c946176416 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -241,6 +241,7 @@ #define CONFIG_IMX_THERMAL +#ifndef CONFIG_SPL_BUILD #define CONFIG_VIDEO #ifdef CONFIG_VIDEO #define CONFIG_CFB_CONSOLE @@ -257,5 +258,6 @@ #define CONFIG_VIDEO_BMP_LOGO #define MXS_LCDIF_BASE MX6UL_LCDIF1_BASE_ADDR #endif +#endif #endif From fcbe8c56743a1f8ec397a71d5a932faee920bc8a Mon Sep 17 00:00:00 2001 From: Peng Fan Date: Mon, 4 Jan 2016 21:12:22 +0800 Subject: [PATCH 6/8] imx: mx7: fix the temperature checking for Rev1.1 To TO1.0, we can not rely on finish bit to read temperature. But to TO1.1, the issue was fixed by IC, we can rely on finish bit for temperature reading for TO1.1. Signed-off-by: Peng Fan Cc: Stefano Babic Cc: Tim Harvey Cc: Fabio Estevam Cc: Adrian Alonso --- drivers/thermal/imx_thermal.c | 27 +++++++++++++++++---------- 1 file changed, 17 insertions(+), 10 deletions(-) diff --git a/drivers/thermal/imx_thermal.c b/drivers/thermal/imx_thermal.c index 09a3c52680..0509094555 100644 --- a/drivers/thermal/imx_thermal.c +++ b/drivers/thermal/imx_thermal.c @@ -130,7 +130,7 @@ static int read_cpu_temperature(struct udevice *dev) #elif defined(CONFIG_MX7) static int read_cpu_temperature(struct udevice *dev) { - unsigned int reg, tmp, start; + unsigned int reg, tmp; unsigned int raw_25c, te1; int temperature; unsigned int *priv = dev_get_priv(dev); @@ -169,18 +169,25 @@ static int read_cpu_temperature(struct udevice *dev) writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); writel(TEMPMON_HW_ANADIG_TEMPSENSE1_MEASURE_TEMP_MASK, &ccm_anatop->tempsense1_set); - start = get_timer(0); - /* Wait max 100ms */ - do { - /* - * Since we can not rely on finish bit, use 1ms delay to get - * temperature. From RM, 17us is enough to get data, but - * to gurantee to get the data, delay 100ms here. - */ + if (soc_rev() >= CHIP_REV_1_1) { + while ((readl(&ccm_anatop->tempsense1) & + TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK) == 0) + ; reg = readl(&ccm_anatop->tempsense1); tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; - } while (get_timer(0) < (start + 100)); + } else { + /* + * Since we can not rely on finish bit, use 10ms + * delay to get temperature. From RM, 17us is + * enough to get data, but to gurantee to get + * the data, delay 10ms here. + */ + udelay(10000); + reg = readl(&ccm_anatop->tempsense1); + tmp = (reg & TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_MASK) + >> TEMPMON_HW_ANADIG_TEMPSENSE1_TEMP_VALUE_SHIFT; + } writel(TEMPMON_HW_ANADIG_TEMPSENSE1_FINISHED_MASK, &ccm_anatop->tempsense1_clr); From 88f91d1375aaf4d21d77a2f2daa351dea9132a58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?M=C3=A5ns=20Rullg=C3=A5rd?= Date: Tue, 15 Dec 2015 22:27:57 +0000 Subject: [PATCH 7/8] gpio: mxs: add name_to_gpio() function Override the default name_to_gpio() function with one that accepts strings of the form bank:pin. If a colon is present in the provided name, it behaves like the default version. This lets the "gpio" command work with sane names rather than requiring the user to enter the bank/pin composite in decimal. Signed-off-by: Mans Rullgard Reviewed-by: Stefano Babic --- drivers/gpio/mxs_gpio.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/drivers/gpio/mxs_gpio.c b/drivers/gpio/mxs_gpio.c index da0199b168..b54a10b493 100644 --- a/drivers/gpio/mxs_gpio.c +++ b/drivers/gpio/mxs_gpio.c @@ -114,3 +114,18 @@ int gpio_free(unsigned gpio) { return 0; } + +int name_to_gpio(const char *name) +{ + unsigned bank, pin; + char *end; + + bank = simple_strtoul(name, &end, 10); + + if (!*end || *end != ':') + return bank; + + pin = simple_strtoul(end + 1, NULL, 10); + + return (bank << MXS_PAD_BANK_SHIFT) | (pin << MXS_PAD_PIN_SHIFT); +} From 587c3f8ebe356b558f1876414885c1b4a31294ab Mon Sep 17 00:00:00 2001 From: Andrey Skvortsov Date: Sun, 20 Dec 2015 21:09:58 +0300 Subject: [PATCH 8/8] imx_watchdog: always set minimal timeout in reset_cpu The problem is that timeout bits in WCR register were leaved unchanged. So previously set timeout value was applied and therefore 'reset' command takes any value up to two minutes, depending on previous watchdog settings, instead of minimal 0.5 seconds. Signed-off-by: Andrey Skvortsov --- drivers/watchdog/imx_watchdog.c | 2 +- include/fsl_wdog.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 0d775956bf..f9f817596f 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -43,7 +43,7 @@ void reset_cpu(ulong addr) { struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR; - clrsetbits_le16(&wdog->wcr, 0, WCR_WDE); + clrsetbits_le16(&wdog->wcr, WCR_WT_MSK, WCR_WDE); writew(0x5555, &wdog->wsr); writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ diff --git a/include/fsl_wdog.h b/include/fsl_wdog.h index d15a70cedb..f698d4d64e 100644 --- a/include/fsl_wdog.h +++ b/include/fsl_wdog.h @@ -16,3 +16,4 @@ struct watchdog_regs { #define WCR_WDT 0x08 #define WCR_SRS 0x10 #define SET_WCR_WT(x) (x << 8) +#define WCR_WT_MSK SET_WCR_WT(0xFF)