x86: Add low-power subsystem (lpss) support
This subsystem is present on various Intel SoCs. Add very basic support for taking an lpss device out of reset. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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				|  | @ -19,6 +19,7 @@ endif | |||
| obj-y += cpu.o | ||||
| obj-y += fast_spi.o | ||||
| obj-y += lpc.o | ||||
| obj-y += lpss.o | ||||
| ifndef CONFIG_TARGET_EFI_APP | ||||
| obj-$(CONFIG_$(SPL_TPL_)X86_32BIT_INIT) += microcode.o | ||||
| ifndef CONFIG_$(SPL_)X86_64 | ||||
|  |  | |||
|  | @ -0,0 +1,44 @@ | |||
| // SPDX-License-Identifier: GPL-2.0
 | ||||
| /*
 | ||||
|  * Special driver to handle of-platdata | ||||
|  * | ||||
|  * Copyright 2019 Google LLC | ||||
|  * | ||||
|  * Some code from coreboot lpss.c | ||||
|  */ | ||||
| 
 | ||||
| #include <common.h> | ||||
| #include <dm.h> | ||||
| #include <pci.h> | ||||
| #include <asm/io.h> | ||||
| #include <asm/lpss.h> | ||||
| 
 | ||||
| enum { | ||||
| 	LPSS_RESET_CTL_REG	= 0x204, | ||||
| 
 | ||||
| 	/*
 | ||||
| 	 * Bit 1:0 controls LPSS controller reset. | ||||
| 	 * | ||||
| 	 * 00 ->LPSS Host Controller is in reset (Reset Asserted) | ||||
| 	 * 01/10 ->Reserved | ||||
| 	 * 11 ->LPSS Host Controller is NOT at reset (Reset Released) | ||||
| 	 */ | ||||
| 	LPSS_CNT_RST_RELEASE	= 3, | ||||
| 
 | ||||
| 	/* Power management control and status register */ | ||||
| 	PME_CTRL_STATUS		= 0x84, | ||||
| 
 | ||||
| 	/* Bit 1:0 Powerstate, controls D0 and D3 state */ | ||||
| 	POWER_STATE_MASK	= 3, | ||||
| }; | ||||
| 
 | ||||
| /* Take controller out of reset */ | ||||
| void lpss_reset_release(void *regs) | ||||
| { | ||||
| 	writel(LPSS_CNT_RST_RELEASE, regs + LPSS_RESET_CTL_REG); | ||||
| } | ||||
| 
 | ||||
| void lpss_set_power_state(struct udevice *dev, enum lpss_pwr_state state) | ||||
| { | ||||
| 	dm_pci_clrset_config8(dev, PME_CTRL_STATUS, POWER_STATE_MASK, state); | ||||
| } | ||||
|  | @ -0,0 +1,36 @@ | |||
| /* SPDX-License-Identifier: GPL-2.0 */ | ||||
| /*
 | ||||
|  * Copyright 2019 Google LLC | ||||
|  */ | ||||
| 
 | ||||
| #ifndef __ASM_LPSS_H | ||||
| #define __ASM_LPSS_H | ||||
| 
 | ||||
| struct udevice; | ||||
| 
 | ||||
| /* D0 and D3 enable config */ | ||||
| enum lpss_pwr_state { | ||||
| 	STATE_D0 = 0, | ||||
| 	STATE_D3 = 3 | ||||
| }; | ||||
| 
 | ||||
| /**
 | ||||
|  * lpss_reset_release() - Release device from reset | ||||
|  * | ||||
|  * This is used for devices which have LPSS support. | ||||
|  * | ||||
|  * @regs: Pointer to device registers | ||||
|  */ | ||||
| void lpss_reset_release(void *regs); | ||||
| 
 | ||||
| /**
 | ||||
|  * lpss_set_power_state() - Change power state of a device | ||||
|  * | ||||
|  * This is used for devices which have LPSS support. | ||||
|  * | ||||
|  * @dev: Device to update | ||||
|  * @state: New power state to set | ||||
|  */ | ||||
| void lpss_set_power_state(struct udevice *dev, enum lpss_pwr_state state); | ||||
| 
 | ||||
| #endif | ||||
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