hancock: add sja1105 eth switch driver
This commit is contained in:
Rene Straub
parent
957b2967e0
commit
b91bd02285
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/*
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* sja1105.c
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*
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* Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
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*
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*SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <errno.h>
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#include <spi.h>
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#include "sja1105.h"
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#define SJA_OPCODE_WRITE 0x80
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#define SJA_OPCODE_READ 0x00
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/*#define SJA_READ_CNT(x) (((x) &0x3F) << 1)*/
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/*
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* Function: sja1105_write_reg
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* --------------------
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* perform the expected 64 bits access to write to a register into the switch
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*
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* spi_slave: spi instance created from sja1105_setup_spi
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* address : expect to be max 21 bits (range 0x0 to 0x100BC3h)
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* data : expect to be max 32 bits
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*
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* Returns: 0 on success, not 0 on failure
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*/
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int sja1105_write_reg(struct spi_slave *spislave, uint32_t address, uint32_t data)
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{
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uint8_t dataspi[8]; /* = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };*/
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int rc;
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dataspi[0] = 0x80 | (address >> 20 & 0x01); /* read/write bit (bit 31) to write */
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dataspi[1] = (address >> 12) & 0xFF;
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dataspi[2] = (address >> 4) & 0xFF;
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dataspi[3] = (address << 4) & 0xF0;
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dataspi[4] = (data >> 24) & 0xFF;
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dataspi[5] = (data >> 16) & 0xFF;
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dataspi[6] = (data >> 8) & 0xFF;
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dataspi[7] = data & 0xFF;
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rc = spi_xfer(spislave, 8*sizeof(dataspi) /*bitlen*/, dataspi, NULL /*din*/, SPI_XFER_BEGIN| SPI_XFER_END /*flags*/);
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return rc;
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}
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/*
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* Function: sja1105_read_reg
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* --------------------
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* perform the expected 64 bits access to readout 1 register ( multiple register not possible with this function)
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*
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* spi_slave: spi instance created from sja1105_setup_spi
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* address : expect to be max 21 bits (range 0x0 to 0x100BC3h)
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*
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* returns : 32 bits read on the address pass as argument
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*
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*/
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/*
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* readout 1 register (multiple register not possible with this function)
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* expect an address of 21 bits
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*/
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int sja1105_read_reg(struct spi_slave *spislave, uint32_t adress)
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{
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uint8_t dataspi[8];
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uint8_t datain[8];
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int rc;
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int return_value;
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/* OPCODE: READ, READ CNT = 1 */
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dataspi[0] = 0x02 | ((adress >> 20) & 0x01); /* read/write bit(bit 31) to read, and rc ( read count) to 1 double work */
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dataspi[1] = (adress >> 12) & 0xFF;
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dataspi[2] = (adress >> 4) & 0xFF;
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dataspi[3] = (adress << 4) & 0xF0;
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dataspi[4] = 0x00; /* ignore by slave, use to readout the register */
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dataspi[5] = 0x00;
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dataspi[6] = 0x00;
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dataspi[7] = 0x00;
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/* printf("%02x %02x %02x %02x\n", dataspi[0], dataspi[1], dataspi[2], dataspi[3]); */
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memset(datain, 0xaa, 8);
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rc = spi_xfer(spislave, 8*sizeof(dataspi) /*bitlen*/, dataspi, datain /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
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printf("sja1105_read_reg %d\n", rc);
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/*
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printf("%02x %02x %02x %02x\n", datain[0], datain[1], datain[2], datain[3]);
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printf("%02x %02x %02x %02x\n", datain[4], datain[5], datain[6], datain[7]);
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*/
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return_value = (datain[4]<<24) | (datain[5]<<16) | (datain[6]<<8) | (datain[7]<<0);
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/* Todo: check byte order */
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return return_value;
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}
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/*
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* Function: sja1105_dynamic_init
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* --------------------
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* Load the dynamic configuration of the switch after the static confiugration to configure the PLL and the CGU
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* this configuration aims to set clocks and system for RMII operation on all ports PLL 1 setup for 50Mhz
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* port 0 and 4: RMII (PHY mode = external REFCLK)
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* port 1,2 and 3: RMII (MAC mode)
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* spi_slave: spi instance created from sja1105_setup_spi
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*
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*/
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/* NOTE: this configuration assume that the driver does automatically
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* a multi-wods access CS deassert must only be done at the end of a conf block
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*/
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void sja1105_dynamic_init(struct spi_slave *spislave)
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{
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int rc;
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rc = sja1105_write_reg(spislave, 0x10000A, 0x0A010141); /* PLL 1 setup for 50MHz */
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rc = sja1105_write_reg(spislave, 0x10000A, 0x0A010940); /* PLL 1 setup for 50MHz */
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/* port 0: RMII (PHY mode = external REFCLK) */
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rc = sja1105_write_reg(spislave, 0x10000B, 0x0A000001);//Disable IDIV0
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rc = sja1105_write_reg(spislave, 0x100015, 0x00000800);//Setting CLKSRC of RMII_REF_CLK_0 to TX_CLK_0
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/* port 1: RMII (MAC mode) */
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rc = sja1105_write_reg(spislave, 0x10000C, 0x0A000001); //Disable IDIV1
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rc = sja1105_write_reg(spislave, 0x10001C, 0x02000800); //Setting CLKSRC of RMII_REF_CLK_1 to TX_CLK_1
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rc = sja1105_write_reg(spislave, 0x10001F, 0x0E000800); //setting CLKSRC of EXT_TX_CLK1 to PLL1 (50 MHz)
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/* port 2: RMII (MAC mode) */
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rc = sja1105_write_reg(spislave, 0x10000D, 0x0A000001); //Disable IDIV2
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rc = sja1105_write_reg(spislave, 0x100023, 0x04000800); //Setting CLKSRC of RMII_REF_CLK_2 to TX_CLK_2
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rc = sja1105_write_reg(spislave, 0x100026, 0x0E000800); //setting CLKSRC of EXT_TX_CLK2 to PLL1 (50 MHz)
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// port 3: RMII (MAC mode)
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rc = sja1105_write_reg(spislave, 0x10000E, 0x0A000001); //Disable IDIV3
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rc = sja1105_write_reg(spislave, 0x10002A, 0x06000800); //Setting CLKSRC of RMII_REF_CLK_3 to TX_CLK_3
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rc = sja1105_write_reg(spislave, 0x10002D, 0x0E000800); //setting CLKSRC of EXT_TX_CLK3 to PLL1 (50 MHz)
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// port 4: RMII (PHY mode = external REFCLK)
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rc = sja1105_write_reg(spislave, 0x10000F, 0x0A000001); //Disable IDIV4
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rc = sja1105_write_reg(spislave, 0x100031, 0x08000800); //Setting CLKSRC of RMII_REF_CLK_4 to TX_CLK_4
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printf("%d\n", rc);
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}
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/*
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* Function: sja1105_static_init
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* --------------------
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* Load the static configuration of the switch that must be loaded at startup of the switch
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* the config is generated by the Intel hex to C tools : Configuration is managed with sja1105_appboard_v14.exe
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*
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*
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* spi_slave: spi instance created from sja1105_setup_spi
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* config : list of configuration to load
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* 0: switch all port with no priority, with port 0 and 5 as PHY MODE , all other MAC Mode
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* ..: To be added
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*/
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/*Notes: this configuration assume that the driver does automatically a multi-wods access CS deassert must only be done at the end of a conf block*/
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void sja1105_static_init(struct spi_slave *spislave, int config)
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{
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static const uint8_t config_data_0[] = { 0x80, 0x20, 0x00, 0x00, 0x9E, 0x00, 0x03, 0x0E, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x21, 0x6F, 0x25, 0x6B, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0B, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF };
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static const uint8_t config_data_1[] = { 0x80, 0x20, 0x04, 0x00, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x0F, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFE, 0xF7, 0x00, 0x00, 0x13, 0xFF, 0xFF, 0xFF, 0xFA, 0x2E, 0x19, 0xF8, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0xF2, 0x69, 0x5C, 0xA5, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xF0, 0x00, 0x08, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0x80, 0x48, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xF0, 0x02, 0x52, 0x13, 0x87, 0x7B, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1A, 0x6A, 0xF6, 0x23, 0x53, 0x10, 0x00, 0x00, 0x00, 0xF7, 0xBD, 0xF5, 0x8D, 0x10, 0x00, 0x00, 0x00, 0xEF, 0x7B, 0xF5, 0x8D, 0x10, 0x00, 0x00, 0x00, 0xDE, 0xF7, 0xF5, 0x8D, 0x10, 0x00, 0x00, 0x00, 0xBD, 0xEF, 0xF5, 0x8D, 0x10, 0x00, 0x00, 0x00, 0x7B, 0xDF, 0xF5, 0x8D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x04, 0xA6, 0x06, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x23, 0xDA, 0xB5, 0xBD, 0xC8 };
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static const uint8_t config_data_2[] = { 0x80, 0x20, 0x08, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFC, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFC, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFC, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFC, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFC, 0x01, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x36, 0x62, 0x42, 0xCA, 0x0D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x25, 0x0E, 0x7C, 0xBD, 0x00, 0x01, 0x25, 0xC0, 0x70, 0x94, 0x84, 0x50, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xC8, 0xA7, 0xCE, 0xE6, 0x00, 0x71, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0xF7, 0x04, 0xB9, 0x11, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0A, 0x57, 0x1F, 0x81, 0x3F, 0x06, 0x44, 0x00, 0x00, 0x00, 0x00, 0x04, 0x08, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x0C, 0x30, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x0E, 0xFF, 0xFF, 0xFF, 0x80, 0xC2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x58, 0x00, 0x00, 0x00, 0x0F, 0xE4, 0x13, 0x21, 0x4E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 };
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static const uint8_t config_data_3[] = { 0x80, 0x20, 0x0C, 0x00, 0x3A, 0x5D, 0x5E, 0x24, 0xA4, 0x9A, 0x00, 0x00, 0x7B, 0x51, 0xDA, 0x7D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x4F, 0x18, 0x7C, 0xE2 };
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int rc;
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(void)config;
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rc = spi_xfer(spislave, 8*sizeof(config_data_0) /*bitlen*/, config_data_0, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
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if (rc != 0)
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printf ("spi_xfer fail for config data 0\n");
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rc = spi_xfer(spislave, 8*sizeof(config_data_1) /*bitlen*/, config_data_1, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
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if (rc != 0)
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printf ("spi_xfer fail for config data 1\n");
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rc = spi_xfer(spislave, 8*sizeof(config_data_2) /*bitlen*/, config_data_2, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
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if (rc != 0)
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printf ("spi_xfer fail for config data 2\n");
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rc = spi_xfer(spislave, 8*sizeof(config_data_3) /*bitlen*/, config_data_3, NULL /*din*/, SPI_XFER_BEGIN | SPI_XFER_END /*flags*/);
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if (rc != 0)
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printf ("spi_xfer fail for config data 3\n");
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}
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@ -0,0 +1,18 @@
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/*
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* sja1105.h
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*
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* Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
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*
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*SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SJA1105_H_
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#define _SJA1105_H_
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int sja1105_read_reg(struct spi_slave *spislave, uint32_t adress);
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int sja1105_write_reg(struct spi_slave *spislave, uint32_t address, uint32_t data);
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void sja1105_static_init(struct spi_slave *spislave, int config);
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void sja1105_dynamic_init(struct spi_slave *spislave);
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#endif
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