ADD: [nrhw22] added new board

BugzID: 56854
(cherry picked from commit a9fbbd0f75)
This commit is contained in:
Marcel Reichmuth 2019-04-29 10:07:35 +02:00
parent b723931900
commit b9de648b97
13 changed files with 1561 additions and 0 deletions

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@ -398,6 +398,14 @@ config TARGET_AM335X_NRHW20
select DM_SERIAL select DM_SERIAL
select DM_GPIO select DM_GPIO
config TARGET_AM335X_NRHW22
bool "Support am335x_nrhw22"
select CPU_V7
select SUPPORT_SPL
select DM
select DM_SERIAL
select DM_GPIO
config TARGET_AM335X_SL50 config TARGET_AM335X_SL50
bool "Support am335x_sl50" bool "Support am335x_sl50"
select CPU_V7 select CPU_V7
@ -897,6 +905,7 @@ source "board/mpl/vcma9/Kconfig"
source "board/nm/netbird/Kconfig" source "board/nm/netbird/Kconfig"
source "board/nm/netbird_v2/Kconfig" source "board/nm/netbird_v2/Kconfig"
source "board/nm/nrhw20/Kconfig" source "board/nm/nrhw20/Kconfig"
source "board/nm/nrhw22/Kconfig"
source "board/olimex/mx23_olinuxino/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig"
source "board/phytec/pcm051/Kconfig" source "board/phytec/pcm051/Kconfig"
source "board/phytec/pcm052/Kconfig" source "board/phytec/pcm052/Kconfig"

26
board/nm/nrhw22/Kconfig Normal file
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@ -0,0 +1,26 @@
if TARGET_AM335X_NRHW22
config SYS_BOARD
default "nrhw22"
config SYS_VENDOR
default "nm"
config SYS_SOC
default "am33xx"
config SYS_CONFIG_NAME
default "am335x_nrhw22"
config CONS_INDEX
int "UART used for console"
range 1 6
default 2
help
The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
in documentation, etc) available to it. Depending on your specific
board you may want something other than UART0 as for example the IDK
uses UART3 so enter 4 here.
endif

13
board/nm/nrhw22/Makefile Normal file
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@ -0,0 +1,13 @@
#
# Makefile
#
# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
#
# SPDX-License-Identifier: GPL-2.0+
#
ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
obj-y := mux.o
endif
obj-y += board.o ../common/bdparser.o ../common/board_descriptor.o fileaccess.o da9063.o

715
board/nm/nrhw22/board.c Normal file
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@ -0,0 +1,715 @@
/*
* board.c
*
* Board functions for Netmodule NRHW 20, based on AM335x EVB
*
* Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <spl.h>
#include <serial.h>
#include <asm/arch/cpu.h>
#include <asm/arch/hardware.h>
#include <asm/arch/omap.h>
#include <asm/arch/ddr_defs.h>
#include <asm/arch/clock.h>
#include <asm/arch/clk_synthesizer.h>
#include <asm/arch/gpio.h>
#include <asm/arch/mmc_host_def.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/mem.h>
#include <asm/io.h>
#include <asm/emif.h>
#include <asm/gpio.h>
#include <i2c.h>
#include <pca953x.h>
#include <miiphy.h>
#include <cpsw.h>
#include <environment.h>
#include <watchdog.h>
#include <libfdt.h>
#include "../common/bdparser.h"
#include "../common/board_descriptor.h"
#include "board.h"
#include "da9063.h"
#include "fileaccess.h"
DECLARE_GLOBAL_DATA_PTR;
/*
* CPU GPIOs
*
* GPIO0_2: RST_GNSS~
* GPIO0_5: EXTINT_GNSS
* GPIO0_6: TIMEPULSE_GNSS
*
* GPIO0_16: RST_PHY~
* GPIO0_17: PMIC FAULT
*
*/
#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
#define NETBIRD_GPIO_RST_PHY_N GPIO_TO_PIN(0, 16)
#define NETBIRD_GPIO_RST_USB_HUB_N GPIO_TO_PIN(3, 21)
#define NETBIRD_GPIO_RST_GNSS GPIO_TO_PIN(0, 2)
#define NETBIRD_GPIO_RST_PCI GPIO_TO_PIN(3, 10)
#define NETBIRD_GPIO_RST_GSM GPIO_TO_PIN(1, 25)
#define NETBIRD_GPIO_PWR_GSM GPIO_TO_PIN(1, 21)
#define NETBIRD_GPIO_WAKE_GSM GPIO_TO_PIN(0, 31)
#define NETBIRD_GPIO_SIM_SEL GPIO_TO_PIN(3, 17)
#define NETBIRD_GPIO_WLAN_EN GPIO_TO_PIN(1, 26)
#define NETBIRD_GPIO_BT_EN GPIO_TO_PIN(1, 20)
#define NETBIRD_GPIO_DIG_OUT GPIO_TO_PIN(1, 14)
#define NETBIRD_GPIO_DIG_IN GPIO_TO_PIN(1, 15)
#define NETBIRD_GPIO_PCI_WDIS GPIO_TO_PIN(3, 9)
/*
* PMIC GPIOs
*
* GPIO_7: EN_SUPPLY_GSM
* GPIO_8: VOLTAGE_SEL_PCIe
* GPIO_9: EN_SUPPLY_PCIe
* GPIO_10: LED0.RD~
* GPIO_11: LED0.GN~
*/
#define PMIC_GSM_SUPPLY_EN_IO 7
#define PMIC_PCIe_SUPPLY_VSEL_IO 8
#define PMIC_PCIe_SUPPLY_EN_IO 9
#define PMIC_LED0_BLUE 10
#define PMIC_LED0_GREEN 11
#define DDR3_CLOCK_FREQUENCY (400)
#if !defined(CONFIG_SPL_BUILD)
static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
#endif
#define I2C_BD_EEPROM_BUS (2)
#define BD_EEPROM_ADDR (0x50) /* CPU BD EEPROM (8kByte) is at 50 (A0) */
#define BD_ADDRESS (0x0000) /* Board descriptor at beginning of EEPROM */
#define PD_ADDRESS (0x0200) /* Product descriptor */
#define PARTITION_ADDRESS (0x0600) /* Partition Table */
static BD_Context bdctx[3]; /* The descriptor contexts */
static void init_i2c(void)
{
i2c_set_bus_num(0);
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
i2c_set_bus_num(2);
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
i2c_set_bus_num(0);
}
static int _bd_init(void)
{
int old_bus;
old_bus = i2c_get_bus_num();
i2c_set_bus_num(I2C_BD_EEPROM_BUS);
if (bd_get_context(&bdctx[0], BD_EEPROM_ADDR, BD_ADDRESS) != 0) {
printf("%s() no valid bd found\n", __func__);
return -1;
}
if (bd_get_context(&bdctx[1], BD_EEPROM_ADDR, PD_ADDRESS) != 0) {
printf("%s() no valid pd found (legacy support)\n", __func__);
return -1;
}
if (bd_get_context(&bdctx[2], BD_EEPROM_ADDR, PARTITION_ADDRESS) != 0) {
printf("%s() no valid partition table found\n", __func__);
return -1;
}
bd_register_context_list(bdctx, ARRAY_SIZE(bdctx));
i2c_set_bus_num(old_bus);
return 0;
}
static bool is_jtag_boot(uint32_t address)
{
char* jtag_token = (char*)address;
if (strcmp(jtag_token, "JTAGBOOT") == 0) {
strcpy(jtag_token, "jtagboot");
return true;
}
else {
return false;
}
}
/*
* Read header information from EEPROM into global structure.
*/
static inline int __maybe_unused read_eeprom(void)
{
return _bd_init();
}
/* Selects console for SPL.
* U-Boot console is defined by CONSOLE_INDEX variable
* defined using serial_set_console_index(int index)
*/
struct serial_device *default_serial_console(void)
{
return &eserial1_device;
}
#ifndef CONFIG_SKIP_LOWLEVEL_INIT
static const struct ddr_data ddr3_netbird_data = {
/* Ratios were optimized by DDR3 training software from TI */
.datardsratio0 = 0x39,
.datawdsratio0 = 0x3f,
.datafwsratio0 = 0x98,
.datawrsratio0 = 0x7d,
};
static const struct cmd_control ddr3_netbird_cmd_ctrl_data = {
.cmd0csratio = MT41K256M16HA125E_RATIO,
.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd1csratio = MT41K256M16HA125E_RATIO,
.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
.cmd2csratio = MT41K256M16HA125E_RATIO,
.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
};
static struct emif_regs ddr3_emif_reg_data = {
.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
.ref_ctrl = 0x61A, /* 32ms > 85°C */
.sdram_tim1 = 0x0AAAE51B,
.sdram_tim2 = 0x246B7FDA,
.sdram_tim3 = 0x50FFE67F,
.zq_config = MT41K256M16HA125E_ZQ_CFG,
.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
};
#define OSC (V_OSCK/1000000)
struct dpll_params dpll_ddr_nrhw22 = {
DDR3_CLOCK_FREQUENCY, OSC-1, 1, -1, -1, -1, -1
};
void am33xx_spl_board_init(void)
{
/* Set CPU speed to 600 MHz (fix) */
dpll_mpu_opp100.m = MPUPLL_M_600;
/* Set CORE Frequencies to OPP100 (600MHz) */
do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
/* Configure both I2C buses used in NRHW22 */
init_i2c();
/* Configure default PMIC current limits. Will be overridden in Linux.
* MEM = 1.5A (0.55A)
* IO = 1.5A (0.5A)
* PERI = 2.0A (1.0A)
* PRO = 0.5A (unused)
* CORE2 = 2.0A (0.55A)
* CORE1 = 2.0A (0.25A, seems too low)
*/
da9063_init(CONFIG_PMIC_I2C_BUS);
da9063_set_reg(PMIC_REG_BUCK_ILIM_A, 0x00);
da9063_set_reg(PMIC_REG_BUCK_ILIM_B, 0x50);
da9063_set_reg(PMIC_REG_BUCK_ILIM_C, 0xFF);
/* Set MPU Frequency to what we detected now that voltages are set */
do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
/* Debugger can place marker at end of SRAM to stop boot here */
if (is_jtag_boot(CONFIG_JTAG_MARKER_SPL))
{
puts("Detected JTAG boot, executing bkpt #0\n");
__asm__ __volatile__ ("bkpt #0");
}
}
const struct dpll_params *get_dpll_ddr_params(void)
{
dpll_ddr_nrhw22.n = (get_osclk() / 1000000) - 1;
return &dpll_ddr_nrhw22;
}
void set_uart_mux_conf(void)
{
enable_uart0_pin_mux();
enable_uart1_pin_mux();
}
void set_mux_conf_regs(void)
{
enable_board_pin_mux();
}
const struct ctrl_ioregs ioregs_netbird = {
.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
};
void sdram_init(void)
{
config_ddr(DDR3_CLOCK_FREQUENCY, &ioregs_netbird,
&ddr3_netbird_data,
&ddr3_netbird_cmd_ctrl_data,
&ddr3_emif_reg_data, 0);
}
#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
#if !defined(CONFIG_SPL_BUILD)
static void request_and_set_gpio(int gpio, const char *name, int value)
{
int ret;
ret = gpio_request(gpio, name);
if (ret < 0) {
printf("%s: Unable to request %s\n", __func__, name);
return;
}
/* TODO: Set value here, remove later call gpio_set_value */
ret = gpio_direction_output(gpio, 0);
if (ret < 0) {
printf("%s: Unable to set %s as output\n", __func__, name);
goto err_free_gpio;
}
gpio_set_value(gpio, value);
return;
err_free_gpio:
gpio_free(gpio);
}
#define REQUEST_AND_SET_GPIO(N) request_and_set_gpio(N, #N, 1);
#define REQUEST_AND_CLEAR_GPIO(N) request_and_set_gpio(N, #N, 0);
#endif
static void set_status_led(int blue, int green)
{
/* LED outputs are active low, invert state */
da9063_set_gpio(PMIC_LED0_BLUE, !blue);
da9063_set_gpio(PMIC_LED0_GREEN, !green);
}
#if !defined(CONFIG_SPL_BUILD)
static void init_ethernet_switch(void)
{
REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_RST_PHY_N);
mdelay(1);
/* OMAP3 does not feature open drain pins, thus configure pin as input */
gpio_direction_input(NETBIRD_GPIO_RST_PHY_N);
/* When the Ethernet switch senses reset, it drives reset for 8..14ms
* Wait longer than this time to avoid IO congestion later on.
*/
mdelay(20);
}
#endif /* !defined(CONFIG_SPL_BUILD) */
/*
* Basic board specific setup. Pinmux has been handled already.
* Not called in SPL build.
*/
int board_init(void)
{
#if defined(CONFIG_HW_WATCHDOG)
hw_watchdog_init();
#endif
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
/* Configure both I2C buses used in NRHW22 */
init_i2c();
da9063_init(CONFIG_PMIC_I2C_BUS);
/* Let user know we're starting */
set_status_led(1, 1);
printf("OSC: %lu MHz\n", get_osclk()/1000000);
return 0;
}
#if !defined(CONFIG_SPL_BUILD)
extern int console_init_f(void);
extern void serial_set_console_index(int index);
/*
* Set Linux console based on
* - Selection in /root/boot/consoledev
* - Available tty interfaces
* - ttyS1: standard console (default)
* - ttyS0: COM/IO shield (or used as console by kernel,
* when no other console available)
* - ttyNull0: Dummy device if no real UART is available
*/
void set_console(void)
{
const char *defaultconsole = getenv("defaultconsole");
char buf[20];
int i;
/* Set default console to ttyS1 if not yet defined in env */
if (defaultconsole == 0) {
setenv("defaultconsole", "ttyS1");
}
/* If consoledev file is present, take the tty defined in it as console */
if (read_file("/root/boot/consoledev",buf, sizeof(buf)) > 3) {
if (strstr(buf, "tty") == buf) {
buf[sizeof(buf)-1] = 0;
for (i=0; i<sizeof(buf); i++) {
if (buf[i]<=' ') {
buf[i] = 0;
break;
}
}
setenv("defaultconsole", buf);
}
}
#if defined(CONFIG_PRE_CONSOLE_BUFFER)
defaultconsole = getenv("defaultconsole");
serial_set_console_index(0);
serial_init(); /* serial communications setup */
console_init_f(); /* stage 1 init of console */
#else
serial_set_console_index(1);
#endif
}
static void set_devicetree_name(void)
{
char devicetreename[64];
/* add hardware versions to environment */
if (bd_get_devicetree(devicetreename, sizeof(devicetreename)) != 0) {
printf("Devicetree name not found, using default name\n");
strcpy(devicetreename, "am335x-nrhw22-prod1.dtb");
}
setenv("fdt_image", devicetreename);
}
static void set_root_partition(void)
{
int boot_partition;
/* add active root partition to environment */
boot_partition = bd_get_boot_partition();
if (boot_partition > 1) {
boot_partition = 0;
}
/* mmcblk0p1 => root0, mmcblk0p2 => root1 so +1 */
setenv_ulong("root_part", boot_partition + 1);
}
static void get_hw_version(void)
{
int hw_ver, hw_rev;
char hw_versions[16];
char new_env[256]; /* current bootargs = 84 bytes */
bd_get_hw_version(&hw_ver, &hw_rev);
printf("HW22: V%d.%d\n", hw_ver, hw_rev);
/* add hardware versions to environment */
snprintf(hw_versions, sizeof(hw_versions), "CP=%d.%d", hw_ver, hw_rev);
snprintf(new_env, sizeof(new_env), "setenv bootargs $bootargs %s", hw_versions);
setenv("add_version_bootargs", new_env);
}
static bool get_button_state(void)
{
u8 state = 0x00;
(void)da9063_get_reg(PMIC_REG_STATUS_A, &state);
return (state & 0x01) == 0x01;
}
static void blink_led(int red)
{
const int pulse_width = 400*1000; /* 400ms */
/* Assumes green status LED is on */
udelay(pulse_width);
set_status_led(red, 1-red);
udelay(pulse_width);
set_status_led(0, 1);
}
static void check_reset_button(void)
{
int counter = 0;
/* Check how long button is pressed */
do {
if (!get_button_state())
break;
udelay(100*1000); /* 100ms */
counter += 100;
if (counter == 2000) {
/* Indicate factory reset threshold */
blink_led(0);
}
else if (counter == 12000) {
/* Indicate recovery boot threshold */
blink_led(1);
}
} while (counter < 12000);
if (counter < 2000) {
/* Don't do anything for duration < 2s */
}
else if (counter < 12000)
{
/* Do factory reset for duration between 2s and 12s */
char new_bootargs[512];
char *bootargs = getenv("bootargs");
if (bootargs == 0) bootargs="";
printf("Do factory reset during boot...\n");
strncpy(new_bootargs, bootargs, sizeof(new_bootargs));
strncat(new_bootargs, " factory-reset", sizeof(new_bootargs));
setenv("bootargs", new_bootargs);
}
else
{
/* Boot into recovery for duration > 12s */
printf("Booting recovery image...\n");
/* Set consoledev to external port */
setenv("defaultconsole", "ttyS1");
/* Set bootcmd to run recovery */
setenv("bootcmd", "run recovery");
}
}
static void check_jtag_boot(void)
{
if (is_jtag_boot(CONFIG_JTAG_MARKER_UBOOT)) {
char *bootcmd = getenv("bootcmd");
setenv ("bootcmd", "");
/* Save original bootcmd in "bc" to allow manual boot */
setenv ("bc", bootcmd);
puts("Detected JTAG boot. Waiting on command line\n");
}
}
#endif /* !defined(CONFIG_SPL_BUILD) */
int board_late_init(void)
{
#if !defined(CONFIG_SPL_BUILD)
if (read_eeprom() < 0)
puts("Could not get board ID.\n");
get_hw_version();
set_root_partition();
set_devicetree_name();
/* Initialize pins */
REQUEST_AND_CLEAR_GPIO(NETBIRD_GPIO_RST_GNSS);
init_ethernet_switch();
check_reset_button();
set_console();
set_status_led(0, 0);
check_jtag_boot();
#endif
return 0;
}
#ifndef CONFIG_DM_ETH
#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
(defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
static void cpsw_control(int enabled)
{
/* VTP can be added here */
return;
}
static struct cpsw_slave_data cpsw_slaves[] = {
{
.slave_reg_ofs = 0x208,
.sliver_reg_ofs = 0xd80,
.phy_addr = 0,
},
{
.slave_reg_ofs = 0x308,
.sliver_reg_ofs = 0xdc0,
.phy_addr = 1,
},
};
static struct cpsw_platform_data cpsw_data = {
.mdio_base = CPSW_MDIO_BASE,
.cpsw_base = CPSW_BASE,
.mdio_div = 0xff,
.channels = 8,
.cpdma_reg_ofs = 0x800,
.slaves = 1,
.slave_data = cpsw_slaves,
.ale_reg_ofs = 0xd00,
.ale_entries = 1024,
.host_port_reg_ofs = 0x108,
.hw_stats_reg_ofs = 0x900,
.bd_ram_ofs = 0x2000,
.mac_control = (1 << 5),
.control = cpsw_control,
.host_port_num = 0,
.version = CPSW_CTRL_VERSION_2,
};
#endif
#if ((defined(CONFIG_SPL_ETH_SUPPORT) || defined(CONFIG_SPL_USBETH_SUPPORT)) &&\
defined(CONFIG_SPL_BUILD)) || \
((defined(CONFIG_DRIVER_TI_CPSW) || \
defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
!defined(CONFIG_SPL_BUILD))
static void set_mac_address(int index, uchar mac[6])
{
/* Then take mac from bd */
if (is_valid_ethaddr(mac)) {
eth_setenv_enetaddr_by_index("eth", index, mac);
}
else {
printf("Trying to set invalid MAC address");
}
}
/* TODO: Update doc */
/*
* This function will:
* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
* in the environment
* Perform fixups to the PHY present on certain boards. We only need this
* function in:
* - SPL with either CPSW or USB ethernet support
* - Full U-Boot, with either CPSW or USB ethernet
* Build in only these cases to avoid warnings about unused variables
* when we build an SPL that has neither option but full U-Boot will.
*/
int board_eth_init(bd_t *bis)
{
int rv, n = 0;
uint8_t mac_addr0[6] = {02,00,00,00,00,01};
__maybe_unused struct ti_am_eeprom *header;
#if !defined(CONFIG_SPL_BUILD)
#ifdef CONFIG_DRIVER_TI_CPSW
cpsw_data.mdio_div = 0x3E;
bd_get_mac(0, mac_addr0, sizeof(mac_addr0));
set_mac_address(0, mac_addr0);
writel(RMII_MODE_ENABLE | RMII_CHIPCKL_ENABLE, &cdev->miisel);
cpsw_slaves[0].phy_if = PHY_INTERFACE_MODE_RMII;
cpsw_slaves[1].phy_if = PHY_INTERFACE_MODE_RMII;
cpsw_slaves[0].phy_addr = 0;
cpsw_slaves[1].phy_addr = 1;
rv = cpsw_register(&cpsw_data);
if (rv < 0)
printf("Error %d registering CPSW switch\n", rv);
else
n += rv;
#endif
#endif
#if defined(CONFIG_USB_ETHER) && \
(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USBETH_SUPPORT))
if (is_valid_ethaddr(mac_addr0))
eth_setenv_enetaddr("usbnet_devaddr", mac_addr0);
rv = usb_eth_initialize(bis);
if (rv < 0)
printf("Error %d registering USB_ETHER\n", rv);
else
n += rv;
#endif
return n;
}
#endif
#endif /* CONFIG_DM_ETH */
#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
return 0;
}
#endif
#if defined(CONFIG_OF_BOARD_SETUP)
int ft_board_setup(void *blob, bd_t *bd)
{
return 0;
}
#endif

35
board/nm/nrhw22/board.h Normal file
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@ -0,0 +1,35 @@
/*
* board.h
*
* TI AM335x boards information header
*
* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef _BOARD_H_
#define _BOARD_H_
/*
* We have three pin mux functions that must exist. We must be able to enable
* uart0, for initial output and i2c2 to read the main EEPROM. We then have a
* main pinmux function that can be overridden to enable all other pinmux that
* is required on the board.
*/
void enable_uart0_pin_mux(void);
void disable_uart0_pin_mux(void);
void enable_uart1_pin_mux(void);
void enable_uart3_pin_mux(void);
void enable_uart5_pin_mux(void);
/*
void enable_uart2_pin_mux(void);
void enable_uart3_pin_mux(void);
void enable_uart4_pin_mux(void);
void enable_uart5_pin_mux(void);
*/
void enable_i2c0_pin_mux(void);
void enable_i2c2_pin_mux(void);
void enable_board_pin_mux(void);
#define GPIO_TO_PIN(bank, gpio) (32 * (bank) + (gpio))
#endif

92
board/nm/nrhw22/da9063.c Normal file
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/*
* da9063.c
*
* Dialog DA9063 PMIC
*
* Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <errno.h>
#include <i2c.h>
#include "da9063.h"
static int da9063_i2c_bus = 0;
void da9063_init(int i2c_bus)
{
da9063_i2c_bus = i2c_bus;
}
int da9063_get_reg(int reg, u8* val)
{
int ret;
int old_bus;
u8 temp;
/* TODO: Check whether switching is required */
old_bus = i2c_get_bus_num();
i2c_set_bus_num(da9063_i2c_bus);
/* TODO: Use CONFIG_PMIC_I2C_ADDR+1 if reg > 0xFF */
*val = 0;
ret = i2c_read(CONFIG_PMIC_I2C_ADDR, reg, 1, &temp, 1);
if (ret == 0)
*val = temp;
i2c_set_bus_num(old_bus);
return ret;
}
int da9063_set_reg(int reg, u8 val)
{
int ret;
int old_bus;
/* TODO: Check whether switching is required */
old_bus = i2c_get_bus_num();
i2c_set_bus_num(da9063_i2c_bus);
/* TODO: Use CONFIG_PMIC_I2C_ADDR+1 if reg > 0xFF */
ret = i2c_write(CONFIG_PMIC_I2C_ADDR, reg, 1, &val, 1);
if (ret != 0)
puts("da9063 write error\n");
i2c_set_bus_num(old_bus);
return ret;
}
void da9063_set_gpio(unsigned bit, int state)
{
int pmic_reg;
int ret;
u8 bitmask;
u8 reg = 0x00;
if (bit <= 7) {
pmic_reg = PMIC_REG_GPIO_MODE0_7;
bitmask = 1U << (bit-0);
}
else {
pmic_reg = PMIC_REG_GPIO_MODE8_15;
bitmask = 1U << (bit-8);
}
/* printf("da9063_set_gpio %d 0x%04x\n", pmic_reg, bitmask); */
ret = da9063_get_reg(pmic_reg, &reg);
if (ret == 0) {
if (state) reg |= bitmask;
else reg &= ~bitmask;
(void)da9063_set_reg(pmic_reg, reg);
}
}

36
board/nm/nrhw22/da9063.h Normal file
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/*
* da9063.c
*
* Dialog DA9063 PMIC
*
* Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
*
* SPDX-License-Identifier: GPL-2.0+
*/
#ifndef DA9063_H
#define DA9063_H
#define CONFIG_PMIC_I2C_BUS 0
#define CONFIG_PMIC_I2C_ADDR 0x58 /* Pages 0 and 1, Pages 2 and 3 -> 0x59 */
#define PMIC_REG_STATUS_A 0x01 /* Status of ON_KEY, WAKE, COMP1V2, DVC */
#define PMIC_REG_GPIO_MODE0_7 0x1D /* Control register for GPIOs 0..7 */
#define PMIC_REG_GPIO_MODE8_15 0x1E /* Control register for GPIOs 8..15 */
#define PMIC_REG_BBAT_CONT 0xC5 /* Control register for backup battery */
#define PMIC_REG_BUCK_ILIM_A 0x9A
#define PMIC_REG_BUCK_ILIM_B 0x9B
#define PMIC_REG_BUCK_ILIM_C 0x9C
extern void da9063_init(int i2c_bus);
extern int da9063_get_reg(int reg, u8* val);
extern int da9063_set_reg(int reg, u8 val);
extern void da9063_set_gpio(unsigned bit, int state);
#endif /* DA9063_H */

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@ -0,0 +1,40 @@
#include <common.h>
#include <fs.h>
#define BLOCK_DEVICE "mmc"
#define OVERLAY_PART "1:3"
int read_file(const char* filename, char *buf, int size)
{
loff_t filesize = 0;
loff_t len;
int ret;
if (fs_set_blk_dev(BLOCK_DEVICE, OVERLAY_PART, FS_TYPE_EXT) != 0) {
puts("Error, can not set blk device\n");
return -1;
}
/* Read at most file size bytes */
if (fs_size(filename, &filesize)) {
return -1;
}
if (filesize < size)
size = filesize;
/* For very unclear reasons the block device needs to be set again after the call to fs_size() */
if (fs_set_blk_dev(BLOCK_DEVICE, OVERLAY_PART, FS_TYPE_EXT) != 0) {
puts("Error, can not set blk device\n");
return -1;
}
if ((ret = fs_read(filename, (ulong)buf, 0, size, &len))) {
printf("Can't read file %s (size %d, len %lld, ret %d)\n", filename, size, len, ret);
return -1;
}
buf[len] = 0;
return len;
}

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/**@file /home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/fileaccess.h
* @author eichenberger
* @version 704
* @date
* Created: Tue 06 Jun 2017 02:02:33 PM CEST \n
* Last Update: Tue 06 Jun 2017 02:02:33 PM CEST
*/
#ifndef FILEACCESS_H
#define FILEACCESS_H
void fs_set_console(void);
int read_file(const char* filename, char *buf, int size);
#endif // FILEACCESS_H

146
board/nm/nrhw22/mux.c Normal file
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/*
* mux.c
*
* Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include "board.h"
static struct module_pin_mux gpio_pin_mux[] = {
/*
* GPIO0_2: RST_GNSS~
* GPIO0_5: EXTINT_GNSS
* GPIO0_6: TIMEPULSE_GNSS
* GPIO0_16: RST_PHY~
* GPIO0_17: PMIC FAULT
*
*/
/* Bank 0 */
{OFFSET(spi0_sclk), (MODE(7) | PULLUDDIS)}, /* (A17) gpio0[2] */ /* RST_GNSS */
{OFFSET(spi0_cs0), (MODE(7) | PULLUDEN | PULLDOWN_EN)}, /* (A16) gpio0[5] */ /* EXTINT_GNSS */
{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},/* (C15) gpio0[6] */ /* TIMEPULSE_GNSS */
{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)}, /* (J18) gpio0[16] */ /* RST_PHY~ */
{OFFSET(mii1_txd2), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (K15) gpio0[17] */ /* PMIC_FAULT */
{-1},
};
/* I2C0 PMIC */
static struct module_pin_mux i2c0_pin_mux[] = {
{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* (C17) I2C0_SDA */
{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* (C16) I2C0_SCL */
{-1},
};
/* I2C2 System */
static struct module_pin_mux i2c2_pin_mux[] = {
{OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* (D17) I2C2_SCL */
{OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* (D18) I2C2_SDA */
{-1},
};
/* RMII1: Ethernet Switch */
static struct module_pin_mux rmii1_pin_mux[] = {
/* RMII */
{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE}, /* (H17) rmii1_crs */
{OFFSET(mii1_rxerr), MODE(7) | PULLUDEN | PULLDOWN_EN | RXACTIVE}, /* (J15) gpio */
{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE}, /* (M16) rmii1_rxd0 */
{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE}, /* (L15) rmii1_rxd1 */
{OFFSET(mii1_txen), MODE(1) | PULLUDDIS}, /* (J16) rmii1_txen */
{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS}, /* (K17) rmii1_txd0 */
{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS}, /* (K16) rmii1_txd1 */
{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE}, /* (H18) rmii1_refclk */
/* SMI */
{OFFSET(mdio_clk), MODE(0) | PULLUDDIS}, /* (M18) mdio_clk */
{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE}, /* (M17) mdio_data */
/* 25MHz Clock Output */
{OFFSET(xdma_event_intr0), MODE(3)}, /* (A15) clkout1 (25 MHz clk for Switch) */
{-1},
};
/* MMC1: eMMC */
static struct module_pin_mux mmc1_emmc_pin_mux[] = {
{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_CLK */
{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_CMD */
{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT0 */
{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT1 */
{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT2 */
{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT3 */
{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT4 */
{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT5 */
{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT6 */
{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_DAT7 */
{-1},
};
/* UART0: RS232 console */
static struct module_pin_mux uart0_pin_mux[] = {
{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (E15) UART0_RXD */
{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* (E16) UART0_TXD */
{-1},
};
/* UART1: GNSS */
static struct module_pin_mux uart1_pin_mux[] = {
{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (D16) uart1_rxd */
{OFFSET(uart1_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)}, /* (D15) uart1_txd */
{-1},
};
static struct module_pin_mux unused_pin_mux[] = {
/* SYSBOOT6, 7, 10, 11: Not used pulldown active, receiver disabled */
{OFFSET(lcd_data6), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
{OFFSET(lcd_data7), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
{OFFSET(lcd_data10), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
{OFFSET(lcd_data11), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
/* TODO: GPMCA1..3, A6..8 */
{-1},
};
void enable_board_pin_mux(void)
{
configure_module_pin_mux(gpio_pin_mux);
configure_module_pin_mux(rmii1_pin_mux);
configure_module_pin_mux(mmc1_emmc_pin_mux);
configure_module_pin_mux(i2c0_pin_mux);
configure_module_pin_mux(i2c2_pin_mux);
configure_module_pin_mux(uart0_pin_mux);
configure_module_pin_mux(uart1_pin_mux);
configure_module_pin_mux(unused_pin_mux);
}
void enable_uart0_pin_mux(void)
{
configure_module_pin_mux(uart0_pin_mux);
}
void enable_uart1_pin_mux(void)
{
configure_module_pin_mux(uart1_pin_mux);
}

158
board/nm/nrhw22/u-boot.lds Normal file
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@ -0,0 +1,158 @@
/*
* Copyright (c) 2004-2008 Texas Instruments
*
* (C) Copyright 2002
* Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
ENTRY(_start)
SECTIONS
{
. = 0x00000000;
. = ALIGN(4);
.text :
{
*(.__image_copy_start)
*(.vectors)
CPUDIR/start.o (.text*)
board/nm/nrhw22/built-in.o (.text*)
*(.text*)
}
. = ALIGN(4);
.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
. = ALIGN(4);
.data : {
*(.data*)
}
. = ALIGN(4);
. = .;
. = ALIGN(4);
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(4);
.__efi_runtime_start : {
*(.__efi_runtime_start)
}
.efi_runtime : {
*(efi_runtime_text)
*(efi_runtime_data)
}
.__efi_runtime_stop : {
*(.__efi_runtime_stop)
}
.efi_runtime_rel_start :
{
*(.__efi_runtime_rel_start)
}
.efi_runtime_rel : {
*(.relefi_runtime_text)
*(.relefi_runtime_data)
}
.efi_runtime_rel_stop :
{
*(.__efi_runtime_rel_stop)
}
. = ALIGN(4);
.image_copy_end :
{
*(.__image_copy_end)
}
.rel_dyn_start :
{
*(.__rel_dyn_start)
}
.rel.dyn : {
*(.rel*)
}
.rel_dyn_end :
{
*(.__rel_dyn_end)
}
.hash : { *(.hash*) }
.end :
{
*(.__end)
}
_image_binary_end = .;
/*
* Deprecated: this MMU section is used by pxa at present but
* should not be used by new boards/CPUs.
*/
. = ALIGN(4096);
.mmutable : {
*(.mmutable)
}
/*
* Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
* __bss_base and __bss_limit are for linker only (overlay ordering)
*/
.bss_start __rel_dyn_start (OVERLAY) : {
KEEP(*(.__bss_start));
__bss_base = .;
}
.bss __bss_base (OVERLAY) : {
*(.bss*)
. = ALIGN(4);
__bss_limit = .;
}
.bss_end __bss_limit (OVERLAY) : {
KEEP(*(.__bss_end));
}
.dynsym _image_binary_end : { *(.dynsym) }
.dynbss : { *(.dynbss) }
.dynstr : { *(.dynstr*) }
.dynamic : { *(.dynamic*) }
.gnu.hash : { *(.gnu.hash) }
.plt : { *(.plt*) }
.interp : { *(.interp*) }
.gnu : { *(.gnu*) }
.ARM.exidx : { *(.ARM.exidx*) }
}

View File

@ -0,0 +1,49 @@
CONFIG_ARM=y
CONFIG_TARGET_AM335X_NRHW22=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_SPL=y
CONFIG_SPL_STACK_R=y
CONFIG_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
CONFIG_HUSH_PARSER=y
CONFIG_AUTOBOOT_KEYED=y
CONFIG_AUTOBOOT_PROMPT="Press s to abort autoboot in %d seconds\n"
CONFIG_AUTOBOOT_STOP_STR="s"
CONFIG_CMD_BOOTZ=y
# CONFIG_CMD_IMLS is not set
CONFIG_CMD_ASKENV=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_MMC=y
CONFIG_CMD_I2C=y
# CONFIG_CMD_USB is not set
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_DHCP=y
CONFIG_CMD_MII=y
CONFIG_CMD_PING=y
CONFIG_CMD_EXT2=y
CONFIG_CMD_EXT4=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_FAT=y
CONFIG_CMD_FS_GENERIC=y
CONFIG_DFU_TFTP=y
CONFIG_SYS_NS16550=y
# CONFIG_USB is not set
# CONFIG_USB_MUSB_HOST is not set
# CONFIG_USB_MUSB_GADGET is not set
# CONFIG_USB_GADGET is not set
# CONFIG_USB_GADGET_DOWNLOAD is not set
CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
CONFIG_G_DNL_VENDOR_NUM=0x0451
CONFIG_G_DNL_PRODUCT_NUM=0xd022
CONFIG_OF_LIBFDT=y
# CONFIG_BOOTP_PXE_CLIENTARCH is not set
# CONFIG_CMD_PXE is not set
# CONFIG_CMD_BOOTEFI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_ELF is not set
# CONFIG_FPGA is not set
# CONFIG_CMD_FPGA is not set
# CONFIG_CMD_PMIC is not set
# CONFIG_EFI_LOADER is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set

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@ -0,0 +1,228 @@
/*
* am335x_phts.h
*
* Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
* Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation version 2.
*
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
* kind, whether express or implied; without even the implied warranty
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __CONFIG_AM335X_NRHW22_H
#define __CONFIG_AM335X_NRHW22_H
#include <configs/ti_am335x_common.h>
#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
#undef CONFIG_HW_WATCHDOG
#undef CONFIG_OMPAP_WATCHDOG
#undef CONFIG_SPL_WATCHDOG_SUPPORT
#ifndef CONFIG_SPL_BUILD
# define CONFIG_TIMESTAMP
# define CONFIG_LZO
#endif
#define CONFIG_SYS_BOOTM_LEN (16 << 20)
#define MACH_TYPE_TIAM335EVM 3589 /* Until the next sync */
#define CONFIG_MACH_TYPE MACH_TYPE_TIAM335EVM
#define CONFIG_BOARD_LATE_INIT
#if 0
#define CONFIG_PRE_CONSOLE_BUFFER 1
#define CONFIG_PRE_CON_BUF_ADDR 0x80000000
#define CONFIG_PRE_CON_BUF_SZ 64*1024
#endif
/* Clock Defines */
#define V_OSCK 0 /* 0 means detect from sysboot1 config */
#define V_SCLK (V_OSCK)
#include <config_distro_bootcmd.h>
#define CONFIG_ARP_TIMEOUT 200
#undef CONFIG_NET_RETRY_COUNT
#define CONFIG_NET_RETRY_COUNT 5
#define CONFIG_BOOTP_MAY_FAIL
#ifndef CONFIG_SPL_BUILD
#define KERNEL_ADDR "0x80000000"
#define LOAD_ADDR "0x83000000"
#define FDT_ADDR "0x82000000"
#define PXE_ADDR "0x82800000"
#define FDT_HIGH_ADDR "0x9f000000"
#define INIT_RD_ADDR "0x88000000"
#define CONFIG_EXTRA_ENV_SETTINGS \
"kernel_image=kernel.bin\0" \
"fdt_image=am335x-phts.dtb\0"\
"modeboot=sdboot\0" \
"fdt_addr=" FDT_ADDR "\0" \
"kernel_addr=" KERNEL_ADDR "\0" \
"load_addr=" LOAD_ADDR "\0" \
"root_part=1\0" /* Default root partition, overwritten in board file */ \
"defaultconsole=ttyS1\0" /* Default output console */ \
"add_sd_bootargs=setenv bootargs $bootargs root=/dev/mmcblk0p$root_part rootfstype=ext4 " \
"console=$defaultconsole,115200 rootwait loglevel=4 ti_cpsw.rx_packet_max=1526\0" \
"add_version_bootargs=setenv bootargs $bootargs\0" \
"fdt_skip_update=yes\0" \
"ethprime=cpsw\0" \
"sdbringup=echo Try bringup boot && ext4load mmc 1:$root_part $kernel_addr /boot/zImage && " \
"ext4load mmc 1:$root_part $fdt_addr /boot/$fdt_image && setenv bootargs $bootargs rw;\0" \
"sdprod=ext4load mmc 1:$root_part $kernel_addr /boot/$kernel_image && " \
"ext4load mmc 1:$root_part $fdt_addr /boot/$fdt_image && setenv bootargs $bootargs ro;\0" \
"sdboot=if mmc dev 1; then echo Copying Linux from SD to RAM...; "\
"if test -e mmc 1:$root_part /boot/$kernel_image; then run sdprod; " \
"else run sdbringup; fi; " \
"run add_sd_bootargs; run add_version_bootargs; run shieldcmd; " \
"bootz $kernel_addr - $fdt_addr; fi\0" \
"bootcmd=run sdboot\0" \
"ipaddr=192.168.1.1\0" \
"serverip=192.168.1.254\0" \
"pxefile_addr_r=" PXE_ADDR "\0" \
"fdt_addr_r=" FDT_ADDR "\0" \
"fdt_high=" FDT_HIGH_ADDR "\0" \
"kernel_addr_r=" KERNEL_ADDR "\0" \
"ramdisk_addr_r=" LOAD_ADDR "\0" \
"initrd_high=" INIT_RD_ADDR "\0" \
"bootpretryperiod=1000\0" \
"tftptimeout=2000\0" \
"tftptimeoutcountmax=5\0" \
"bootpretryperiod=2000\0" \
"autoload=false\0" \
"shieldcmd=\0" \
"tftp_recovery=tftpboot $kernel_addr recovery-image; tftpboot $fdt_addr recovery-dtb; " \
"setenv bootargs rdinit=/etc/preinit console=$defaultconsole,115200 " \
"debug ti_cpsw.rx_packet_max=1526; run shieldcmd; " \
"bootz $kernel_addr - $fdt_addr\0" \
"pxe_recovery=sleep 3 && dhcp && pxe get && pxe boot\0" \
"recovery=run pxe_recovery || setenv ipaddr $ipaddr; setenv serverip $serverip; run tftp_recovery\0" \
/* setenv ipaddr and serverip is necessary, because dhclient can destroy the IPs inernally */
#endif
/* UART Configuration */
#define CONFIG_SYS_NS16550_COM1 0x44e09000 /* UART0: Console */
#define CONFIG_SYS_NS16550_COM2 0x48022000 /* UART1: GNSS */
#define CONFIG_SYS_NS16550_COM3 0x48024000 /* Unused */
#define CONFIG_SYS_NS16550_COM4 0x481A6000 /* Unused */
#define CONFIG_SYS_NS16550_COM5 0x481A8000 /* Unused */
#define CONFIG_SYS_NS16550_COM6 0x481AA000 /* Unused */
#define CONFIG_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_CMD_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* Main EEPROM */
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
#define CONFIG_SYS_I2C_SPEED 100000
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 50 /* TODO: Can this be reduced to 20ms */
/* Put Environment in eMMC */
#define CONFIG_ENV_OFFSET (512 * 128) /* @ 512*256 SPL starts */
#define CONFIG_ENV_SIZE (4 * 1024)
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV 1
#if 0
#define CONFIG_SYS_MMC_ENV_PART 2
#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
#endif
#undef CONFIG_SPL_ENV_SUPPORT
#undef CONFIG_SPL_NAND_SUPPORT
#undef CONFIG_SPL_ONENAND_SUPPORT
/* We need to disable SPI to not confuse the eeprom env driver */
#undef CONFIG_SPI
#undef CONFIG_SPI_BOOT
#undef CONFIG_SPL_OS_BOOT
#define CONFIG_SPL_POWER_SUPPORT /* TODO: Check */
#define CONFIG_SPL_YMODEM_SUPPORT
#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/am33xx/u-boot-spl.lds"
#define CONFIG_SUPPORT_EMMC_BOOT
/* To support eMMC booting */
#define CONFIG_STORAGE_EMMC
#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
#ifdef CONFIG_USB_MUSB_HOST
#define CONFIG_USB_STORAGE
#endif
#ifdef CONFIG_USB_MUSB_GADGET
/* Removing USB gadget and can be enabled adter adding support usb DM */
#ifndef CONFIG_DM_ETH
#define CONFIG_USB_ETHER
#define CONFIG_USB_ETH_RNDIS
#define CONFIG_USBNET_HOST_ADDR "de:ad:be:af:00:00"
#endif /* CONFIG_DM_ETH */
#endif /* CONFIG_USB_MUSB_GADGET */
/*
* Disable MMC DM for SPL build and can be re-enabled after adding
* DM support in SPL
*/
#ifdef CONFIG_SPL_BUILD
#undef CONFIG_DM_MMC
#undef CONFIG_TIMER
#endif
#if defined(CONFIG_SPL_BUILD)
/* Remove other SPL modes. */
#undef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_ENV_IS_NOWHERE
#undef CONFIG_PARTITION_UUIDS
#undef CONFIG_EFI_PARTITION
#endif
/* Network. */
#define CONFIG_PHY_GIGE
#define CONFIG_PHYLIB
#define CONFIG_PHY_SMSC
#ifdef CONFIG_DRIVER_TI_CPSW
#define CONFIG_CLOCK_SYNTHESIZER
#define CLK_SYNTHESIZER_I2C_ADDR 0x65
#endif
#define CONFIG_SYS_MEMTEST_START 0x80000000
#define CONFIG_SYS_MEMTEST_END 0x87900000
#define CONFIG_NM_LOGIN
#define CONFIG_CRYPT
#if 0
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_DA9063 /* TODO: Provide driver */
#endif
#define CONFIG_CMD_PXE
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_JTAG_MARKER_SPL 0x402FFF00
#define CONFIG_JTAG_MARKER_UBOOT 0x807FFF00
/* SPL command is not needed */
#undef CONFIG_CMD_SPL
/* Never enable ISO it is broken and can lead to a crash */
#undef CONFIG_ISO_PARTITION
#endif /* ! __CONFIG_AM335X_NRHW22_H */