ADD: [nrhw24] add support for new platform

BugzID: 57900
2019-08-16 07:46:02 +02:00 · 2019-08-16 07:46:02 +02:00 · bd9c1481e7
parent e0b32a6409
commit bd9c1481e7
18 changed files with 2463 additions and 13 deletions
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@ -391,20 +391,28 @@ config TARGET_AM335X_NETBIRD_V2
 	select DM_GPIO

 config TARGET_AM335X_NRHW20
-        bool "Support am335x_nrhw20"
-        select CPU_V7
-        select SUPPORT_SPL
-        select DM
-        select DM_SERIAL
-        select DM_GPIO
+	bool "Support am335x_nrhw20"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO

 config TARGET_AM335X_NRHW22
-        bool "Support am335x_nrhw22"
-        select CPU_V7
-        select SUPPORT_SPL
-        select DM
-        select DM_SERIAL
-        select DM_GPIO
+	bool "Support am335x_nrhw22"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO
+
+config TARGET_AM335X_NRHW24
+	bool "Support am335x_nrhw24"
+	select CPU_V7
+	select SUPPORT_SPL
+	select DM
+	select DM_SERIAL
+	select DM_GPIO

 config TARGET_AM335X_SL50
 	bool "Support am335x_sl50"
@ -906,6 +914,7 @@ source "board/nm/netbird/Kconfig"
 source "board/nm/netbird_v2/Kconfig"
 source "board/nm/nrhw20/Kconfig"
 source "board/nm/nrhw22/Kconfig"
+source "board/nm/nrhw24/Kconfig"
 source "board/olimex/mx23_olinuxino/Kconfig"
 source "board/phytec/pcm051/Kconfig"
 source "board/phytec/pcm052/Kconfig"
--- a/board/nm/common/da9063.h
+++ b/board/nm/common/da9063.h
@ -17,14 +17,32 @@

 #define PMIC_REG_STATUS_A	0x01	/* Status of ON_KEY, WAKE, COMP1V2, DVC */
 #define PMIC_REG_FAULT_LOG	0x05
+#define PMIC_REG_CONTROL_D      0x11    /* Control register for blink/watchdog */
+#define PMIC_REG_GPIO14_15      0x1C    /* Configuration of GPIO14/15 (mode, wake) */
 #define PMIC_REG_GPIO_MODE0_7	0x1D	/* Control register for GPIOs 0..7 */
 #define PMIC_REG_GPIO_MODE8_15	0x1E	/* Control register for GPIOs 8..15 */

-#define PMIC_REG_BBAT_CONT	0xC5	/* Control register for backup battery */
+#define PMIC_REG_BCORE1_CONT	0x21	/* Control register of BCORE1 */
+#define PMIC_REG_BCORE2_CONT	0x20	/* Control register of BCORE2 */
+#define PMIC_REG_BPERI_CONT	0x25	/* Control register of BPERI */
+#define PMIC_REG_BIO_CONT	0x24	/* Control register of BIO */
+#define PMIC_REG_BMEM_CONT	0x23	/* Control register of BMEM */
+
+#define PMIC_REG_LDO3_CONT	0x28	/* Control register of LDO3 */
+#define PMIC_REG_LDO6_CONT	0x2B	/* Control register of LDO6 */
+#define PMIC_REG_LDO7_CONT	0x2C	/* Control register of LDO7 */
+#define PMIC_REG_LDO11_CONT	0x30	/* Control register of LDO11 */
+
+#define PMIC_LDOx_EN_MASK	0x01
+#define PMIC_LDOx_CONF_MASK	0x80
+
+#define PMIC_REG_ID_4_3		0x84

 #define PMIC_REG_BUCK_ILIM_A	0x9A
 #define PMIC_REG_BUCK_ILIM_B	0x9B
 #define PMIC_REG_BUCK_ILIM_C	0x9C
+#define PMIC_REG_BBAT_CONT	0xC5	/* Control register for backup battery */
+

 #define PMIC_REG_BCORE2_CONF	0x9D
 #define PMIC_REG_BCORE1_CONF	0x9E
@ -32,6 +50,15 @@
 #define PMIC_REG_BMEM_CONF	0xA1
 #define PMIC_REG_BPERI_CONF	0xA2

+#define PMIC_REG_CONFIG_E	0x10A
+#define PMIC_REG_CONFIG_G	0x10C
+#define PMIC_REG_CONFIG_L	0x111
+
+#define PMIC_REG_TRIM_CLDR	0x120	/* Calendar Trim register, 2's complement, 1.9ppm per bit */
+
+#define PMIC_REG_CONFIG_ID	0x184	/* OTP Config ID <ver.rev> */
+
+
 extern void da9063_init(int i2c_bus);
 extern int da9063_get_reg(int reg, u8* val);
 extern int da9063_set_reg(int reg, u8 val);
--- a/board/nm/nrhw24/Kconfig
+++ b/board/nm/nrhw24/Kconfig
@ -0,0 +1,26 @@
+if TARGET_AM335X_NRHW24
+
+config SYS_BOARD
+        default "nrhw24"
+
+config SYS_VENDOR
+        default "nm"
+
+config SYS_SOC
+        default "am33xx"
+
+config SYS_CONFIG_NAME
+        default "am335x_nrhw24"
+
+config CONS_INDEX
+        int "UART used for console"
+        range 1 6
+        default 2
+        help
+          The AM335x SoC has a total of 6 UARTs (UART0 to UART5 as referenced
+          in documentation, etc) available to it.  Depending on your specific
+          board you may want something other than UART0 as for example the IDK
+          uses UART3 so enter 4 here.
+
+endif
+
--- a/board/nm/nrhw24/Makefile
+++ b/board/nm/nrhw24/Makefile
@ -0,0 +1,13 @@
+#
+# Makefile
+#
+# Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+ifeq ($(CONFIG_SKIP_LOWLEVEL_INIT),)
+obj-y	:= mux.o
+endif
+
+obj-y	+= board.o ../common/bdparser.o ../common/board_descriptor.o shield.o shield_can.o shield_comio.o fileaccess.o ../common/da9063.o
--- a/board/nm/nrhw24/board.c
+++ b/board/nm/nrhw24/board.c
--- a/board/nm/nrhw24/board.h
+++ b/board/nm/nrhw24/board.h
@ -0,0 +1,35 @@
+/*
+ * board.h
+ *
+ * TI AM335x boards information header
+ *
+ * Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+/*
+ * We have three pin mux functions that must exist.  We must be able to enable
+ * uart0, for initial output and i2c2 to read the main EEPROM.  We then have a
+ * main pinmux function that can be overridden to enable all other pinmux that
+ * is required on the board.
+ */
+void enable_uart0_pin_mux(void);
+void disable_uart0_pin_mux(void);
+void enable_uart1_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart5_pin_mux(void);
+/*
+void enable_uart2_pin_mux(void);
+void enable_uart3_pin_mux(void);
+void enable_uart4_pin_mux(void);
+void enable_uart5_pin_mux(void);
+*/
+void enable_i2c0_pin_mux(void);
+void enable_i2c2_pin_mux(void);
+void enable_board_pin_mux(void);
+
+#define GPIO_TO_PIN(bank, gpio)		(32 * (bank) + (gpio))
+#endif
--- a/board/nm/nrhw24/fileaccess.c
+++ b/board/nm/nrhw24/fileaccess.c
@ -0,0 +1,40 @@
+#include <common.h>
+#include <fs.h>
+
+#define BLOCK_DEVICE "mmc"
+#define OVERLAY_PART "1:3"
+
+int read_file(const char* filename, char *buf, int size)
+{
+	loff_t filesize = 0;
+	loff_t len;
+	int ret;
+
+	if (fs_set_blk_dev(BLOCK_DEVICE, OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+	/* Read at most file size bytes */
+	if (fs_size(filename, &filesize)) {
+		return -1;
+	}
+
+	if (filesize < size)
+		size = filesize;
+
+	/* For very unclear reasons the block device needs to be set again after the call to fs_size() */
+	if (fs_set_blk_dev(BLOCK_DEVICE, OVERLAY_PART, FS_TYPE_EXT) != 0) {
+		puts("Error, can not set blk device\n");
+		return -1;
+	}
+
+	if ((ret = fs_read(filename, (ulong)buf, 0, size, &len))) {
+		printf("Can't read file %s (size %d, len %lld, ret %d)\n", filename, size, len, ret);
+		return -1;
+	}
+
+	buf[len] = 0;
+
+	return len;
+}
--- a/board/nm/nrhw24/fileaccess.h
+++ b/board/nm/nrhw24/fileaccess.h
@ -0,0 +1,14 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/fileaccess.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Tue 06 Jun 2017 02:02:33 PM CEST \n
+ * 	Last Update:	Tue 06 Jun 2017 02:02:33 PM CEST
+ */
+#ifndef FILEACCESS_H
+#define FILEACCESS_H
+
+void fs_set_console(void);
+int read_file(const char* filename, char *buf, int size);
+
+#endif // FILEACCESS_H
--- a/board/nm/nrhw24/mux.c
+++ b/board/nm/nrhw24/mux.c
@ -0,0 +1,241 @@
+/*
+ * mux.c
+ *
+ * Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <common.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/arch/hardware.h>
+#include <asm/arch/mux.h>
+#include <asm/io.h>
+#include "board.h"
+
+static struct module_pin_mux gpio_pin_mux[] = {
+	/*
+	* GPIO0_2: RST_GNSS~
+	* GPIO0_5: EXTINT_GNSS
+	* GPIO0_6: TIMEPULSE_GNSS
+	* GPIO0_16: RST_PHY~
+	* GPIO0_17: PMIC FAULT
+	* GPIO0_27: RST_SHIELD~
+	*
+	* GPIO1_20: BT_EN
+	* GPIO1_21: GSM_PWR_EN
+	* GPIO1_25: RST_GSM
+	* GPIO1_26: WLAN_EN
+	* GPIO1_27: WLAN_IRQ
+	*
+	* GPIO3_17: SIM_SEL
+	*/
+
+	/* Bank 0 */
+	{OFFSET(spi0_sclk), (MODE(7) | PULLUDDIS)},			/* (A17) gpio0[2] */  /* RST_GNSS */
+	{OFFSET(spi0_cs0), (MODE(7) | PULLUDEN | PULLDOWN_EN)},		/* (A16) gpio0[5] */  /* EXTINT_GNSS */
+	{OFFSET(spi0_cs1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},/* (C15) gpio0[6] */  /* TIMEPULSE_GNSS */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (C18) gpio0[7] */  /* IO_SHIELD */
+	{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)},			/* (J18) gpio0[16] */  /* RST_PHY~ */
+	{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)},			/* (U12) gpio0[27] */  /* RST_SHIELD~ */
+
+	/* Bank 1 */
+	{OFFSET(gpmc_a4), (MODE(7) | PULLUDDIS)},			/* (R14) gpio1[20] */  /* BT_EN */
+	{OFFSET(gpmc_a5), (MODE(7) | PULLUDDIS)},			/* (V15) gpio1[21] */  /* GSM_PWR_EN */
+	{OFFSET(gpmc_a9),  (MODE(7) | PULLUDDIS)},			/* (U16) gpio1[25] */  /* RST_GSM */
+	{OFFSET(gpmc_a10), (MODE(7) | PULLUDDIS)},			/* (T16) gpio1[26] */  /* WLAN_EN */
+	{OFFSET(gpmc_a11),  (MODE(7) | PULLUDDIS | RXACTIVE)},		/* (V17) gpio1[27] */  /* WLAN_IRQ */
+
+	/* TODO: What about all the unused GPMC pins ? */
+
+	/* Bank 2 */
+#if 0
+	/* TODO: What is this meant for? */
+	{OFFSET(lcd_data3), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (R4) gpio2[9] */  /* SYSBOOT_3 */
+	{OFFSET(lcd_data4), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (T1) gpio2[10] */  /* SYSBOOT_4 */
+
+	/* TODO: Check other unued pins from sysboot block */
+	/* Ensure PU/PD does not work against external signal */
+	/*
+	 * SYSBOOT 0,1,5,12,13 = Low
+	 * SYSBOOT 2 = High
+	 */
+#endif
+
+	/* Bank 3 */
+	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDEN | PULLDOWN_EN)},	/* (C12) gpio3[17] */  /* SIM_SEL */
+	{-1},
+};
+
+/* I2C0 PMIC */
+static struct module_pin_mux i2c0_pin_mux[] = {
+	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C17) I2C0_SDA */
+	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (C16) I2C0_SCL */
+	{-1},
+};
+
+/* I2C2 System */
+static struct module_pin_mux i2c2_pin_mux[] = {
+	{OFFSET(uart1_rtsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D17) I2C2_SCL */
+	{OFFSET(uart1_ctsn), (MODE(3) | RXACTIVE | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D18) I2C2_SDA */
+	{-1},
+};
+
+/* RMII1: Ethernet */
+static struct module_pin_mux rmii1_pin_mux[] = {
+	/* RMII */
+	{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE},			/* (H17) rmii1_crs */
+	{OFFSET(mii1_rxerr), MODE(7) | PULLUDEN | PULLDOWN_EN | RXACTIVE},	/* (J15) gpio */
+	{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE},			/* (M16) rmii1_rxd0 */
+	{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE},			/* (L15) rmii1_rxd1 */
+	{OFFSET(mii1_txen), MODE(1) | PULLUDDIS},				/* (J16) rmii1_txen */
+	{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS},				/* (K17) rmii1_txd0 */
+	{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS},				/* (K16) rmii1_txd1 */
+	{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE},			/* (H18) rmii1_refclk */
+
+	/* SMI */
+	{OFFSET(mdio_clk), MODE(0) | PULLUDDIS},				/* (M18) mdio_clk */
+	{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE},		/* (M17) mdio_data */
+
+	/* 25MHz Clock Output */
+	{OFFSET(xdma_event_intr0), MODE(3)},					/* (A15) clkout1 (25 MHz clk for Switch) */
+	{-1},
+};
+
+/* MMC0: WiFi */
+static struct module_pin_mux mmc0_sdio_pin_mux[] = {
+	{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_CLK */
+	{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_CMD */
+	{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_DAT0 */
+	{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_DAT1 */
+	{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_DAT2 */
+	{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC0_DAT3 */
+	{-1},
+};
+
+/* MMC1: eMMC */
+static struct module_pin_mux mmc1_emmc_pin_mux[] = {
+	{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_CLK */
+	{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_CMD */
+	{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT0 */
+	{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT1 */
+	{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT2 */
+	{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT3 */
+	{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT4 */
+	{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT5 */
+	{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT6 */
+	{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* MMC1_DAT7 */
+	{-1},
+};
+
+/* USB_DRVBUS not used -> configure as GPIO */
+static struct module_pin_mux usb_pin_mux[] = {
+	{OFFSET(usb0_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F16) USB0_DRVVBUS */
+	{OFFSET(usb1_drvvbus), (MODE(7) | PULLUDDIS)},				/* (F15) USB1_DRVVBUS */
+	{-1},
+};
+
+/* UART0: RS232/RS485 shield mode */
+static struct module_pin_mux uart0_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (E15) UART0_RXD */
+	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (E16) UART0_TXD */
+	{-1},
+};
+
+/* UART0: Shield I/F (UART, CAN) */
+/* Leave UART0 unconfigured because we want to configure it as needed by Linux (can/spi/uart/etc) */
+/* Mode 7 = GPIO */
+static struct module_pin_mux uart0_disabled_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E15) GPIO1_10 */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E16) GPIO1_11 */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDDIS | RXACTIVE)},			/* (E18) GPIO1_8 */
+	{OFFSET(uart0_rtsn), (MODE(7) | PULLUDEN | PULLUP_EN)},			/* (E17) GPIO1_9 */
+	{-1},
+};
+
+/* UART1: User (Debug/Console) */
+static struct module_pin_mux uart1_pin_mux[] = {
+	{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (D16) uart1_rxd */
+	{OFFSET(uart1_txd), (MODE(0) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (D15) uart1_txd */
+	{-1},
+};
+
+/* UART3: GNSS */
+static struct module_pin_mux uart3_pin_mux[] = {
+	{OFFSET(mii1_rxd3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (L17) UART3_RXD */
+	{OFFSET(mii1_rxd2), (MODE(1) | PULLUDEN | PULLUP_EN | SLEWCTRL)},	/* (L16) UART3_TXD */
+	{-1},
+};
+
+/* UART5: Highspeed UART for Bluetooth (no SLEWCTRL) */
+static struct module_pin_mux uart5_pin_mux[] = {
+	{OFFSET(lcd_data9), (MODE(4) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (U2) UART5_RXD */
+	{OFFSET(lcd_data8), (MODE(4) | PULLUDEN | PULLUP_EN)},			/* (U1) UART5_TXD */
+	{OFFSET(lcd_data14), (MODE(6) | PULLUDEN | PULLUP_EN | RXACTIVE)},	/* (V4) uart5_ctsn */
+	{OFFSET(lcd_data15), (MODE(6) | PULLUDEN | PULLUP_EN)},			/* (T5) uart5_rtsn */
+	{-1},
+};
+
+static struct module_pin_mux unused_pin_mux[] = {
+	/* SYSBOOT6, 7, 10, 11: Not used pulldown active, receiver disabled */
+	{OFFSET(lcd_data6), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data7), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data10), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+	{OFFSET(lcd_data11), (MODE(7) | PULLUDEN | PULLDOWN_EN)},
+
+	/* TODO: GPMCA1..3, A6..8 */
+
+	{-1},
+};
+
+
+void enable_board_pin_mux(void)
+{
+	configure_module_pin_mux(gpio_pin_mux);
+
+	configure_module_pin_mux(rmii1_pin_mux);
+	configure_module_pin_mux(mmc0_sdio_pin_mux);
+	configure_module_pin_mux(mmc1_emmc_pin_mux);
+	configure_module_pin_mux(usb_pin_mux);
+
+	configure_module_pin_mux(i2c0_pin_mux);
+	configure_module_pin_mux(i2c2_pin_mux);
+
+	configure_module_pin_mux(uart3_pin_mux);
+	configure_module_pin_mux(uart5_pin_mux);
+
+	configure_module_pin_mux(unused_pin_mux);
+}
+
+void enable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_pin_mux);
+}
+
+void disable_uart0_pin_mux(void)
+{
+	configure_module_pin_mux(uart0_disabled_pin_mux);
+}
+
+void enable_uart1_pin_mux(void)
+{
+	configure_module_pin_mux(uart1_pin_mux);
+}
+
+void enable_uart3_pin_mux(void)
+{
+	configure_module_pin_mux(uart3_pin_mux);
+}
+
+void enable_uart5_pin_mux(void)
+{
+	configure_module_pin_mux(uart5_pin_mux);
+}
--- a/board/nm/nrhw24/shield.c
+++ b/board/nm/nrhw24/shield.c
@ -0,0 +1,73 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define MAX_SHIELDS 16
+
+static struct shield_t *shields[MAX_SHIELDS];
+static int shield_count = 0;
+
+/* Perhaps this function shouldn't leave in shields.c? */
+int shield_gpio_request_as_input(unsigned int gpio, const char *label)
+{
+	int ret;
+
+ 	ret = gpio_request(gpio, label);
+	if ((ret < 0)) {
+		printf("Could not request shield slot %s gpio\n", label);
+		return -1;
+	}
+
+	ret = gpio_direction_input(gpio);
+	if ((ret < 0)) {
+		printf("Could not configure shield slot %s gpio as input\n", label);
+		return -1;
+	}
+
+	return 0;
+}
+
+void shield_register(struct shield_t *shield)
+{
+	if (shield_count >= MAX_SHIELDS) {
+		printf("Max shield count reached (%d), please increment MAX_SHIELDS\n", MAX_SHIELDS);
+		return;
+	}
+	shields[shield_count++] = shield;
+}
+
+int shield_set_mode(const char* shield_type, int argc, char * const argv[])
+{
+	int i;
+
+	for (i = 0; i < shield_count; i++) {
+		if (strcmp(shield_type, shields[i]->name) == 0) {
+			return shields[i]->setmode(argv, argc);
+		}
+	}
+	printf("## Error: No %s shield installed\n", shield_type);
+	/* Do not return error, to not show usage (request by rs) */
+	return 0;
+}
+
+static int do_shieldmode(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+	if (argc < 2) {
+		return -1;
+	}
+
+	return shield_set_mode(argv[1], argc - 2, &argv[2]);
+}
+
+U_BOOT_CMD(
+	shield,	6,	1,	do_shieldmode,
+	"Set the shield mode",
+	"dualcan termination [on|off] [on|off]\n"
+	"shield comio mode [rs232|rs485] termination [on|off]\n"
+);
+
--- a/board/nm/nrhw24/shield.h
+++ b/board/nm/nrhw24/shield.h
@ -0,0 +1,21 @@
+/**@file	/home/eichenberger/projects/nbhw16/u-boot/board/nm/netbird_v2/shield.h
+ * @author	eichenberger
+ * @version	704
+ * @date
+ * 	Created:	Wed 31 May 2017 02:56:16 PM CEST \n
+ * 	Last Update:	Wed 31 May 2017 02:56:16 PM CEST
+ */
+#ifndef SHIELD_H
+#define SHIELD_H
+
+struct shield_t{
+    char name[64];
+    int (*setmode)(char * const argv[], int argc);
+};
+
+int shield_setmode(int mode);
+void shield_register(struct shield_t *shield);
+
+int shield_gpio_request_as_input(unsigned int gpio, const char *label);
+
+#endif // SHIELD_H
--- a/board/nm/nrhw24/shield_can.c
+++ b/board/nm/nrhw24/shield_can.c
@ -0,0 +1,195 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+#define CAN_PORTS			2
+
+#define NETBIRD_GPIO_RST_SHIELD_N	GPIO_TO_PIN(0, 27)
+#define NETBIRD_GPIO_LATCH		GPIO_TO_PIN(0, 7)
+#define NETBIRD_GPIO_MODE_0		GPIO_TO_PIN(1, 8)
+#define NETBIRD_GPIO_MODE_1		GPIO_TO_PIN(1, 10)
+
+
+static int shield_slot_initialized = 0;
+
+
+static struct module_pin_mux can_shield_netbird_pin_mux_config[] = {
+	/* Leave UART0 unconfigured because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (E18) gpio1_8 */ /* Mode 0 */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (E15) gpio1_10 */ /* Mode 1 */
+	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | PULLUP_EN)},	/* (C18) eCAP0_in_PWM0_out.gpio0[7] */ /* Latch EN */
+	{-1},
+};
+
+static struct module_pin_mux can_shield_netbird_pin_mux_final[] = {
+	{OFFSET(uart0_txd), (MODE(2) | PULLUDDIS | RXACTIVE)},		/* (E16) dcan0_rx */
+	{OFFSET(uart0_rxd), (MODE(2) | PULLUDEN | PULLUP_EN)},		/* (E15) dcan0_tx */
+	{OFFSET(uart0_rtsn), (MODE(2) | PULLUDDIS | RXACTIVE)},		/* (E17) dcan1_rx */
+	{OFFSET(uart0_ctsn), (MODE(2) | PULLUDEN | PULLUP_EN)},		/* (E18) dcan1_tx */
+	{-1},
+};
+
+
+static int request_gpios(void)
+{
+	int ret;
+
+	debug("Shield configure gpios\n");
+ 	ret = shield_gpio_request_as_input(NETBIRD_GPIO_RST_SHIELD_N, "shield-rst");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_LATCH, "shield-load");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_0, "shield-mode0");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_1, "shield-mode1");
+	if ((ret < 0))
+		return -1;
+
+	shield_slot_initialized = 1;
+	return 0;
+}
+
+static int configure_shieldmode(int mode)
+{
+	int ret;
+
+	if (mode < 0 || mode > 3) {
+		debug("Invalid shield mode %d\n", mode);
+		return -1;
+	}
+
+	debug("Shield type dualcan\n");
+	debug ("Set shield mode to %d\n", mode);
+
+	if (!shield_slot_initialized) {
+		if (request_gpios()) {
+			puts("Failed to request gpios\n");
+			return -1;
+		}
+	}
+
+	debug("Configure shield pin muxing for configuration\n");
+	configure_module_pin_mux(can_shield_netbird_pin_mux_config);
+
+	debug("Make sure shield module is in reset\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_RST_SHIELD_N, 0);
+	if (ret < 0) {
+		puts("Can not set shield-rst as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set latch to high\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_LATCH, 1);
+	if (ret < 0) {
+		puts("Can not set shield-load as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Write mode to GPIOs\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_0, mode & 0x01);
+	if (ret < 0) {
+		puts("Can not set shield-mode0 as output\n");
+		return -1;
+	}
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_1, mode & 0x02);
+	if (ret < 0) {
+		puts("Can not set shield-mode1 as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set latch to low\n");
+	gpio_set_value(NETBIRD_GPIO_LATCH, 0);
+	udelay(10);
+
+	debug("Set mode0 and mode1 to highz again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_0);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode0 gpio as input\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_1);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode1 gpio as input\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Take shield out of reset\n");
+	gpio_set_value(NETBIRD_GPIO_RST_SHIELD_N, 1);
+	udelay(10);
+
+	debug("Set final can shield muxing\n");
+	configure_module_pin_mux(can_shield_netbird_pin_mux_final);
+
+	return 0;
+
+}
+
+static int get_termination(const char* termination)
+{
+	if (strcmp("on", termination) == 0) {
+		return 1;
+	}
+	else if (strcmp("off", termination) == 0)  {
+		return 0;
+	}
+
+	debug ("Invalid termination mode %s (falling back to off)", termination);
+	return -1;
+}
+
+static int get_mode_from_args(char * const argv[], int argc)
+{
+	int terminations[CAN_PORTS];
+	int i;
+
+	assert(argc == (CAN_PORTS + 1));
+
+	if (strcmp ("termination", argv[0])) {
+		debug("The only option for dualcan is terminations\n");
+		return -1;
+	}
+
+	for (i = 0; i < CAN_PORTS; i ++) {
+		terminations[i] = get_termination(argv[i + 1]);
+		if (terminations[i] < 0) {
+			return -1;
+		}
+	}
+
+	/* Termination is inverse */
+	/* TODO: Double check */
+	return (!terminations[0] << 0) | (!terminations[1] << 1);
+}
+
+static int set_shieldmode(char * const argv[], int argc)
+{
+	if (argc != 3) {
+		debug("Too few arguments for dualcan\n");
+		return -1;
+	}
+
+	return configure_shieldmode(get_mode_from_args(argv, argc));
+}
+
+/* TODO: Static ? */
+struct shield_t can_shield = {
+	"dualcan", set_shieldmode
+};
+
+void can_shield_init(void)
+{
+	shield_register(&can_shield);
+}
--- a/board/nm/nrhw24/shield_can.h
+++ b/board/nm/nrhw24/shield_can.h
@ -0,0 +1,9 @@
+#ifndef SHIELD_CAN_H
+#define SHIELD_CAN_H
+
+int shield_can_init(void);
+int shield_can_setmode(int mode);
+
+void can_shield_init(void);
+
+#endif // SHIELD_CAN_H
--- a/board/nm/nrhw24/shield_comio.c
+++ b/board/nm/nrhw24/shield_comio.c
@ -0,0 +1,252 @@
+#undef DEBUG
+
+#include <common.h>
+#include <asm/gpio.h>
+#include <asm/arch/mux.h>
+
+#include "shield.h"
+#include "board.h"
+
+/* TODO: Double Check */
+#define NETBIRD_GPIO_RST_SHIELD_N	GPIO_TO_PIN(0, 27)
+#define NETBIRD_GPIO_LOAD		GPIO_TO_PIN(1, 9)
+/* TODO: Who configures UART0_RTSn, GPIO1_9 ? */
+#define NETBIRD_GPIO_MODE_0		GPIO_TO_PIN(1, 11)
+#define NETBIRD_GPIO_MODE_1		GPIO_TO_PIN(1, 10)
+
+static int shield_slot_initialized = 0;
+
+
+/* TODO: Naming -> config, final */
+static struct module_pin_mux shield_gpio_netbird_pin_mux[] = {
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS)},			/* (E15) gpio1_10 */ /* Mode 0 */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDEN | PULLUP_EN)},		/* (E16) gpio1_11 */ /* Mode 1 */
+	{-1},
+};
+
+static struct module_pin_mux shield_gpio_safe_netbird_pin_mux[] = {
+	/* Leave UART0 unconfigured (GPIO) because we want to configure it as needed by linux (can/spi/uart/etc) */
+	{OFFSET(uart0_rxd), (MODE(7) | PULLUDDIS | RXACTIVE)},		/* (E15) gpio1_10 */ /* Mode 0 */
+	{OFFSET(uart0_txd), (MODE(7) | PULLUDDIS | RXACTIVE)},		/* (E16) gpio1_11 */ /* Mode 1 */
+	{-1},
+};
+
+
+static int request_gpios(void)
+{
+	int ret;
+
+	debug("Extension slot init\n");
+ 	ret = shield_gpio_request_as_input(NETBIRD_GPIO_RST_SHIELD_N, "shield-rst");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_LOAD, "shield-load");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_0, "shield-mode0");
+	if ((ret < 0))
+		return -1;
+	ret = shield_gpio_request_as_input(NETBIRD_GPIO_MODE_1, "shield-mode1");
+	if ((ret < 0))
+		return -1;
+
+	shield_slot_initialized = 1;
+	return 0;
+}
+
+static int configure_shieldmode(int mode)
+{
+	int ret;
+
+	if (mode < 0 || mode > 3) {
+		debug ("Invalid shield mode %d\n", mode);
+		return -1;
+	}
+
+	debug("Shield type comio\n");
+	debug ("Set shield mode to %d\n", mode);
+
+	if (!shield_slot_initialized) {
+		if (request_gpios()) {
+			puts("Failed to request gpios\n");
+			return -1;
+		}
+	}
+
+	debug("Make sure shield module is in reset\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_RST_SHIELD_N, 0);
+	if (ret < 0) {
+		puts("Can not set shield-rst as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Enable gpio pull-ups\n");
+	configure_module_pin_mux(shield_gpio_netbird_pin_mux);
+
+	debug("Set load to low\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_LOAD, 0);
+	if (ret < 0) {
+		puts("Can not set shield-load as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Write mode to GPIOs\n");
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_0, mode & 0x01);
+	if (ret < 0) {
+		puts("Can not set shield-mode0 as output\n");
+		return -1;
+	}
+	ret = gpio_direction_output(NETBIRD_GPIO_MODE_1, mode & 0x02);
+	if (ret < 0) {
+		puts("Can not set shield-mode1 as output\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Set load to high\n");
+	gpio_set_value(NETBIRD_GPIO_LOAD, 1);
+	udelay(10);
+
+	debug("Set mode0 and mode1 to highz again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_0);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode0 gpio as input\n");
+		return -1;
+	}
+
+	ret = gpio_direction_input(NETBIRD_GPIO_MODE_1);
+	if ((ret < 0)) {
+		puts("Could not configure shield slot mode1 gpio as input\n");
+		return -1;
+	}
+	udelay(10);
+
+	debug("Disable pullups on shield gpios\n");
+	configure_module_pin_mux(shield_gpio_safe_netbird_pin_mux);
+	udelay(10);
+
+	debug("Take shield out of reset\n");
+	gpio_set_value(NETBIRD_GPIO_RST_SHIELD_N, 1);
+	udelay(10);
+
+	debug("Set gpio load as input again\n");
+	ret = gpio_direction_input(NETBIRD_GPIO_LOAD);
+	if (ret < 0) {
+		puts("Can not configure shield slot load as input");
+		return -1;
+	}
+
+	return 0;
+}
+
+enum mode_nr {
+	RS232,
+	RS485,
+	UNKNOWN
+};
+
+struct mode {
+	enum mode_nr nr;
+	const char* name;
+	int argc;
+};
+
+struct mode modes[] = {
+	{ RS232, "rs232", 0 },
+	{ RS485, "rs485", 2 }
+};
+
+static const struct mode *get_mode(const char *mode)
+{
+	int i;
+	for (i = 0; i < ARRAY_SIZE(modes); i++) {
+		if (strcmp(modes[i].name, mode) == 0) {
+			return &modes[i];
+		}
+	}
+	return NULL;
+}
+
+static int get_termination(const char* termination)
+{
+	if (strcmp("on", termination) == 0) {
+		return 1;
+	}
+	else if (strcmp("off", termination) == 0)  {
+		return 0;
+	}
+
+	debug ("Invalid termination mode %s (falling back to off)", termination);
+	return -1;
+}
+
+static int get_mode_from_args(char * const argv[], int argc)
+{
+	int termination = 0;
+	int rs232 = 0;
+	const struct mode *selected_mode;
+
+	assert(argc >= 2);
+
+	if (strcmp ("mode", argv[0])) {
+		debug("Invalid arguments (see help)\n");
+		return -1;
+	}
+
+	selected_mode = get_mode(argv[1]);
+	if (selected_mode == NULL) {
+		debug("Mode %s not supported\n", argv[1]);
+		return -1;
+	}
+
+	debug ("Mode %s, index %d, argc %d\n", selected_mode->name,
+			selected_mode->nr, selected_mode->argc);
+
+	if (selected_mode->argc != argc - 2) {
+		debug("Invalid argument count for mode %s (should %d is %d)\n",
+				argv[1],  selected_mode->argc, argc - 2);
+		return -1;
+	}
+
+	if (selected_mode->nr == RS485) {
+		if (strcmp("termination", argv[2])) {
+			debug("Invalid arguments, do not configure termination\n");
+			return -1;
+		}
+
+		termination = get_termination(argv[3]);
+		if (termination < 0) {
+			debug("Invalid termination %s\n", argv[3]);
+			return -1;
+		}
+	}
+	else {
+		rs232 = 1;
+	}
+
+	/* Termination is inverse */
+	return (rs232 << 0) | ((!termination) << 1);
+}
+
+int set_shieldmode(char * const argv[], int argc)
+{
+	if (argc < 2) {
+		debug("Too few arguments for comio\n");
+		return -1;
+	}
+
+	/* -1 will make configure_shieldmode to faile and is okay therefore */
+	return configure_shieldmode(get_mode_from_args(argv, argc));
+}
+
+/* TODO: Static ? */
+struct shield_t comio_shield = {
+	"comio", set_shieldmode
+};
+
+void comio_shield_init(void)
+{
+	shield_register(&comio_shield);
+}
--- a/board/nm/nrhw24/shield_comio.h
+++ b/board/nm/nrhw24/shield_comio.h
@ -0,0 +1,6 @@
+#ifndef SHIELD_COMIO_H
+#define SHIELD_COMIO_H
+
+void comio_shield_init(void);
+
+#endif // SHIELD_COMIO_H
--- a/board/nm/nrhw24/u-boot.lds
+++ b/board/nm/nrhw24/u-boot.lds
@ -0,0 +1,158 @@
+/*
+ * Copyright (c) 2004-2008 Texas Instruments
+ *
+ * (C) Copyright 2002
+ * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
+OUTPUT_ARCH(arm)
+ENTRY(_start)
+SECTIONS
+{
+	. = 0x00000000;
+
+	. = ALIGN(4);
+	.text :
+	{
+		*(.__image_copy_start)
+		*(.vectors)
+		CPUDIR/start.o (.text*)
+                board/nm/nrhw24/built-in.o (.text*)
+		*(.text*)
+	}
+
+	. = ALIGN(4);
+	.rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
+
+	. = ALIGN(4);
+	.data : {
+		*(.data*)
+	}
+
+	. = ALIGN(4);
+
+	. = .;
+
+	. = ALIGN(4);
+	.u_boot_list : {
+		KEEP(*(SORT(.u_boot_list*)));
+	}
+
+	. = ALIGN(4);
+
+	.__efi_runtime_start : {
+		*(.__efi_runtime_start)
+	}
+
+	.efi_runtime : {
+		*(efi_runtime_text)
+		*(efi_runtime_data)
+	}
+
+	.__efi_runtime_stop : {
+		*(.__efi_runtime_stop)
+	}
+
+	.efi_runtime_rel_start :
+	{
+		*(.__efi_runtime_rel_start)
+	}
+
+	.efi_runtime_rel : {
+		*(.relefi_runtime_text)
+		*(.relefi_runtime_data)
+	}
+
+	.efi_runtime_rel_stop :
+	{
+		*(.__efi_runtime_rel_stop)
+	}
+
+	. = ALIGN(4);
+
+	.image_copy_end :
+	{
+		*(.__image_copy_end)
+	}
+
+	.rel_dyn_start :
+	{
+		*(.__rel_dyn_start)
+	}
+
+	.rel.dyn : {
+		*(.rel*)
+	}
+
+	.rel_dyn_end :
+	{
+		*(.__rel_dyn_end)
+	}
+
+	.hash : { *(.hash*) }
+
+	.end :
+	{
+		*(.__end)
+	}
+
+	_image_binary_end = .;
+
+	/*
+	 * Deprecated: this MMU section is used by pxa at present but
+	 * should not be used by new boards/CPUs.
+	 */
+	. = ALIGN(4096);
+	.mmutable : {
+		*(.mmutable)
+	}
+
+/*
+ * Compiler-generated __bss_start and __bss_end, see arch/arm/lib/bss.c
+ * __bss_base and __bss_limit are for linker only (overlay ordering)
+ */
+
+	.bss_start __rel_dyn_start (OVERLAY) : {
+		KEEP(*(.__bss_start));
+		__bss_base = .;
+	}
+
+	.bss __bss_base (OVERLAY) : {
+		*(.bss*)
+		 . = ALIGN(4);
+		 __bss_limit = .;
+	}
+
+	.bss_end __bss_limit (OVERLAY) : {
+		KEEP(*(.__bss_end));
+	}
+
+	.dynsym _image_binary_end : { *(.dynsym) }
+	.dynbss : { *(.dynbss) }
+	.dynstr : { *(.dynstr*) }
+	.dynamic : { *(.dynamic*) }
+	.gnu.hash : { *(.gnu.hash) }
+	.plt : { *(.plt*) }
+	.interp : { *(.interp*) }
+	.gnu : { *(.gnu*) }
+	.ARM.exidx : { *(.ARM.exidx*) }
+}
--- a/configs/am335x_nrhw24_defconfig
+++ b/configs/am335x_nrhw24_defconfig
@ -0,0 +1,49 @@
+CONFIG_ARM=y
+CONFIG_TARGET_AM335X_NRHW24=y
+CONFIG_SPL_STACK_R_ADDR=0x82000000
+CONFIG_SPL=y
+CONFIG_SPL_STACK_R=y
+CONFIG_FIT=y
+CONFIG_SYS_EXTRA_OPTIONS="EMMC_BOOT"
+CONFIG_HUSH_PARSER=y
+CONFIG_AUTOBOOT_KEYED=y
+CONFIG_AUTOBOOT_PROMPT="Press s to abort autoboot in %d seconds\n"
+CONFIG_AUTOBOOT_STOP_STR="s"
+CONFIG_CMD_BOOTZ=y
+# CONFIG_CMD_IMLS is not set
+CONFIG_CMD_ASKENV=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_DHCP=y
+CONFIG_CMD_MII=y
+CONFIG_CMD_PING=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+CONFIG_DFU_TFTP=y
+CONFIG_SYS_NS16550=y
+CONFIG_USB=y
+CONFIG_USB_MUSB_HOST=y
+CONFIG_USB_MUSB_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_DOWNLOAD=y
+CONFIG_G_DNL_MANUFACTURER="Texas Instruments"
+CONFIG_G_DNL_VENDOR_NUM=0x0451
+CONFIG_G_DNL_PRODUCT_NUM=0xd022
+CONFIG_OF_LIBFDT=y
+# CONFIG_BOOTP_PXE_CLIENTARCH is not set
+# CONFIG_CMD_PXE is not set
+# CONFIG_CMD_BOOTEFI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_FPGA is not set
+# CONFIG_CMD_FPGA is not set
+# CONFIG_CMD_PMIC is not set
+# CONFIG_EFI_LOADER is not set
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
--- a/include/configs/am335x_nrhw24.h
+++ b/include/configs/am335x_nrhw24.h
@ -0,0 +1,250 @@
+/*
+ * am335x_nrhw24.h
+ *
+ * Copyright (C) 2018 NetModule AG - http://www.netmodule.com/
+ * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_AM335X_NRHW24_H
+#define __CONFIG_AM335X_NRHW24_H
+
+#include <configs/ti_am335x_common.h>
+
+#undef CONFIG_SPL_AM33XX_ENABLE_RTC32K_OSC
+
+#undef CONFIG_HW_WATCHDOG
+#undef CONFIG_OMPAP_WATCHDOG
+#undef CONFIG_SPL_WATCHDOG_SUPPORT
+
+#ifndef CONFIG_SPL_BUILD
+# define CONFIG_TIMESTAMP
+# define CONFIG_LZO
+#endif
+
+#define CONFIG_SYS_BOOTM_LEN		(16 << 20)
+
+#define MACH_TYPE_TIAM335EVM		3589	/* Until the next sync */
+#define CONFIG_MACH_TYPE		MACH_TYPE_TIAM335EVM
+#define CONFIG_BOARD_LATE_INIT
+
+#define CONFIG_PRE_CONSOLE_BUFFER 1
+#define CONFIG_PRE_CON_BUF_ADDR   0x80000000
+#define CONFIG_PRE_CON_BUF_SZ     64*1024
+
+/* Clock Defines */
+#define V_OSCK				0 /* 0 means detect from sysboot1 config */
+#define V_SCLK				(V_OSCK)
+
+#include <config_distro_bootcmd.h>
+
+#define CONFIG_ARP_TIMEOUT		200
+#undef CONFIG_NET_RETRY_COUNT
+#define CONFIG_NET_RETRY_COUNT		5
+#define CONFIG_BOOTP_MAY_FAIL
+
+#ifndef CONFIG_SPL_BUILD
+#define KERNEL_ADDR			"0x80000000"
+#define LOAD_ADDR			"0x83000000"
+#define FDT_ADDR			"0x82000000"
+#define PXE_ADDR			"0x82800000"
+#define FDT_HIGH_ADDR			"0x9f000000"
+#define INIT_RD_ADDR			"0x88000000"
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"kernel_image=kernel.bin\0"	\
+	"fdt_image=openwrt-nrhw24-nb801.dtb\0"\
+	"modeboot=sdboot\0" \
+	"fdt_addr=" FDT_ADDR "\0" \
+	"kernel_addr=" KERNEL_ADDR "\0" \
+	"load_addr=" LOAD_ADDR "\0" \
+	"root_part=1\0" /* Default root partition, overwritten in board file */ \
+	"defaultconsole=ttyS1\0" /* Default output console */ \
+	"add_sd_bootargs=setenv bootargs $bootargs root=/dev/${mmc_dev}p$root_part rootfstype=ext4 " \
+			"console=$defaultconsole,115200 rootwait loglevel=4 ti_cpsw.rx_packet_max=1526\0" \
+	"add_version_bootargs=setenv bootargs $bootargs\0" \
+	"fdt_skip_update=yes\0" \
+	"ethprime=cpsw\0" \
+	"sdbringup=echo Try bringup boot && ext4load mmc 1:$root_part $kernel_addr /boot/zImage && " \
+			"ext4load mmc 1:$root_part $fdt_addr /boot/$fdt_image && setenv bootargs $bootargs rw;\0" \
+	"sdprod=ext4load mmc 1:$root_part $kernel_addr /boot/$kernel_image && " \
+			"ext4load mmc 1:$root_part $fdt_addr /boot/$fdt_image && setenv bootargs $bootargs ro;\0" \
+	"sdboot=if mmc dev 1; then echo Copying Linux from SD to RAM...; "\
+			"if test -e mmc 1:$root_part /boot/$kernel_image; then run sdprod; " \
+			"else run sdbringup; fi; " \
+			/* For v4.19 kernel $mmc_dev should be "mmcblk1" (read from DT), for v3.18 kernel: "mmcblk0". */ \
+			"fdt addr $fdt_addr;if fdt get value mmc_dev /nm_env nm,mmc-dev;then;else setenv mmc_dev mmcblk0;fi;" \
+			"run add_sd_bootargs; run add_version_bootargs; run shieldcmd; " \
+			"bootz $kernel_addr - $fdt_addr; fi\0" \
+	"bootcmd=run sdboot\0" \
+	"ipaddr=192.168.1.1\0" \
+	"serverip=192.168.1.254\0" \
+	"pxefile_addr_r=" PXE_ADDR "\0" \
+	"fdt_addr_r=" FDT_ADDR "\0" \
+	"fdt_high=" FDT_HIGH_ADDR "\0" \
+	"kernel_addr_r=" KERNEL_ADDR "\0" \
+	"ramdisk_addr_r=" LOAD_ADDR "\0" \
+	"initrd_high=" INIT_RD_ADDR "\0" \
+	"bootpretryperiod=1000\0" \
+	"tftptimeout=2000\0" \
+	"tftptimeoutcountmax=5\0" \
+	"bootpretryperiod=2000\0" \
+	"autoload=false\0" \
+	"shieldcmd=\0" \
+	"tftp_recovery=tftpboot $kernel_addr recovery-image; tftpboot $fdt_addr recovery-dtb; " \
+			"setenv bootargs rdinit=/etc/preinit console=$defaultconsole,115200 " \
+			"debug ti_cpsw.rx_packet_max=1526; run shieldcmd; " \
+			"bootz $kernel_addr - $fdt_addr\0" \
+	"pxe_recovery=sleep 3 && dhcp && pxe get && pxe boot\0" \
+	"recovery=run pxe_recovery || setenv ipaddr $ipaddr; setenv serverip $serverip; run tftp_recovery\0" \
+			/* setenv ipaddr and serverip is necessary, because dhclient can destroy the IPs inernally */
+#endif
+
+/* UART Configuration */
+#define CONFIG_SYS_NS16550_COM1			0x44e09000	/* UART0: XModem Boot, Shield */
+#define CONFIG_SYS_NS16550_COM2			0x48022000	/* UART1: Debug UART (Internal) */
+#define CONFIG_SYS_NS16550_COM3			0x48024000	/* Unused */
+#define CONFIG_SYS_NS16550_COM4			0x481A6000	/* GNSS */
+#define CONFIG_SYS_NS16550_COM5			0x481A8000	/* Unused */
+#define CONFIG_SYS_NS16550_COM6			0x481AA000	/* Bluetooth */
+
+#define CONFIG_I2C
+#define CONFIG_I2C_MULTI_BUS
+
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_ADDR              0x50	/* Main EEPROM */
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
+#define CONFIG_SYS_I2C_SPEED                    100000
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   50	/* TODO: Can this be reduced to 20ms */
+
+/* Put Environment in eMMC */
+#define CONFIG_ENV_OFFSET			(512 * 128)	/* @ 512*256 SPL starts */
+#define CONFIG_ENV_SIZE				(4 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV			1
+
+#if 0
+#define CONFIG_SYS_MMC_ENV_PART			2
+#define CONFIG_ENV_OFFSET_REDUND		(CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
+#define CONFIG_SYS_REDUNDAND_ENVIRONMENT
+#endif
+
+
+#undef CONFIG_SPL_ENV_SUPPORT
+#undef CONFIG_SPL_NAND_SUPPORT
+#undef CONFIG_SPL_ONENAND_SUPPORT
+
+/* We need to disable SPI to not confuse the eeprom env driver */
+#undef CONFIG_SPI
+#undef CONFIG_SPI_BOOT
+#undef CONFIG_SPL_OS_BOOT
+
+#define CONFIG_SPL_POWER_SUPPORT	/* TODO: Check */
+#define CONFIG_SPL_YMODEM_SUPPORT
+
+#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/am33xx/u-boot-spl.lds"
+
+#define CONFIG_SUPPORT_EMMC_BOOT
+
+/*
+ * USB configuration.  We enable MUSB support, both for host and for
+ * gadget.  We set USB0 as peripheral and USB1 as host, based on the
+ * board schematic and physical port wired to each.  Then for host we
+ * add mass storage support and for gadget we add both RNDIS ethernet
+ * and DFU.
+ */
+#define CONFIG_USB_MUSB_DSPS
+#define CONFIG_ARCH_MISC_INIT
+#define CONFIG_USB_MUSB_PIO_ONLY
+#define CONFIG_USB_MUSB_DISABLE_BULK_COMBINE_SPLIT
+#define CONFIG_AM335X_USB0
+#define CONFIG_AM335X_USB0_MODE		MUSB_HOST
+
+/* Fastboot */
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_ANDROID_BOOT_IMAGE
+#define CONFIG_FASTBOOT_BUF_ADDR	CONFIG_SYS_LOAD_ADDR
+#define CONFIG_FASTBOOT_BUF_SIZE	0x07000000
+/* TODO: Check */
+
+/* To support eMMC booting */
+#define CONFIG_STORAGE_EMMC
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV   1
+
+#ifdef CONFIG_USB_MUSB_HOST
+#define CONFIG_USB_STORAGE
+#endif
+
+#ifdef CONFIG_USB_MUSB_GADGET
+/* Removing USB gadget and can be enabled adter adding support usb DM */
+#ifndef CONFIG_DM_ETH
+#define CONFIG_USB_ETHER
+#define CONFIG_USB_ETH_RNDIS
+#define CONFIG_USBNET_HOST_ADDR	"de:ad:be:af:00:00"
+#endif /* CONFIG_DM_ETH */
+#endif /* CONFIG_USB_MUSB_GADGET */
+
+
+/*
+ * Disable MMC DM for SPL build and can be re-enabled after adding
+ * DM support in SPL
+ */
+#ifdef CONFIG_SPL_BUILD
+#undef CONFIG_DM_MMC
+#undef CONFIG_TIMER
+#endif
+
+#if defined(CONFIG_SPL_BUILD)
+/* Remove other SPL modes. */
+#undef CONFIG_SPL_NAND_SUPPORT
+#define CONFIG_ENV_IS_NOWHERE
+#undef CONFIG_PARTITION_UUIDS
+#undef CONFIG_EFI_PARTITION
+#endif
+
+/* Network. */
+#define CONFIG_PHY_GIGE
+#define CONFIG_PHYLIB
+#define CONFIG_PHY_SMSC
+
+#ifdef CONFIG_DRIVER_TI_CPSW
+#define CONFIG_CLOCK_SYNTHESIZER
+#define CLK_SYNTHESIZER_I2C_ADDR 0x65
+#endif
+
+#define CONFIG_SYS_MEMTEST_START    0x80000000
+#define CONFIG_SYS_MEMTEST_END      0x87900000
+
+#define CONFIG_NM_LOGIN
+#define CONFIG_CRYPT
+
+#if 0
+#define CONFIG_POWER
+#define CONFIG_POWER_I2C
+#define CONFIG_POWER_DA9063	/* TODO: Provide driver */
+#endif
+
+#define CONFIG_CMD_PXE
+
+#define CONFIG_OF_BOARD_SETUP
+
+#define CONFIG_JTAG_MARKER_SPL		0x402FFF00
+#define CONFIG_JTAG_MARKER_UBOOT	0x807FFF00
+
+/* SPL command is not needed */
+#undef CONFIG_CMD_SPL
+
+/* Never enable ISO it is broken and can lead to a crash */
+#undef CONFIG_ISO_PARTITION
+
+#endif	/* ! __CONFIG_AM335X_NRHW24_H */