From be0f41c2a48d36b4ef60839af5536159624b70e6 Mon Sep 17 00:00:00 2001 From: Dasnavis Sabiya Date: Wed, 5 Jul 2023 12:41:17 +0530 Subject: [PATCH] arm: dts: k3-am69-sk: Add support for OSPI flash AM69 SK has S28HS512T OSPI flash connected to MCU OSPI0. Add ospi flash node required for OSPI boot. Also describe the partition information according to the offsets in the bootloader. Signed-off-by: Dasnavis Sabiya --- arch/arm/dts/k3-am69-r5-sk.dts | 5 ++ arch/arm/dts/k3-am69-sk-u-boot.dtsi | 21 ++++++++ arch/arm/dts/k3-am69-sk.dts | 77 +++++++++++++++++++++++++++++ 3 files changed, 103 insertions(+) diff --git a/arch/arm/dts/k3-am69-r5-sk.dts b/arch/arm/dts/k3-am69-r5-sk.dts index 1ca45a06e8..b9e8036f20 100644 --- a/arch/arm/dts/k3-am69-r5-sk.dts +++ b/arch/arm/dts/k3-am69-r5-sk.dts @@ -165,4 +165,9 @@ ti,sci = <&dm_tifs>; }; +&ospi0 { + reg = <0x0 0x47040000 0x0 0x100>, + <0x0 0x50000000 0x0 0x8000000>; +}; + #include "k3-am69-sk-u-boot.dtsi" diff --git a/arch/arm/dts/k3-am69-sk-u-boot.dtsi b/arch/arm/dts/k3-am69-sk-u-boot.dtsi index 5c512d1e82..c929061b2c 100644 --- a/arch/arm/dts/k3-am69-sk-u-boot.dtsi +++ b/arch/arm/dts/k3-am69-sk-u-boot.dtsi @@ -22,6 +22,7 @@ i2c2 = &mcu_i2c1; i2c3 = &main_i2c0; ethernet0 = &mcu_cpsw_port1; + spi0 = &ospi0; }; }; @@ -162,6 +163,10 @@ }; }; +&mcu_fss0_ospi0_pins_default { + bootph-pre-ram; +}; + &serdes_ln_ctrl { u-boot,mux-autoprobe; }; @@ -170,6 +175,22 @@ u-boot,mux-autoprobe; }; +&fss { + bootph-pre-ram; +}; + +&ospi0 { + bootph-pre-ram; + + flash@0 { + bootph-pre-ram; + + partition@3fc0000 { + bootph-pre-ram; + }; + }; +}; + &main_sdhci0 { bootph-pre-ram; }; diff --git a/arch/arm/dts/k3-am69-sk.dts b/arch/arm/dts/k3-am69-sk.dts index d70963d31e..e915f516fc 100644 --- a/arch/arm/dts/k3-am69-sk.dts +++ b/arch/arm/dts/k3-am69-sk.dts @@ -105,6 +105,24 @@ }; }; +&wkup_pmx0 { + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + >; + }; +}; + &wkup_pmx2 { mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < @@ -228,6 +246,65 @@ }; }; +&ospi0 { + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +}; + &main_sdhci1 { /* SD card */ status = "okay";