Blackfin: add driver for on-chip NAND controller
This is a port of the Linux Blackfin on-chip NFC driver to U-Boot. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
This commit is contained in:
Mike Frysinger
parent
4148e02aba
commit
be9d8c780e
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@ -35,6 +35,7 @@ COBJS-y += nand_ids.o
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COBJS-y += nand_util.o
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endif
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COBJS-$(CONFIG_DRIVER_NAND_BFIN) += bfin_nand.o
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COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o
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COBJS-$(CONFIG_NAND_FSL_UPM) += fsl_upm.o
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COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o
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@ -0,0 +1,385 @@
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/*
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* Driver for Blackfin on-chip NAND controller.
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*
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* Enter bugs at http://blackfin.uclinux.org/
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*
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* Copyright (c) 2007-2008 Analog Devices Inc.
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*
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* Licensed under the GPL-2 or later.
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*/
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/* TODO:
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* - move bit defines into mach-common/bits/nand.h
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* - try and replace all IRQSTAT usage with STAT polling
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* - have software ecc mode use same algo as hw ecc ?
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*/
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#include <common.h>
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#include <asm/io.h>
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#ifdef DEBUG
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# define pr_stamp() printf("%s:%s:%i: here i am\n", __FILE__, __func__, __LINE__)
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#else
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# define pr_stamp()
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#endif
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#include <nand.h>
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#include <asm/blackfin.h>
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/* Bit masks for NFC_CTL */
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#define WR_DLY 0xf /* Write Strobe Delay */
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#define RD_DLY 0xf0 /* Read Strobe Delay */
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#define NWIDTH 0x100 /* NAND Data Width */
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#define PG_SIZE 0x200 /* Page Size */
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/* Bit masks for NFC_STAT */
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#define NBUSY 0x1 /* Not Busy */
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#define WB_FULL 0x2 /* Write Buffer Full */
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#define PG_WR_STAT 0x4 /* Page Write Pending */
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#define PG_RD_STAT 0x8 /* Page Read Pending */
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#define WB_EMPTY 0x10 /* Write Buffer Empty */
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/* Bit masks for NFC_IRQSTAT */
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#define NBUSYIRQ 0x1 /* Not Busy IRQ */
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#define WB_OVF 0x2 /* Write Buffer Overflow */
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#define WB_EDGE 0x4 /* Write Buffer Edge Detect */
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#define RD_RDY 0x8 /* Read Data Ready */
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#define WR_DONE 0x10 /* Page Write Done */
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#define NAND_IS_512() (CONFIG_BFIN_NFC_CTL_VAL & 0x200)
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/*
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* hardware specific access to control-lines
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*/
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static void bfin_nfc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
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{
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pr_stamp();
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if (cmd == NAND_CMD_NONE)
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return;
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while (bfin_read_NFC_STAT() & WB_FULL)
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continue;
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if (ctrl & NAND_CLE)
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bfin_write_NFC_CMD(cmd);
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else
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bfin_write_NFC_ADDR(cmd);
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SSYNC();
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}
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int bfin_nfc_devready(struct mtd_info *mtd)
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{
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pr_stamp();
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return (bfin_read_NFC_STAT() & NBUSY ? 1 : 0);
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}
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/*
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* PIO mode for buffer writing and reading
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*/
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static void bfin_nfc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
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{
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pr_stamp();
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int i;
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/*
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* Data reads are requested by first writing to NFC_DATA_RD
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* and then reading back from NFC_READ.
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*/
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for (i = 0; i < len; ++i) {
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while (bfin_read_NFC_STAT() & WB_FULL)
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if (ctrlc())
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return;
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/* Contents do not matter */
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bfin_write_NFC_DATA_RD(0x0000);
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while (!(bfin_read_NFC_IRQSTAT() & RD_RDY))
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if (ctrlc())
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return;
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buf[i] = bfin_read_NFC_READ();
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bfin_write_NFC_IRQSTAT(RD_RDY);
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}
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}
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static uint8_t bfin_nfc_read_byte(struct mtd_info *mtd)
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{
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pr_stamp();
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uint8_t val;
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bfin_nfc_read_buf(mtd, &val, 1);
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return val;
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}
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static void bfin_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
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{
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pr_stamp();
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int i;
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for (i = 0; i < len; ++i) {
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while (bfin_read_NFC_STAT() & WB_FULL)
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if (ctrlc())
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return;
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bfin_write_NFC_DATA_WR(buf[i]);
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}
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}
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/*
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* ECC functions
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* These allow the bfin to use the controller's ECC
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* generator block to ECC the data as it passes through
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*/
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/*
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* ECC error correction function
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*/
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static int bfin_nfc_correct_data_256(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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u32 syndrome[5];
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u32 calced, stored;
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unsigned short failing_bit, failing_byte;
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u_char data;
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pr_stamp();
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calced = calc_ecc[0] | (calc_ecc[1] << 8) | (calc_ecc[2] << 16);
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stored = read_ecc[0] | (read_ecc[1] << 8) | (read_ecc[2] << 16);
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syndrome[0] = (calced ^ stored);
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/*
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* syndrome 0: all zero
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* No error in data
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* No action
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*/
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if (!syndrome[0] || !calced || !stored)
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return 0;
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/*
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* sysdrome 0: only one bit is one
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* ECC data was incorrect
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* No action
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*/
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if (hweight32(syndrome[0]) == 1)
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return 1;
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syndrome[1] = (calced & 0x7FF) ^ (stored & 0x7FF);
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syndrome[2] = (calced & 0x7FF) ^ ((calced >> 11) & 0x7FF);
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syndrome[3] = (stored & 0x7FF) ^ ((stored >> 11) & 0x7FF);
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syndrome[4] = syndrome[2] ^ syndrome[3];
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/*
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* sysdrome 0: exactly 11 bits are one, each parity
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* and parity' pair is 1 & 0 or 0 & 1.
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* 1-bit correctable error
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* Correct the error
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*/
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if (hweight32(syndrome[0]) == 11 && syndrome[4] == 0x7FF) {
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failing_bit = syndrome[1] & 0x7;
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failing_byte = syndrome[1] >> 0x3;
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data = *(dat + failing_byte);
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data = data ^ (0x1 << failing_bit);
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*(dat + failing_byte) = data;
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return 0;
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}
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/*
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* sysdrome 0: random data
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* More than 1-bit error, non-correctable error
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* Discard data, mark bad block
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*/
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return 1;
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}
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static int bfin_nfc_correct_data(struct mtd_info *mtd, u_char *dat,
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u_char *read_ecc, u_char *calc_ecc)
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{
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int ret;
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pr_stamp();
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ret = bfin_nfc_correct_data_256(mtd, dat, read_ecc, calc_ecc);
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/* If page size is 512, correct second 256 bytes */
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if (NAND_IS_512()) {
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dat += 256;
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read_ecc += 8;
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calc_ecc += 8;
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ret |= bfin_nfc_correct_data_256(mtd, dat, read_ecc, calc_ecc);
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}
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return ret;
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}
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static void reset_ecc(void)
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{
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bfin_write_NFC_RST(0x1);
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while (bfin_read_NFC_RST() & 1)
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continue;
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}
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static void bfin_nfc_enable_hwecc(struct mtd_info *mtd, int mode)
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{
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reset_ecc();
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}
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static int bfin_nfc_calculate_ecc(struct mtd_info *mtd,
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const u_char *dat, u_char *ecc_code)
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{
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u16 ecc0, ecc1;
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u32 code[2];
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u8 *p;
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pr_stamp();
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/* first 4 bytes ECC code for 256 page size */
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ecc0 = bfin_read_NFC_ECC0();
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ecc1 = bfin_read_NFC_ECC1();
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code[0] = (ecc0 & 0x7FF) | ((ecc1 & 0x7FF) << 11);
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/* first 3 bytes in ecc_code for 256 page size */
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p = (u8 *) code;
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memcpy(ecc_code, p, 3);
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/* second 4 bytes ECC code for 512 page size */
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if (NAND_IS_512()) {
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ecc0 = bfin_read_NFC_ECC2();
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ecc1 = bfin_read_NFC_ECC3();
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code[1] = (ecc0 & 0x7FF) | ((ecc1 & 0x7FF) << 11);
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/* second 3 bytes in ecc_code for second 256
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* bytes of 512 page size
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*/
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p = (u8 *) (code + 1);
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memcpy((ecc_code + 3), p, 3);
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}
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reset_ecc();
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return 0;
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}
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#ifdef CONFIG_BFIN_NFC_BOOTROM_ECC
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# define BOOTROM_ECC 1
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#else
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# define BOOTROM_ECC 0
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#endif
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static uint8_t bbt_pattern[] = { 0xff };
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static struct nand_bbt_descr bootrom_bbt = {
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.options = 0,
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.offs = 63,
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.len = 1,
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.pattern = bbt_pattern,
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};
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static struct nand_ecclayout bootrom_ecclayout = {
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.eccbytes = 24,
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.eccpos = {
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0x8 * 0, 0x8 * 0 + 1, 0x8 * 0 + 2,
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0x8 * 1, 0x8 * 1 + 1, 0x8 * 1 + 2,
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0x8 * 2, 0x8 * 2 + 1, 0x8 * 2 + 2,
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0x8 * 3, 0x8 * 3 + 1, 0x8 * 3 + 2,
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0x8 * 4, 0x8 * 4 + 1, 0x8 * 4 + 2,
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0x8 * 5, 0x8 * 5 + 1, 0x8 * 5 + 2,
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0x8 * 6, 0x8 * 6 + 1, 0x8 * 6 + 2,
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0x8 * 7, 0x8 * 7 + 1, 0x8 * 7 + 2
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},
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.oobfree = {
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{ 0x8 * 0 + 3, 5 },
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{ 0x8 * 1 + 3, 5 },
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{ 0x8 * 2 + 3, 5 },
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{ 0x8 * 3 + 3, 5 },
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{ 0x8 * 4 + 3, 5 },
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{ 0x8 * 5 + 3, 5 },
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{ 0x8 * 6 + 3, 5 },
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{ 0x8 * 7 + 3, 5 },
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}
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};
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/*
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* Board-specific NAND initialization. The following members of the
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* argument are board-specific (per include/linux/mtd/nand.h):
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* - IO_ADDR_R?: address to read the 8 I/O lines of the flash device
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* - IO_ADDR_W?: address to write the 8 I/O lines of the flash device
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* - cmd_ctrl: hardwarespecific function for accesing control-lines
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* - dev_ready: hardwarespecific function for accesing device ready/busy line
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* - enable_hwecc?: function to enable (reset) hardware ecc generator. Must
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* only be provided if a hardware ECC is available
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* - ecc.mode: mode of ecc, see defines
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* - chip_delay: chip dependent delay for transfering data from array to
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* read regs (tR)
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* - options: various chip options. They can partly be set to inform
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* nand_scan about special functionality. See the defines for further
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* explanation
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* Members with a "?" were not set in the merged testing-NAND branch,
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* so they are not set here either.
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*/
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int board_nand_init(struct nand_chip *chip)
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{
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pr_stamp();
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/* set width/ecc/timings/etc... */
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bfin_write_NFC_CTL(CONFIG_BFIN_NFC_CTL_VAL);
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/* clear interrupt status */
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bfin_write_NFC_IRQMASK(0x0);
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bfin_write_NFC_IRQSTAT(0xffff);
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/* enable GPIO function enable register */
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#ifdef __ADSPBF54x__
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bfin_write_PORTJ_FER(bfin_read_PORTJ_FER() | 6);
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#elif defined(__ADSPBF52x__)
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bfin_write_PORTH_FER(bfin_read_PORTH_FER() | 0xFCFF);
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bfin_write_PORTH_MUX(0);
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#else
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# error no support for this variant
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#endif
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chip->cmd_ctrl = bfin_nfc_cmd_ctrl;
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chip->read_buf = bfin_nfc_read_buf;
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chip->write_buf = bfin_nfc_write_buf;
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chip->read_byte = bfin_nfc_read_byte;
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#ifdef CONFIG_BFIN_NFC_NO_HW_ECC
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# define ECC_HW 0
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#else
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# define ECC_HW 1
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#endif
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if (ECC_HW) {
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if (BOOTROM_ECC) {
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chip->badblock_pattern = &bootrom_bbt;
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chip->ecc.layout = &bootrom_ecclayout;
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}
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if (!NAND_IS_512()) {
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chip->ecc.bytes = 3;
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chip->ecc.size = 256;
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} else {
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chip->ecc.bytes = 6;
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chip->ecc.size = 512;
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}
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chip->ecc.mode = NAND_ECC_HW;
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chip->ecc.calculate = bfin_nfc_calculate_ecc;
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chip->ecc.correct = bfin_nfc_correct_data;
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chip->ecc.hwctl = bfin_nfc_enable_hwecc;
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} else
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chip->ecc.mode = NAND_ECC_SOFT;
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chip->dev_ready = bfin_nfc_devready;
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chip->chip_delay = 0;
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return 0;
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}
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