LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

riscv: dts: Sync DT with Linux Kernel 

Use same dts to boot U-Boot and RISC-V
Linux Kernel v4.16-rc2 in ax25-ae350 platform.

Signed-off-by: Rick Chen <rick@andestech.com>
Signed-off-by: Rick Chen <rickchen36@gmail.com>
Cc: Greentime Hu <green.hu@gmail.com>
This commit is contained in:
Rick Chen 2018-05-29 10:53:41 +08:00 committed by Andes
parent 28b52a6fb7
commit c14e90e844
1 changed files with 78 additions and 38 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

116
arch/riscv/dts/ae350.dts
View File

@ -1,90 +1,131 @@
/dts-v1/; /dts-v1/;
/ { / {
compatible = "riscv32 nx25"; #address-cells = <2>;
#address-cells = <1>; #size-cells = <2>;
#size-cells = <1>; compatible = "andestech,ax25";
interrupt-parent = <&intc>; model = "andestech,ax25";
aliases { aliases {
uart0 = &serial0; uart0 = &serial0;
ethernet0 = &mac0;
spi0 = &spi; spi0 = &spi;
} ; } ;
chosen { chosen {
bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7"; bootargs = "console=ttyS0,38400n8 earlyprintk=uart8250-32bit,0xf0300000 debug loglevel=7";
stdout-path = "uart0:38400n8"; stdout-path = "uart0:38400n8";
tick-timer = &timer0; };
cpus {
#address-cells = <1>;
#size-cells = <0>;
timebase-frequency = <10000000>;
CPU0: cpu@0 {
device_type = "cpu";
reg = <0>;
status = "okay";
compatible = "riscv";
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv39";
clock-frequency = <60000000>;
CPU0_intc: interrupt-controller {
#interrupt-cells = <1>;
interrupt-controller;
compatible = "riscv,cpu-intc";
};
};
}; };
memory@0 { memory@0 {
device_type = "memory"; device_type = "memory";
reg = <0x00000000 0x40000000>; reg = <0x0 0x00000000 0x0 0x40000000>;
}; };
spiclk: virt_100mhz { soc {
#clock-cells = <0>; #address-cells = <2>;
compatible = "fixed-clock"; #size-cells = <2>;
clock-frequency = <100000000>; compatible = "andestech,riscv-ae350-soc";
ranges;
}; };
cpus { plmt0@e6000000 {
#address-cells = <1>; compatible = "riscv,plmt0";
#size-cells = <0>; interrupts-extended = <&CPU0_intc 7>;
cpu@0 { reg = <0x0 0xe6000000 0x0 0x100000>;
compatible = "andestech,n13";
reg = <0>;
/* FIXME: to fill correct frqeuency */
clock-frequency = <60000000>;
}; };
plic0: interrupt-controller@e4000000 {
compatible = "riscv,plic0";
#address-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller;
reg = <0x0 0xe4000000 0x0 0x2000000>;
riscv,ndev=<31>;
interrupts-extended = <&CPU0_intc 11 &CPU0_intc 9>;
}; };
intc: interrupt-controller { plic1: interrupt-controller@e6400000 {
compatible = "andestech,atnointc010"; compatible = "riscv,plic1";
#interrupt-cells = <1>; #address-cells = <2>;
#interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
reg = <0x0 0xe6400000 0x0 0x400000>;
riscv,ndev=<1>;
interrupts-extended = <&CPU0_intc 3>;
};
spiclk: virt_100mhz {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <100000000>;
};
timer0: timer@f0400000 {
compatible = "andestech,atcpit100";
reg = <0x0 0xf0400000 0x0 0x1000>;
clock-frequency = <40000000>;
interrupts = <3 4>;
interrupt-parent = <&plic0>;
}; };
serial0: serial@f0300000 { serial0: serial@f0300000 {
compatible = "andestech,uart16550", "ns16550a"; compatible = "andestech,uart16550", "ns16550a";
reg = <0xf0300000 0x1000>; reg = <0x0 0xf0300000 0x0 0x1000>;
interrupts = <7 4>; interrupts = <9 4>;
clock-frequency = <19660800>; clock-frequency = <19660800>;
reg-shift = <2>; reg-shift = <2>;
reg-offset = <32>; reg-offset = <32>;
no-loopback-test = <1>; no-loopback-test = <1>;
}; interrupt-parent = <&plic0>;
timer0: timer@f0400000 {
compatible = "andestech,atcpit100";
reg = <0xf0400000 0x1000>;
interrupts = <2 4>;
clock-frequency = <40000000>;
}; };
mac0: mac@e0100000 { mac0: mac@e0100000 {
compatible = "andestech,atmac100"; compatible = "andestech,atmac100";
reg = <0xe0100000 0x1000>; reg = <0x0 0xe0100000 0x0 0x1000>;
interrupts = <25 4>; interrupts = <19 4>;
interrupt-parent = <&plic0>;
}; };
mmc0: mmc@f0e00000 { mmc0: mmc@f0e00000 {
compatible = "andestech,atsdc010"; compatible = "andestech,atfsdc010";
max-frequency = <100000000>; max-frequency = <100000000>;
clock-freq-min-max = <400000 100000000>;
fifo-depth = <0x10>; fifo-depth = <0x10>;
reg = <0xf0e00000 0x1000>; reg = <0x0 0xf0e00000 0x0 0x1000>;
interrupts = <17 4>; interrupts = <18 4>;
cap-sd-highspeed; cap-sd-highspeed;
interrupt-parent = <&plic0>;
}; };
spi: spi@f0b00000 { spi: spi@f0b00000 {
compatible = "andestech,atcspi200"; compatible = "andestech,atcspi200";
reg = <0xf0b00000 0x1000>; reg = <0x0 0xf0b00000 0x0 0x1000>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
num-cs = <1>; num-cs = <1>;
clocks = <&spiclk>; clocks = <&spiclk>;
interrupts = <3 4>; interrupts = <3 4>;
interrupt-parent = <&plic0>;
flash@0 { flash@0 {
compatible = "spi-flash"; compatible = "spi-flash";
spi-max-frequency = <50000000>; spi-max-frequency = <50000000>;
@ -93,5 +134,4 @@
spi-cpha; spi-cpha;
}; };
}; };
}; };