MLK-18155-1 dts: mx6ulevk: Add DTS for i.MX6UL EVK boards
Update imx6ul.dtsi file to align with kernel (commit f3834c73366f985fef6c1fdaaa129dfceb6151cb) Remove the MMC alias due DM MMC will used as device index. Add the DTS files for 14x14 EVK, 9x9 EVK, etc. Signed-off-by: Ye Li <ye.li@nxp.com>
This commit is contained in:
Ye Li
parent
bbc43351ab
commit
c2e510834d
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@ -382,7 +382,11 @@ dtb-$(CONFIG_VF610) += vf500-colibri.dtb \
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dtb-$(CONFIG_MX53) += imx53-cx9020.dtb
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dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
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dtb-$(CONFIG_MX6) += imx6ul-14x14-evk.dtb \
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imx6ul-14x14-evk-emmc.dtb \
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imx6ul-14x14-evk-gpmi-weim.dtb \
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imx6ul-9x9-evk.dtb \
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imx6ull-14x14-evk.dtb \
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imx6sl-evk.dtb \
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imx6sll-evk.dtb \
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imx6dl-icore.dtb \
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@ -0,0 +1,20 @@
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "imx6ul-14x14-evk.dts"
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2_8bit>;
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pinctrl-1 = <&pinctrl_usdhc2_8bit_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc2_8bit_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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@ -0,0 +1,49 @@
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "imx6ul-14x14-evk.dts"
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&gpmi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpmi_nand_1>;
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status = "okay";
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nand-on-flash-bbt;
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};
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&iomuxc {
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imx6ul-evk-gpmi-rework {
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pinctrl_gpmi_nand_1: gpmi-nand-1 {
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fsl,pins = <
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MX6UL_PAD_NAND_CLE__RAWNAND_CLE 0xb0b1
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MX6UL_PAD_NAND_ALE__RAWNAND_ALE 0xb0b1
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MX6UL_PAD_NAND_WP_B__RAWNAND_WP_B 0xb0b1
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MX6UL_PAD_NAND_READY_B__RAWNAND_READY_B 0xb000
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MX6UL_PAD_NAND_CE0_B__RAWNAND_CE0_B 0xb0b1
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MX6UL_PAD_NAND_CE1_B__RAWNAND_CE1_B 0xb0b1
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MX6UL_PAD_NAND_RE_B__RAWNAND_RE_B 0xb0b1
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MX6UL_PAD_NAND_WE_B__RAWNAND_WE_B 0xb0b1
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MX6UL_PAD_NAND_DATA00__RAWNAND_DATA00 0xb0b1
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MX6UL_PAD_NAND_DATA01__RAWNAND_DATA01 0xb0b1
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MX6UL_PAD_NAND_DATA02__RAWNAND_DATA02 0xb0b1
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MX6UL_PAD_NAND_DATA03__RAWNAND_DATA03 0xb0b1
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MX6UL_PAD_NAND_DATA04__RAWNAND_DATA04 0xb0b1
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MX6UL_PAD_NAND_DATA05__RAWNAND_DATA05 0xb0b1
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MX6UL_PAD_NAND_DATA06__RAWNAND_DATA06 0xb0b1
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MX6UL_PAD_NAND_DATA07__RAWNAND_DATA07 0xb0b1
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>;
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};
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};
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};
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&qspi {
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status = "disabled";
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};
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&usdhc2 {
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status = "disabled";
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};
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@ -0,0 +1,780 @@
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "imx6ul.dtsi"
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/ {
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model = "Freescale i.MX6 UltraLite 14x14 EVK Board";
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compatible = "fsl,imx6ul-14x14-evk", "fsl,imx6ul";
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chosen {
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stdout-path = &uart1;
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};
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memory {
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reg = <0x80000000 0x20000000>;
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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linux,cma {
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compatible = "shared-dma-pool";
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reusable;
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size = <0x14000000>;
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linux,cma-default;
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};
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};
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backlight {
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compatible = "pwm-backlight";
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pwms = <&pwm1 0 5000000>;
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brightness-levels = <0 4 8 16 32 64 128 255>;
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default-brightness-level = <6>;
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status = "okay";
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};
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pxp_v4l2 {
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compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
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status = "okay";
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};
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regulators {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <0>;
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reg_can_3v3: regulator@0 {
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compatible = "regulator-fixed";
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reg = <0>;
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regulator-name = "can-3v3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
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};
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reg_sd1_vmmc: regulator@1 {
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compatible = "regulator-fixed";
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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reg_gpio_dvfs: regulator-gpio {
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compatible = "regulator-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dvfs>;
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regulator-min-microvolt = <1300000>;
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regulator-max-microvolt = <1400000>;
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regulator-name = "gpio_dvfs";
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regulator-type = "voltage";
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gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
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states = <1300000 0x1 1400000 0x0>;
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};
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};
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sound: sound {
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compatible = "fsl,imx6ul-evk-wm8960",
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"fsl,imx-audio-wm8960";
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model = "wm8960-audio";
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cpu-dai = <&sai2>;
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audio-codec = <&codec>;
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asrc-controller = <&asrc>;
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codec-master;
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gpr = <&gpr 4 0x100000 0x100000>;
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/*
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* hp-det = <hp-det-pin hp-det-polarity>;
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* hp-det-pin: JD1 JD2 or JD3
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* hp-det-polarity = 0: hp detect high for headphone
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* hp-det-polarity = 1: hp detect high for speaker
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*/
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hp-det = <3 0>;
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hp-det-gpios = <&gpio5 4 0>;
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mic-det-gpios = <&gpio5 4 0>;
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audio-routing =
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"Headphone Jack", "HP_L",
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"Headphone Jack", "HP_R",
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"Ext Spk", "SPK_LP",
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"Ext Spk", "SPK_LN",
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"Ext Spk", "SPK_RP",
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"Ext Spk", "SPK_RN",
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"LINPUT2", "Mic Jack",
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"LINPUT3", "Mic Jack",
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"RINPUT1", "Main MIC",
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"RINPUT2", "Main MIC",
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"Mic Jack", "MICB",
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"Main MIC", "MICB",
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"CPU-Playback", "ASRC-Playback",
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"Playback", "CPU-Playback",
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"ASRC-Capture", "CPU-Capture",
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"CPU-Capture", "Capture";
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};
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spi4 {
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compatible = "spi-gpio";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spi4>;
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pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
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status = "okay";
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gpio-sck = <&gpio5 11 0>;
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gpio-mosi = <&gpio5 10 0>;
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cs-gpios = <&gpio5 7 0>;
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num-chipselects = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio_spi: gpio_spi@0 {
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compatible = "fairchild,74hc595";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0>;
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registers-number = <1>;
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registers-default = /bits/ 8 <0x57>;
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spi-max-frequency = <100000>;
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};
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};
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};
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&cpu0 {
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arm-supply = <®_arm>;
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soc-supply = <®_soc>;
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dc-supply = <®_gpio_dvfs>;
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};
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&clks {
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assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
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assigned-clock-rates = <786432000>;
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};
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&csi {
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status = "disabled";
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port {
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csi1_ep: endpoint {
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remote-endpoint = <&ov5640_ep>;
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};
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};
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet1>;
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phy-mode = "rmii";
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phy-handle = <ðphy0>;
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status = "okay";
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};
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&fec2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_enet2>;
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phy-mode = "rmii";
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phy-handle = <ðphy1>;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@2 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <2>;
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};
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ethphy1: ethernet-phy@1 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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};
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};
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};
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&can1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan1>;
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xceiver-supply = <®_can_3v3>;
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status = "okay";
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};
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&can2 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexcan2>;
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xceiver-supply = <®_can_3v3>;
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status = "okay";
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};
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&gpc {
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fsl,cpu_pupscr_sw2iso = <0x1>;
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fsl,cpu_pupscr_sw = <0x0>;
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fsl,cpu_pdnscr_iso2sw = <0x1>;
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fsl,cpu_pdnscr_iso = <0x1>;
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fsl,ldo-bypass = <0>; /* DCDC, ldo-enable */
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c1>;
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pinctrl-1 = <&pinctrl_i2c1_gpio>;
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scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
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status = "okay";
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mag3110@0e {
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compatible = "fsl,mag3110";
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reg = <0x0e>;
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position = <2>;
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};
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fxls8471@1e {
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compatible = "fsl,fxls8471";
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reg = <0x1e>;
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position = <0>;
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interrupt-parent = <&gpio5>;
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interrupts = <0 8>;
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};
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};
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&i2c2 {
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clock_frequency = <100000>;
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pinctrl-names = "default", "gpio";
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pinctrl-0 = <&pinctrl_i2c2>;
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pinctrl-1 = <&pinctrl_i2c2_gpio>;
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scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
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sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
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status = "okay";
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codec: wm8960@1a {
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compatible = "wlf,wm8960";
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reg = <0x1a>;
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clocks = <&clks IMX6UL_CLK_SAI2>;
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clock-names = "mclk";
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wlf,shared-lrclk;
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};
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ov5640: ov5640@3c {
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compatible = "ovti,ov5640";
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reg = <0x3c>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_csi1>;
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clocks = <&clks IMX6UL_CLK_CSI>;
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clock-names = "csi_mclk";
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pwn-gpios = <&gpio_spi 6 1>;
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rst-gpios = <&gpio_spi 5 0>;
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csi_id = <0>;
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mclk = <24000000>;
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mclk_source = <0>;
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status = "disabled";
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port {
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ov5640_ep: endpoint {
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remote-endpoint = <&csi1_ep>;
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};
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};
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};
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};
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&iomuxc {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_hog_1>;
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imx6ul-evk {
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pinctrl_hog_1: hoggrp-1 {
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fsl,pins = <
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MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
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MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
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MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
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MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000
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>;
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};
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pinctrl_csi1: csi1grp {
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fsl,pins = <
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MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
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MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
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MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
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MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
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MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
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MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
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MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
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MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
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MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
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MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
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MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
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MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
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>;
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};
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pinctrl_dvfs: dvfsgrp {
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fsl,pins = <
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MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
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>;
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};
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pinctrl_enet1: enet1grp {
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fsl,pins = <
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MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
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MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
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MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
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MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
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MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
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>;
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};
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pinctrl_enet2: enet2grp {
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fsl,pins = <
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MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
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MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
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MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
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MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
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MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
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MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
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MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp{
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
|
||||
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp{
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
|
||||
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
|
||||
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1grp_gpio {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
|
||||
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
|
||||
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_gpio: i2c2grp_gpio {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
|
||||
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcdif_dat: lcdifdatgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
|
||||
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
|
||||
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
|
||||
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
|
||||
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
|
||||
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
|
||||
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
|
||||
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
|
||||
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
|
||||
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
|
||||
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
|
||||
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
|
||||
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
|
||||
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
|
||||
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
|
||||
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
|
||||
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
|
||||
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
|
||||
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
|
||||
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
|
||||
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
|
||||
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
|
||||
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
|
||||
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcdif_ctrl: lcdifctrlgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
|
||||
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
|
||||
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
|
||||
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
|
||||
/* used for lcd reset */
|
||||
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pf1550: pf1550 {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_qspi: qspigrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
|
||||
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
|
||||
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
|
||||
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
|
||||
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
|
||||
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai2: sai2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
|
||||
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
|
||||
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
|
||||
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
|
||||
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
|
||||
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sim2_1: sim2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
|
||||
MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x11
|
||||
MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb810
|
||||
MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb810
|
||||
MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb811
|
||||
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_spi4: spi4grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
|
||||
MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
|
||||
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
|
||||
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tsc: tscgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
|
||||
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
|
||||
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
|
||||
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
|
||||
MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
|
||||
MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2dte: uart2dtegrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
|
||||
MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1
|
||||
MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb_otg1_id: usbotg1idgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10071
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_8bit: usdhc2grp_8bit {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_8bit_100mhz: usdhc2grp_8bit_100mhz {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100b9
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170b9
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170b9
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170b9
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170b9
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170b9
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170b9
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170b9
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170b9
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_8bit_200mhz: usdhc2grp_8bit_200mhz {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x100f9
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x170f9
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x170f9
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x170f9
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x170f9
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x170f9
|
||||
MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x170f9
|
||||
MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x170f9
|
||||
MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x170f9
|
||||
MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x170f9
|
||||
>;
|
||||
};
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcdif_dat
|
||||
&pinctrl_lcdif_ctrl>;
|
||||
display = <&display0>;
|
||||
status = "okay";
|
||||
|
||||
display0: display {
|
||||
bits-per-pixel = <16>;
|
||||
bus-width = <24>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <9200000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hfront-porch = <8>;
|
||||
hback-porch = <4>;
|
||||
hsync-len = <41>;
|
||||
vback-porch = <2>;
|
||||
vfront-porch = <4>;
|
||||
vsync-len = <10>;
|
||||
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pxp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_qspi>;
|
||||
status = "okay";
|
||||
ddrsmp=<0>;
|
||||
|
||||
flash0: n25q256a@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spi-flash";
|
||||
spi-max-frequency = <29000000>;
|
||||
spi-nor,ddr-quad-read-dummy = <6>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai2>;
|
||||
|
||||
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
|
||||
<&clks IMX6UL_CLK_SAI2>;
|
||||
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
|
||||
assigned-clock-rates = <0>, <12288000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sim2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sim2_1>;
|
||||
assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>;
|
||||
assigned-clock-rates = <240000000>;
|
||||
/* GPIO_ACTIVE_HIGH/LOW:sim card voltage control
|
||||
* NCN8025:Vcc = ACTIVE_HIGH?5V:3V
|
||||
* TDA8035:Vcc = ACTIVE_HIGH?5V:1.8V
|
||||
*/
|
||||
pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_HIGH>;
|
||||
port = <1>;
|
||||
sven_low_active;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tsc>;
|
||||
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
measure-delay-time = <0xffff>;
|
||||
pre-charge-time = <0xfff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
fsl,uart-has-rtscts;
|
||||
/* for DTE mode, add below change */
|
||||
/* fsl,dte-mode; */
|
||||
/* pinctrl-0 = <&pinctrl_uart2dte>; */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg1_id>;
|
||||
dr_mode = "otg";
|
||||
srp-disable;
|
||||
hnp-disable;
|
||||
adp-disable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbphy1 {
|
||||
tx-d-cal = <0x5>;
|
||||
};
|
||||
|
||||
&usbphy2 {
|
||||
tx-d-cal = <0x5>;
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
|
||||
keep-power-in-suspend;
|
||||
enable-sdio-wakeup;
|
||||
vmmc-supply = <®_sd1_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
non-removable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,wdog_b;
|
||||
};
|
||||
|
|
@ -0,0 +1,832 @@
|
|||
/*
|
||||
* Copyright (C) 2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2017 NXP
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "imx6ul.dtsi"
|
||||
|
||||
/ {
|
||||
model = "Freescale i.MX6 UltraLite 9x9 EVK Board";
|
||||
compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul";
|
||||
|
||||
backlight {
|
||||
compatible = "pwm-backlight";
|
||||
pwms = <&pwm1 0 5000000>;
|
||||
brightness-levels = <0 4 8 16 32 64 128 255>;
|
||||
default-brightness-level = <6>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
chosen {
|
||||
stdout-path = &uart1;
|
||||
};
|
||||
|
||||
memory {
|
||||
reg = <0x80000000 0x10000000>;
|
||||
};
|
||||
|
||||
reserved-memory {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
linux,cma {
|
||||
compatible = "shared-dma-pool";
|
||||
reusable;
|
||||
size = <0x6000000>;
|
||||
linux,cma-default;
|
||||
};
|
||||
};
|
||||
|
||||
pxp_v4l2 {
|
||||
compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2";
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
regulators {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
reg_can_3v3: regulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
reg = <0>;
|
||||
regulator-name = "can-3v3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
reg_gpio_dvfs: regulator-gpio {
|
||||
compatible = "regulator-gpio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_dvfs>;
|
||||
regulator-min-microvolt = <1300000>;
|
||||
regulator-max-microvolt = <1400000>;
|
||||
regulator-name = "gpio_dvfs";
|
||||
regulator-type = "voltage";
|
||||
gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
|
||||
states = <1300000 0x1 1400000 0x0>;
|
||||
};
|
||||
|
||||
reg_sd1_vmmc: regulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "VSD_3V3";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
|
||||
enable-active-high;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
compatible = "fsl,imx6ul-evk-wm8960",
|
||||
"fsl,imx-audio-wm8960";
|
||||
model = "wm8960-audio";
|
||||
cpu-dai = <&sai2>;
|
||||
audio-codec = <&codec>;
|
||||
asrc-controller = <&asrc>;
|
||||
codec-master;
|
||||
gpr = <&gpr 4 0x100000 0x100000>;
|
||||
/*
|
||||
* hp-det = <hp-det-pin hp-det-polarity>;
|
||||
* hp-det-pin: JD1 JD2 or JD3
|
||||
* hp-det-polarity = 0: hp detect high for headphone
|
||||
* hp-det-polarity = 1: hp detect high for speaker
|
||||
*/
|
||||
hp-det = <3 0>;
|
||||
hp-det-gpios = <&gpio5 4 0>;
|
||||
mic-det-gpios = <&gpio5 4 0>;
|
||||
audio-routing =
|
||||
"Headphone Jack", "HP_L",
|
||||
"Headphone Jack", "HP_R",
|
||||
"Ext Spk", "SPK_LP",
|
||||
"Ext Spk", "SPK_LN",
|
||||
"Ext Spk", "SPK_RP",
|
||||
"Ext Spk", "SPK_RN",
|
||||
"LINPUT2", "Mic Jack",
|
||||
"LINPUT3", "Mic Jack",
|
||||
"RINPUT1", "Main MIC",
|
||||
"RINPUT2", "Main MIC",
|
||||
"Mic Jack", "MICB",
|
||||
"Main MIC", "MICB",
|
||||
"CPU-Playback", "ASRC-Playback",
|
||||
"Playback", "CPU-Playback",
|
||||
"ASRC-Capture", "CPU-Capture",
|
||||
"CPU-Capture", "Capture";
|
||||
};
|
||||
|
||||
spi4 {
|
||||
compatible = "spi-gpio";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_spi4>;
|
||||
pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
gpio-sck = <&gpio5 11 0>;
|
||||
gpio-mosi = <&gpio5 10 0>;
|
||||
cs-gpios = <&gpio5 7 0>;
|
||||
num-chipselects = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
gpio_spi: gpio_spi@0 {
|
||||
compatible = "fairchild,74hc595";
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
reg = <0>;
|
||||
registers-number = <1>;
|
||||
registers-default = /bits/ 8 <0x57>;
|
||||
spi-max-frequency = <100000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&clks {
|
||||
assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
|
||||
assigned-clock-rates = <786432000>;
|
||||
};
|
||||
|
||||
&cpu0 {
|
||||
/*
|
||||
* on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN,
|
||||
* to align with other platform and use the same cpufreq
|
||||
* driver, still use the seperated OPP define for arm
|
||||
* and soc.
|
||||
*/
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
528000 1175000
|
||||
396000 1175000
|
||||
198000 1175000
|
||||
>;
|
||||
fsl,soc-operating-points = <
|
||||
/* KHz uV */
|
||||
528000 1175000
|
||||
396000 1175000
|
||||
198000 1175000
|
||||
>;
|
||||
arm-supply = <&sw1c_reg>;
|
||||
soc-supply = <&sw1c_reg>;
|
||||
fsl,arm-soc-shared = <1>;
|
||||
};
|
||||
|
||||
&csi {
|
||||
status = "disabled";
|
||||
|
||||
port {
|
||||
csi1_ep: endpoint {
|
||||
remote-endpoint = <&ov5640_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&fec1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet1>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <ðphy0>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&fec2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_enet2>;
|
||||
phy-mode = "rmii";
|
||||
phy-handle = <ðphy1>;
|
||||
status = "okay";
|
||||
|
||||
mdio {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ethphy0: ethernet-phy@2 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <2>;
|
||||
};
|
||||
|
||||
ethphy1: ethernet-phy@1 {
|
||||
compatible = "ethernet-phy-ieee802.3-c22";
|
||||
reg = <1>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&can1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan1>;
|
||||
xceiver-supply = <®_can_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&can2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_flexcan2>;
|
||||
xceiver-supply = <®_can_3v3>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpc {
|
||||
fsl,cpu_pupscr_sw2iso = <0x1>;
|
||||
fsl,cpu_pupscr_sw = <0x0>;
|
||||
fsl,cpu_pdnscr_iso2sw = <0x1>;
|
||||
fsl,cpu_pdnscr_iso = <0x1>;
|
||||
fsl,wdog-reset = <1>; /* watchdog select of reset source */
|
||||
fsl,ldo-bypass = <1>;
|
||||
};
|
||||
|
||||
&i2c1 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c1>;
|
||||
pinctrl-1 = <&pinctrl_i2c1_gpio>;
|
||||
scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
pmic: pfuze3000@08 {
|
||||
compatible = "fsl,pfuze3000";
|
||||
reg = <0x08>;
|
||||
|
||||
regulators {
|
||||
sw1a_reg: sw1a {
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
/* use sw1c_reg to align with pfuze100/pfuze200 */
|
||||
sw1c_reg: sw1b {
|
||||
regulator-min-microvolt = <700000>;
|
||||
regulator-max-microvolt = <1475000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
regulator-ramp-delay = <6250>;
|
||||
};
|
||||
|
||||
sw2_reg: sw2 {
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
sw3a_reg: sw3 {
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1650000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
swbst_reg: swbst {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5150000>;
|
||||
};
|
||||
|
||||
snvs_reg: vsnvs {
|
||||
regulator-min-microvolt = <1000000>;
|
||||
regulator-max-microvolt = <3000000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vref_reg: vrefddr {
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen1_reg: vldo1 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen2_reg: vldo2 {
|
||||
regulator-min-microvolt = <800000>;
|
||||
regulator-max-microvolt = <1550000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen3_reg: vccsd {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen4_reg: v33 {
|
||||
regulator-min-microvolt = <2850000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen5_reg: vldo3 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
vgen6_reg: vldo4 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
mag3110@0e {
|
||||
compatible = "fsl,mag3110";
|
||||
reg = <0x0e>;
|
||||
position = <2>;
|
||||
};
|
||||
|
||||
fxls8471@1e {
|
||||
compatible = "fsl,fxls8471";
|
||||
reg = <0x1e>;
|
||||
position = <0>;
|
||||
interrupt-parent = <&gpio5>;
|
||||
interrupts = <0 8>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock_frequency = <100000>;
|
||||
pinctrl-names = "default", "gpio";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
pinctrl-1 = <&pinctrl_i2c2_gpio>;
|
||||
scl-gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>;
|
||||
sda-gpios = <&gpio1 31 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
|
||||
codec: wm8960@1a {
|
||||
compatible = "wlf,wm8960";
|
||||
reg = <0x1a>;
|
||||
clocks = <&clks IMX6UL_CLK_SAI2>;
|
||||
clock-names = "mclk";
|
||||
wlf,shared-lrclk;
|
||||
};
|
||||
|
||||
ov5640: ov5640@3c {
|
||||
compatible = "ovti,ov5640";
|
||||
reg = <0x3c>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_csi1>;
|
||||
clocks = <&clks IMX6UL_CLK_CSI>;
|
||||
clock-names = "csi_mclk";
|
||||
pwn-gpios = <&gpio_spi 6 1>;
|
||||
rst-gpios = <&gpio_spi 5 0>;
|
||||
csi_id = <0>;
|
||||
mclk = <24000000>;
|
||||
mclk_source = <0>;
|
||||
status = "disabled";
|
||||
port {
|
||||
ov5640_ep: endpoint {
|
||||
remote-endpoint = <&csi1_ep>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_hog_1>;
|
||||
imx6ul-evk {
|
||||
pinctrl_csi1: csi1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088
|
||||
MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088
|
||||
MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088
|
||||
MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088
|
||||
MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088
|
||||
MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088
|
||||
MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088
|
||||
MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088
|
||||
MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088
|
||||
MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088
|
||||
MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088
|
||||
MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_dvfs: dvfsgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet1: enet1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0
|
||||
MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_enet2: enet2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0
|
||||
MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0
|
||||
MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031
|
||||
MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan1: flexcan1grp{
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020
|
||||
MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexcan2: flexcan2grp{
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020
|
||||
MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_hog_1: hoggrp-1 {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */
|
||||
MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */
|
||||
MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
|
||||
MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1_gpio: i2c1grp_gpio {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0
|
||||
MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
|
||||
MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_gpio: i2c2grp_gpio {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x1b8b0
|
||||
MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x1b8b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcdif_ctrl: lcdifctrlgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79
|
||||
MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79
|
||||
MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79
|
||||
MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79
|
||||
/* used for lcd reset */
|
||||
MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_lcdif_dat: lcdifdatgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79
|
||||
MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79
|
||||
MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79
|
||||
MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79
|
||||
MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79
|
||||
MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79
|
||||
MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79
|
||||
MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79
|
||||
MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79
|
||||
MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79
|
||||
MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79
|
||||
MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79
|
||||
MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79
|
||||
MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79
|
||||
MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79
|
||||
MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79
|
||||
MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79
|
||||
MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79
|
||||
MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79
|
||||
MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79
|
||||
MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79
|
||||
MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79
|
||||
MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79
|
||||
MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pwm1: pwm1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_qspi: qspigrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1
|
||||
MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1
|
||||
MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1
|
||||
MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1
|
||||
MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1
|
||||
MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai2: sai2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088
|
||||
MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088
|
||||
MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088
|
||||
MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088
|
||||
MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088
|
||||
MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sim2_1: sim2grp-1 {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808
|
||||
MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31
|
||||
MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808
|
||||
MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808
|
||||
MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809
|
||||
MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_spi4: spi4grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1
|
||||
MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1
|
||||
MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1
|
||||
MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_tsc: tscgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0
|
||||
MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0
|
||||
MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0
|
||||
MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1
|
||||
MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1
|
||||
MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2dte: uart2dtegrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1
|
||||
MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1
|
||||
MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1
|
||||
MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usb_otg1_id: usbotg1idgrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9
|
||||
MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9
|
||||
MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9
|
||||
MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9
|
||||
MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9
|
||||
MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059
|
||||
MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059
|
||||
MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059
|
||||
MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059
|
||||
MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059
|
||||
MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0
|
||||
>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_lcdif_dat
|
||||
&pinctrl_lcdif_ctrl>;
|
||||
display = <&display0>;
|
||||
status = "okay";
|
||||
|
||||
display0: display {
|
||||
bits-per-pixel = <16>;
|
||||
bus-width = <24>;
|
||||
|
||||
display-timings {
|
||||
native-mode = <&timing0>;
|
||||
timing0: timing0 {
|
||||
clock-frequency = <9200000>;
|
||||
hactive = <480>;
|
||||
vactive = <272>;
|
||||
hfront-porch = <8>;
|
||||
hback-porch = <4>;
|
||||
hsync-len = <41>;
|
||||
vback-porch = <2>;
|
||||
vfront-porch = <4>;
|
||||
vsync-len = <10>;
|
||||
|
||||
hsync-active = <0>;
|
||||
vsync-active = <0>;
|
||||
de-active = <1>;
|
||||
pixelclk-active = <0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pwm1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_pwm1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&pxp {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_qspi>;
|
||||
status = "okay";
|
||||
ddrsmp=<0>;
|
||||
|
||||
flash0: n25q256a@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "spi-flash";
|
||||
spi-max-frequency = <29000000>;
|
||||
spi-nor,ddr-quad-read-dummy = <6>;
|
||||
reg = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
&sai2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sai2>;
|
||||
|
||||
assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>,
|
||||
<&clks IMX6UL_CLK_SAI2>;
|
||||
assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>;
|
||||
assigned-clock-rates = <0>, <12288000>;
|
||||
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sim2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sim2_1>;
|
||||
assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>;
|
||||
assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>;
|
||||
assigned-clock-rates = <240000000>;
|
||||
pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>;
|
||||
port = <1>;
|
||||
sven_low_active;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&tsc {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_tsc>;
|
||||
xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
|
||||
measure_delay_time = <0xffff>;
|
||||
pre_charge_time = <0xfff>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart1>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_uart2>;
|
||||
fsl,uart-has-rtscts;
|
||||
/* for DTE mode, add below change */
|
||||
/* fsl,dte-mode; */
|
||||
/* pinctrl-0 = <&pinctrl_uart2dte>; */
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usb_otg1_id>;
|
||||
dr_mode = "otg";
|
||||
srp-disable;
|
||||
hnp-disable;
|
||||
adp-disable;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usbotg2 {
|
||||
dr_mode = "host";
|
||||
disable-over-current;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc1 {
|
||||
pinctrl-names = "default", "state_100mhz", "state_200mhz";
|
||||
pinctrl-0 = <&pinctrl_usdhc1>;
|
||||
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
|
||||
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
|
||||
cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
|
||||
keep-power-in-suspend;
|
||||
enable-sdio-wakeup;
|
||||
vmmc-supply = <®_sd1_vmmc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&usdhc2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_usdhc2>;
|
||||
no-1-8-v;
|
||||
non-removable;
|
||||
keep-power-in-suspend;
|
||||
enable-sdio-wakeup;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&wdog1 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_wdog>;
|
||||
fsl,wdog_b;
|
||||
};
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright 2015 Freescale Semiconductor, Inc.
|
||||
* Copyright 2015-2016 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
|
|
@ -26,8 +26,6 @@
|
|||
i2c1 = &i2c2;
|
||||
i2c2 = &i2c3;
|
||||
i2c3 = &i2c4;
|
||||
mmc0 = &usdhc1;
|
||||
mmc1 = &usdhc2;
|
||||
serial0 = &uart1;
|
||||
serial1 = &uart2;
|
||||
serial2 = &uart3;
|
||||
|
|
@ -39,14 +37,15 @@
|
|||
sai1 = &sai1;
|
||||
sai2 = &sai2;
|
||||
sai3 = &sai3;
|
||||
spi0 = &ecspi1;
|
||||
spi1 = &ecspi2;
|
||||
spi2 = &ecspi3;
|
||||
spi3 = &ecspi4;
|
||||
usbotg0 = &usbotg1;
|
||||
usbotg1 = &usbotg2;
|
||||
spi0 = &qspi;
|
||||
spi1 = &ecspi1;
|
||||
spi2 = &ecspi2;
|
||||
spi3 = &ecspi3;
|
||||
spi4 = &ecspi4;
|
||||
usbphy0 = &usbphy1;
|
||||
usbphy1 = &usbphy2;
|
||||
usb0 = &usbotg1;
|
||||
usb1 = &usbotg2;
|
||||
};
|
||||
|
||||
cpus {
|
||||
|
|
@ -60,12 +59,14 @@
|
|||
clock-latency = <61036>; /* two CLK32 periods */
|
||||
operating-points = <
|
||||
/* kHz uV */
|
||||
696000 1275000
|
||||
528000 1175000
|
||||
396000 1025000
|
||||
198000 950000
|
||||
>;
|
||||
fsl,soc-operating-points = <
|
||||
/* KHz uV */
|
||||
696000 1275000
|
||||
528000 1175000
|
||||
396000 1175000
|
||||
198000 1175000
|
||||
|
|
@ -134,7 +135,24 @@
|
|||
compatible = "simple-bus";
|
||||
interrupt-parent = <&gpc>;
|
||||
ranges;
|
||||
u-boot,dm-spl;
|
||||
|
||||
busfreq {
|
||||
compatible = "fsl,imx_busfreq";
|
||||
clocks = <&clks IMX6UL_CLK_PLL2_PFD2>, <&clks IMX6UL_CLK_PLL2_198M>,
|
||||
<&clks IMX6UL_CLK_PLL2_BUS>, <&clks IMX6UL_CLK_ARM>,
|
||||
<&clks IMX6UL_CLK_PLL3_USB_OTG>, <&clks IMX6UL_CLK_PERIPH>,
|
||||
<&clks IMX6UL_CLK_PERIPH_PRE>, <&clks IMX6UL_CLK_PERIPH_CLK2>,
|
||||
<&clks IMX6UL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6UL_CLK_OSC>,
|
||||
<&clks IMX6UL_CLK_AHB>, <&clks IMX6UL_CLK_AXI>,
|
||||
<&clks IMX6UL_CLK_PERIPH2>, <&clks IMX6UL_CLK_PERIPH2_PRE>,
|
||||
<&clks IMX6UL_CLK_PERIPH2_CLK2>, <&clks IMX6UL_CLK_PERIPH2_CLK2_SEL>,
|
||||
<&clks IMX6UL_CLK_STEP>, <&clks IMX6UL_CLK_MMDC_P0_FAST>;
|
||||
clock-names = "pll2_pfd2_396m", "pll2_198m", "pll2_bus", "arm", "pll3_usb_otg",
|
||||
"periph", "periph_pre", "periph_clk2", "periph_clk2_sel", "osc",
|
||||
"ahb", "ocram", "periph2", "periph2_pre", "periph2_clk2", "periph2_clk2_sel",
|
||||
"step", "mmdc";
|
||||
fsl,max_ddr_freq = <400000000>;
|
||||
};
|
||||
|
||||
pmu {
|
||||
compatible = "arm,cortex-a7-pmu";
|
||||
|
|
@ -142,9 +160,19 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
ocram: sram@00900000 {
|
||||
ocrams: sram@00900000 {
|
||||
compatible = "fsl,lpm-sram";
|
||||
reg = <0x00900000 0x4000>;
|
||||
};
|
||||
|
||||
ocrams_ddr: sram@00904000 {
|
||||
compatible = "fsl,ddr-lpm-sram";
|
||||
reg = <0x00904000 0x1000>;
|
||||
};
|
||||
|
||||
ocram: sram@00905000 {
|
||||
compatible = "mmio-sram";
|
||||
reg = <0x00900000 0x20000>;
|
||||
reg = <0x00905000 0x1B000>;
|
||||
};
|
||||
|
||||
dma_apbh: dma-apbh@01804000 {
|
||||
|
|
@ -160,6 +188,21 @@
|
|||
clocks = <&clks IMX6UL_CLK_APBHDMA>;
|
||||
};
|
||||
|
||||
caam_sm: caam-sm@00100000 {
|
||||
compatible = "fsl,imx7d-caam-sm", "fsl,imx6q-caam-sm";
|
||||
reg = <0x00100000 0x3fff>;
|
||||
};
|
||||
|
||||
irq_sec_vio: caam_secvio {
|
||||
compatible = "fsl,imx7d-caam-secvio", "fsl,imx6q-caam-secvio";
|
||||
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
||||
jtag-tamper = "disabled";
|
||||
watchdog-tamper = "enabled";
|
||||
internal-boot-tamper = "enabled";
|
||||
external-pin-tamper = "disabled";
|
||||
};
|
||||
|
||||
|
||||
gpmi: gpmi-nand@01806000 {
|
||||
compatible = "fsl,imx6q-gpmi-nand";
|
||||
#address-cells = <1>;
|
||||
|
|
@ -186,7 +229,6 @@
|
|||
#size-cells = <1>;
|
||||
reg = <0x02000000 0x100000>;
|
||||
ranges;
|
||||
u-boot,dm-spl;
|
||||
|
||||
spba-bus@02000000 {
|
||||
compatible = "fsl,spba-bus", "simple-bus";
|
||||
|
|
@ -195,6 +237,28 @@
|
|||
reg = <0x02000000 0x40000>;
|
||||
ranges;
|
||||
|
||||
spdif: spdif@02004000 {
|
||||
compatible = "fsl,imx6ul-spdif", "fsl,imx35-spdif";
|
||||
reg = <0x02004000 0x4000>;
|
||||
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&sdma 41 18 0>,
|
||||
<&sdma 42 18 0>;
|
||||
dma-names = "rx", "tx";
|
||||
clocks = <&clks IMX6UL_CLK_SPDIF_GCLK>,
|
||||
<&clks IMX6UL_CLK_OSC>,
|
||||
<&clks IMX6UL_CLK_SPDIF>,
|
||||
<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
|
||||
<&clks IMX6UL_CLK_IPG>,
|
||||
<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>,
|
||||
<&clks IMX6UL_CLK_SPBA>;
|
||||
clock-names = "core", "rxtx0",
|
||||
"rxtx1", "rxtx2",
|
||||
"rxtx3", "rxtx4",
|
||||
"rxtx5", "rxtx6",
|
||||
"rxtx7", "spba";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ecspi1: ecspi@02008000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
|
@ -204,6 +268,8 @@
|
|||
clocks = <&clks IMX6UL_CLK_ECSPI1>,
|
||||
<&clks IMX6UL_CLK_ECSPI1>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 3 7 1>, <&sdma 4 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -216,6 +282,8 @@
|
|||
clocks = <&clks IMX6UL_CLK_ECSPI2>,
|
||||
<&clks IMX6UL_CLK_ECSPI2>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 5 7 1>, <&sdma 6 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -228,6 +296,8 @@
|
|||
clocks = <&clks IMX6UL_CLK_ECSPI3>,
|
||||
<&clks IMX6UL_CLK_ECSPI3>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 7 7 1>, <&sdma 8 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -240,23 +310,27 @@
|
|||
clocks = <&clks IMX6UL_CLK_ECSPI4>,
|
||||
<&clks IMX6UL_CLK_ECSPI4>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 9 7 1>, <&sdma 10 7 2>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart7: serial@02018000 {
|
||||
compatible = "fsl,imx6ul-uart",
|
||||
"fsl,imx6q-uart";
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02018000 0x4000>;
|
||||
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_UART7_IPG>,
|
||||
<&clks IMX6UL_CLK_UART7_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 43 4 0>, <&sdma 44 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart1: serial@02020000 {
|
||||
compatible = "fsl,imx6ul-uart",
|
||||
"fsl,imx6q-uart";
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02020000 0x4000>;
|
||||
interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_UART1_IPG>,
|
||||
|
|
@ -267,12 +341,14 @@
|
|||
|
||||
uart8: serial@02024000 {
|
||||
compatible = "fsl,imx6ul-uart",
|
||||
"fsl,imx6q-uart";
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x02024000 0x4000>;
|
||||
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_UART8_IPG>,
|
||||
<&clks IMX6UL_CLK_UART8_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 45 4 0>, <&sdma 46 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -282,9 +358,10 @@
|
|||
reg = <0x02028000 0x4000>;
|
||||
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
|
||||
<&clks IMX6UL_CLK_DUMMY>,
|
||||
<&clks IMX6UL_CLK_SAI1>,
|
||||
<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
||||
dmas = <&sdma 35 24 0>,
|
||||
<&sdma 36 24 0>;
|
||||
dma-names = "rx", "tx";
|
||||
|
|
@ -297,9 +374,11 @@
|
|||
reg = <0x0202c000 0x4000>;
|
||||
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
|
||||
<&clks IMX6UL_CLK_DUMMY>,
|
||||
<&clks IMX6UL_CLK_SAI2>,
|
||||
<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
||||
|
||||
dmas = <&sdma 37 24 0>,
|
||||
<&sdma 38 24 0>;
|
||||
dma-names = "rx", "tx";
|
||||
|
|
@ -312,14 +391,40 @@
|
|||
reg = <0x02030000 0x4000>;
|
||||
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
|
||||
<&clks IMX6UL_CLK_DUMMY>,
|
||||
<&clks IMX6UL_CLK_SAI3>,
|
||||
<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
|
||||
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
||||
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
|
||||
dmas = <&sdma 39 24 0>,
|
||||
<&sdma 40 24 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
asrc: asrc@02034000 {
|
||||
compatible = "fsl,imx53-asrc";
|
||||
reg = <0x02034000 0x4000>;
|
||||
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_ASRC_IPG>,
|
||||
<&clks IMX6UL_CLK_ASRC_MEM>, <&clks 0>,
|
||||
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
|
||||
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
|
||||
<&clks 0>, <&clks 0>, <&clks 0>, <&clks 0>,
|
||||
<&clks IMX6UL_CLK_SPDIF>, <&clks 0>, <&clks 0>,
|
||||
<&clks IMX6UL_CLK_SPBA>;
|
||||
clock-names = "mem", "ipg", "asrck_0",
|
||||
"asrck_1", "asrck_2", "asrck_3", "asrck_4",
|
||||
"asrck_5", "asrck_6", "asrck_7", "asrck_8",
|
||||
"asrck_9", "asrck_a", "asrck_b", "asrck_c",
|
||||
"asrck_d", "asrck_e", "asrck_f", "spba";
|
||||
dmas = <&sdma 17 23 1>, <&sdma 18 23 1>, <&sdma 19 23 1>,
|
||||
<&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>;
|
||||
dma-names = "rxa", "rxb", "rxc",
|
||||
"txa", "txb", "txc";
|
||||
fsl,asrc-rate = <48000>;
|
||||
fsl,asrc-width = <16>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
tsc: tsc@02040000 {
|
||||
|
|
@ -333,6 +438,13 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
bee: bee@02044000 {
|
||||
compatible = "fsl,imx6ul-bee";
|
||||
reg = <0x02044000 0x4000>;
|
||||
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
pwm1: pwm@02080000 {
|
||||
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
||||
reg = <0x02080000 0x4000>;
|
||||
|
|
@ -384,6 +496,7 @@
|
|||
clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
|
||||
<&clks IMX6UL_CLK_CAN1_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
stop-mode = <&gpr 0x10 1 0x10 17>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -394,6 +507,7 @@
|
|||
clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
|
||||
<&clks IMX6UL_CLK_CAN2_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
stop-mode = <&gpr 0x10 2 0x10 18>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -402,8 +516,8 @@
|
|||
reg = <0x02098000 0x4000>;
|
||||
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
|
||||
<&clks IMX6UL_CLK_GPT1_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
<&clks IMX6UL_CLK_GPT_3M>;
|
||||
clock-names = "ipg", "osc_per";
|
||||
};
|
||||
|
||||
gpio1: gpio@0209c000 {
|
||||
|
|
@ -417,7 +531,6 @@
|
|||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
|
||||
<&iomuxc 16 33 16>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
gpio2: gpio@020a0000 {
|
||||
|
|
@ -454,7 +567,6 @@
|
|||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
gpio5: gpio@020ac000 {
|
||||
|
|
@ -469,6 +581,12 @@
|
|||
gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
|
||||
};
|
||||
|
||||
snvslp: snvs@020b0000 {
|
||||
compatible = "fsl,imx6ul-snvs";
|
||||
reg = <0x020b0000 0x4000>;
|
||||
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
fec2: ethernet@020b4000 {
|
||||
compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
|
||||
reg = <0x020b4000 0x4000>;
|
||||
|
|
@ -481,8 +599,11 @@
|
|||
<&clks IMX6UL_CLK_ENET2_REF_125M>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
stop-mode = <&gpr 0x10 4>;
|
||||
fsl,num-tx-queues=<1>;
|
||||
fsl,num-rx-queues=<1>;
|
||||
fsl,magic-packet;
|
||||
fsl,wakeup_irq = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -594,6 +715,19 @@
|
|||
fsl,anatop = <&anatop>;
|
||||
};
|
||||
|
||||
tempmon: tempmon {
|
||||
compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
|
||||
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
|
||||
fsl,tempmon = <&anatop>;
|
||||
fsl,tempmon-data = <&ocotp>;
|
||||
clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
|
||||
};
|
||||
|
||||
caam_snvs: caam-snvs@020cc000 {
|
||||
compatible = "fsl,imx6q-caam-snvs";
|
||||
reg = <0x020cc000 0x4000>;
|
||||
};
|
||||
|
||||
snvs: snvs@020cc000 {
|
||||
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
|
||||
reg = <0x020cc000 0x4000>;
|
||||
|
|
@ -610,7 +744,7 @@
|
|||
compatible = "syscon-poweroff";
|
||||
regmap = <&snvs>;
|
||||
offset = <0x38>;
|
||||
mask = <0x60>;
|
||||
mask = <0x61>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -648,12 +782,12 @@
|
|||
#interrupt-cells = <3>;
|
||||
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&intc>;
|
||||
fsl,mf-mix-wakeup-irq = <0x7c00000 0x7d00 0x0 0x1400640>;
|
||||
};
|
||||
|
||||
iomuxc: iomuxc@020e0000 {
|
||||
compatible = "fsl,imx6ul-iomuxc";
|
||||
reg = <0x020e0000 0x4000>;
|
||||
u-boot,dm-spl;
|
||||
};
|
||||
|
||||
gpr: iomuxc-gpr@020e4000 {
|
||||
|
|
@ -671,6 +805,13 @@
|
|||
clock-names = "ipg", "per";
|
||||
};
|
||||
|
||||
mqs: mqs {
|
||||
compatible = "fsl,imx6sx-mqs";
|
||||
gpr = <&gpr>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
||||
sdma: sdma@020ec000 {
|
||||
compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
|
||||
"fsl,imx35-sdma";
|
||||
|
|
@ -680,6 +821,7 @@
|
|||
<&clks IMX6UL_CLK_SDMA>;
|
||||
clock-names = "ipg", "ahb";
|
||||
#dma-cells = <3>;
|
||||
iram = <&ocram>;
|
||||
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
|
||||
};
|
||||
|
||||
|
|
@ -734,7 +876,44 @@
|
|||
#size-cells = <1>;
|
||||
reg = <0x02100000 0x100000>;
|
||||
ranges;
|
||||
u-boot,dm-spl;
|
||||
|
||||
crypto: caam@2140000 {
|
||||
compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x2140000 0x3c000>;
|
||||
ranges = <0 0x2140000 0x3c000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
|
||||
<&clks IMX6UL_CLK_CAAM_MEM>;
|
||||
clock-names = "ipg", "aclk", "mem";
|
||||
|
||||
sec_ctrl: ctrl@0 {
|
||||
/* CAAM Page 0 only accessible */
|
||||
/* by secure world */
|
||||
compatible = "fsl,sec-v4.0-ctrl";
|
||||
reg = <0x2140000 0x1000>;
|
||||
secure-status = "okay";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sec_jr0: jr0@1000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
sec_jr1: jr1@2000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
sec_jr2: jr2@3000 {
|
||||
compatible = "fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
usbotg1: usb@02184000 {
|
||||
compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
|
||||
|
|
@ -781,8 +960,18 @@
|
|||
<&clks IMX6UL_CLK_ENET_REF>;
|
||||
clock-names = "ipg", "ahb", "ptp",
|
||||
"enet_clk_ref", "enet_out";
|
||||
stop-mode = <&gpr 0x10 3>;
|
||||
fsl,num-tx-queues=<1>;
|
||||
fsl,num-rx-queues=<1>;
|
||||
fsl,magic-packet;
|
||||
fsl,wakeup_irq = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sim1: sim@0218c000 {
|
||||
compatible = "fsl,imx6ul-sim";
|
||||
reg = <0x0218c000 0x4000>;
|
||||
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -852,11 +1041,56 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
romcp@021ac000 {
|
||||
compatible = "fsl,imx6ul-romcp", "syscon";
|
||||
reg = <0x021ac000 0x4000>;
|
||||
};
|
||||
|
||||
mmdc: mmdc@021b0000 {
|
||||
compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
|
||||
reg = <0x021b0000 0x4000>;
|
||||
};
|
||||
|
||||
sim2: sim@021b4000 {
|
||||
compatible = "fsl,imx6ul-sim";
|
||||
reg = <0x021b4000 0x4000>;
|
||||
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_SIM2>;
|
||||
clock-names = "sim";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
weim: weim@021b8000 {
|
||||
compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
|
||||
reg = <0x021b8000 0x4000>;
|
||||
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_DUMMY>;
|
||||
};
|
||||
|
||||
ocotp: ocotp-ctrl@021bc000 {
|
||||
compatible = "fsl,imx6ul-ocotp", "syscon";
|
||||
reg = <0x021bc000 0x4000>;
|
||||
clocks = <&clks IMX6UL_CLK_OCOTP>;
|
||||
};
|
||||
|
||||
csu: csu@021c0000 {
|
||||
compatible = "fsl,imx6ul-csu";
|
||||
reg = <0x021c0000 0x4000>;
|
||||
interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
csi: csi@021c4000 {
|
||||
compatible = "fsl,imx6ul-csi", "fsl,imx6s-csi";
|
||||
reg = <0x021c4000 0x4000>;
|
||||
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_DUMMY>,
|
||||
<&clks IMX6UL_CLK_CSI>,
|
||||
<&clks IMX6UL_CLK_DUMMY>;
|
||||
clock-names = "disp-axi", "csi_mclk", "disp_dcic";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
lcdif: lcdif@021c8000 {
|
||||
compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
|
||||
reg = <0x021c8000 0x4000>;
|
||||
|
|
@ -881,47 +1115,65 @@
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
pxp: pxp@021cc000 {
|
||||
compatible = "fsl,imx6ul-pxp-dma", "fsl,imx6sl-pxp-dma", "fsl,imx6dl-pxp-dma";
|
||||
reg = <0x021cc000 0x4000>;
|
||||
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_PXP>,
|
||||
<&clks IMX6UL_CLK_DUMMY>;
|
||||
clock-names = "pxp-axi", "disp-axi";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart2: serial@021e8000 {
|
||||
compatible = "fsl,imx6ul-uart",
|
||||
"fsl,imx6q-uart";
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021e8000 0x4000>;
|
||||
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_UART2_IPG>,
|
||||
<&clks IMX6UL_CLK_UART2_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@021ec000 {
|
||||
compatible = "fsl,imx6ul-uart",
|
||||
"fsl,imx6q-uart";
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021ec000 0x4000>;
|
||||
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_UART3_IPG>,
|
||||
<&clks IMX6UL_CLK_UART3_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart4: serial@021f0000 {
|
||||
compatible = "fsl,imx6ul-uart",
|
||||
"fsl,imx6q-uart";
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f0000 0x4000>;
|
||||
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_UART4_IPG>,
|
||||
<&clks IMX6UL_CLK_UART4_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart5: serial@021f4000 {
|
||||
compatible = "fsl,imx6ul-uart",
|
||||
"fsl,imx6q-uart";
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021f4000 0x4000>;
|
||||
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_UART5_IPG>,
|
||||
<&clks IMX6UL_CLK_UART5_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
|
|
@ -937,12 +1189,14 @@
|
|||
|
||||
uart6: serial@021fc000 {
|
||||
compatible = "fsl,imx6ul-uart",
|
||||
"fsl,imx6q-uart";
|
||||
"fsl,imx6q-uart", "fsl,imx21-uart";
|
||||
reg = <0x021fc000 0x4000>;
|
||||
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&clks IMX6UL_CLK_UART6_IPG>,
|
||||
<&clks IMX6UL_CLK_UART6_SERIAL>;
|
||||
clock-names = "ipg", "per";
|
||||
dmas = <&sdma 0 4 0>, <&sdma 47 4 0>;
|
||||
dma-names = "rx", "tx";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
|
|
|||
Loading…
Reference in New Issue