pinmux fixes
This commit is contained in:
mr
parent
f5a8f7e759
commit
c306eb66df
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@ -51,6 +51,9 @@ DECLARE_GLOBAL_DATA_PTR;
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#define NETBIRD_GPIO_RST_GSM_N GPIO_TO_PIN(1, 24)
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#define NETBIRD_GPIO_WLAN_EN GPIO_TO_PIN(3, 10)
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#define NETBIRD_GPIO_BT_EN GPIO_TO_PIN(3, 4)
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#define NETBIRD_GPIO_EN_GPS_ANT GPIO_TO_PIN(2, 24)
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#define NETBIRD_GPIO_LED_A GPIO_TO_PIN(1, 14)
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#define NETBIRD_GPIO_LED_B GPIO_TO_PIN(1, 15)
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#if defined(CONFIG_SPL_BUILD) || \
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(defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_DM_ETH))
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@ -577,6 +580,7 @@ int board_init(void)
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#endif
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if (board_is_nbhw16()) {
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REQUEST_AND_SET_GPIO(NETBIRD_GPIO_LED_A);
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REQUEST_AND_SET_GPIO(NETBIRD_GPIO_RST_PHY_N);
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REQUEST_AND_SET_GPIO(NETBIRD_GPIO_RST_GSM_N);
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REQUEST_AND_SET_GPIO(NETBIRD_GPIO_WLAN_EN);
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@ -262,49 +262,93 @@ static struct module_pin_mux uart3_icev2_pin_mux[] = {
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{-1},
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};
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static struct module_pin_mux rmii0_pin_mux_netbird[] = {
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{OFFSET(mdio_clk), MODE(0) | PULLUDEN}, /* MDIO_CLK */
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{OFFSET(mdio_data), MODE(0) | PULLUP_EN | RXACTIVE }, /* MDIO_DATA */
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{OFFSET(mii1_crs), MODE(1) | PULLUDEN | RXACTIVE}, /* MII1_CRS */
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{OFFSET(mii1_rxerr), MODE(1) | PULLUDEN | RXACTIVE}, /* MII1_RXERR */
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{OFFSET(mii1_txen), MODE(1) | PULLUDEN}, /* MII1_TXEN */
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{OFFSET(mii1_txd0), MODE(1) | PULLUDEN}, /* MII1_TXD0 */
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{OFFSET(mii1_txd1), MODE(1) | PULLUDEN}, /* MII1_TXD1 */
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{OFFSET(mii1_rxd0), MODE(1) | PULLUDEN | RXACTIVE}, /* MII1_RXD0 */
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{OFFSET(mii1_rxd1), MODE(1) | PULLUDEN | RXACTIVE}, /* MII1_RXD1 */
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{OFFSET(rmii1_refclk), MODE(0) | PULLUDEN | RXACTIVE}, /* RMII1_REFCLK */
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static struct module_pin_mux uart0_netbird_pin_mux[] = {
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{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* UART0_RXD */
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{OFFSET(uart0_txd), (MODE(0) | PULLUDEN | PULLUP_EN)}, /* UART0_TXD */
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{-1},
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};
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static struct module_pin_mux rmii1_pin_mux_netbird[] = {
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{OFFSET(gpmc_a9), MODE(3) | PULLUDEN | RXACTIVE}, /* MII2_CRS */
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{OFFSET(gpmc_wpn), MODE(3) | PULLUDEN | RXACTIVE}, /* MII2_RXERR */
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{OFFSET(gpmc_a0), MODE(3) | PULLUDEN}, /* MII2_TXEN */
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{OFFSET(gpmc_a5), MODE(3) | PULLUDEN}, /* MII2_TXD0 */
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{OFFSET(gpmc_a4), MODE(3) | PULLUDEN}, /* MII2_TXD1 */
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{OFFSET(gpmc_a11), MODE(3) | PULLUDEN | RXACTIVE}, /* MII1_RXD0 */
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{OFFSET(gpmc_a10), MODE(3) | PULLUDEN | RXACTIVE}, /* MII1_RXD1 */
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{OFFSET(mii1_col), MODE(1) | PULLUDEN | RXACTIVE}, /* RMII1_REFCLK */
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static struct module_pin_mux uart1_netbird_pin_mux[] = {
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{OFFSET(uart1_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (D16) uart1_rxd.uart1_rxd */
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{OFFSET(uart1_txd), (MODE(0) | PULLUDEN | PULLUP_EN)}, /* (D15) uart1_txd.uart1_txd */
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{OFFSET(uart1_ctsn), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (D18) uart1_ctsn.uart1_ctsn */
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{OFFSET(uart1_rtsn), (MODE(0) | PULLUDEN | PULLUP_EN)}, /* (D17) uart1_rtsn.uart1_rtsn */
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{-1},
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};
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static struct module_pin_mux mmc0_sdio_pin_mux_netbird[] = {
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{OFFSET(mmc0_clk), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | PULLUP_EN | RXACTIVE)}, /* MMC0_CMD */
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{OFFSET(mmc0_dat0), (MODE(0) | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT0 */
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{OFFSET(mmc0_dat1), (MODE(0) | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat2), (MODE(0) | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat3), (MODE(0) | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT3 */
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static struct module_pin_mux rmii0_netbird_pin_mux[] = {
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{OFFSET(mii1_crs), MODE(1) | PULLUDDIS | RXACTIVE}, /* MII1_CRS */
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{OFFSET(mii1_rxerr), MODE(1) | PULLUDDIS | RXACTIVE}, /* MII1_RXERR */
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{OFFSET(mii1_txen), MODE(1) | PULLUDDIS }, /* MII1_TXEN */
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{OFFSET(mii1_txd0), MODE(1) | PULLUDDIS }, /* MII1_TXD0 */
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{OFFSET(mii1_txd1), MODE(1) | PULLUDDIS }, /* MII1_TXD1 */
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{OFFSET(mii1_rxd0), MODE(1) | PULLUDDIS | RXACTIVE }, /* MII1_RXD0 */
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{OFFSET(mii1_rxd1), MODE(1) | PULLUDDIS | RXACTIVE }, /* MII1_RXD1 */
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{OFFSET(rmii1_refclk), MODE(0) | PULLUDDIS | RXACTIVE}, /* RMII1_REFCLK */
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{OFFSET(mdio_clk), MODE(0) | PULLUDDIS }, /* MDIO_CLK */
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{OFFSET(mdio_data), MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE }, /* MDIO_DATA */
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{-1},
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};
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static struct module_pin_mux mmc1_emmc_pin_mux_netbird[] = {
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{OFFSET(gpmc_csn1), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* MMC1_CLK */
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{OFFSET(gpmc_csn2), (MODE(2) | PULLUP_EN | RXACTIVE)}, /* MMC1_CMD */
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{OFFSET(gpmc_ad0), (MODE(1) | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT0 */
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{OFFSET(gpmc_ad1), (MODE(1) | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT1 */
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{OFFSET(gpmc_ad2), (MODE(1) | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT2 */
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{OFFSET(gpmc_ad3), (MODE(1) | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */
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static struct module_pin_mux rmii1_netbird_pin_mux[] = {
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{OFFSET(gpmc_a9), MODE(3) | PULLUDDIS | RXACTIVE}, /* MII2_CRS */
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{OFFSET(gpmc_wpn), MODE(3) | PULLUDDIS | RXACTIVE}, /* MII2_RXERR */
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{OFFSET(gpmc_a0), MODE(3) | PULLUDDIS}, /* MII2_TXEN */
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{OFFSET(gpmc_a5), MODE(3) | PULLUDDIS}, /* MII2_TXD0 */
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{OFFSET(gpmc_a4), MODE(3) | PULLUDDIS}, /* MII2_TXD1 */
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{OFFSET(gpmc_a11), MODE(3) | PULLUDDIS | RXACTIVE}, /* MII1_RXD0 */
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{OFFSET(gpmc_a10), MODE(3) | PULLUDDIS | RXACTIVE}, /* MII1_RXD1 */
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{OFFSET(mii1_col), MODE(1) | PULLUDDIS | RXACTIVE}, /* RMII1_REFCLK */
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{-1},
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};
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static struct module_pin_mux mmc0_sdio_netbird_pin_mux[] = {
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{OFFSET(mmc0_clk), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC0_CLK */
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{OFFSET(mmc0_cmd), (MODE(0) | PULLUDEN | PULLUP_EN)}, /* MMC0_CMD */
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{OFFSET(mmc0_dat0), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT0 */
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{OFFSET(mmc0_dat1), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT1 */
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{OFFSET(mmc0_dat2), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT2 */
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{OFFSET(mmc0_dat3), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC0_DAT3 */
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{-1},
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};
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static struct module_pin_mux mmc1_emmc_netbird_pin_mux[] = {
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{OFFSET(gpmc_csn1), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_CLK */
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{OFFSET(gpmc_csn2), (MODE(2) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* MMC1_CMD */
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{OFFSET(gpmc_ad0), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT0 */
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{OFFSET(gpmc_ad1), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT1 */
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{OFFSET(gpmc_ad2), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT2 */
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{OFFSET(gpmc_ad3), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad4), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad5), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad6), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */
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{OFFSET(gpmc_ad7), (MODE(1) | PULLUDEN | PULLUP_EN | RXACTIVE )}, /* MMC1_DAT3 */
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{-1},
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};
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static struct module_pin_mux gpio_netbird_pin_mux[] = {
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/* Bank 0 */
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{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDDIS | RXACTIVE)}, /* (C18) eCAP0_in_PWM0_out.gpio0[7] */ /* PWM */
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{OFFSET(mii1_txd3), (MODE(7) | PULLUDDIS)}, /* (J18) gmii1_txd3.gpio0[16] */ /* RST_PHY~ */
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{OFFSET(gpmc_ad11), (MODE(7) | PULLUDDIS)}, /* (U12) gpmc_ad11.gpio0[27] */ /* RST_EXT~ */
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/* Bank 1 */
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{OFFSET(gpmc_ad13), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (R12) gpmc_ad13.gpio1[13] */ /* BUTTON */
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{OFFSET(gpmc_ad14), (MODE(7) | PULLUDDIS)}, /* (V13) gpmc_ad14.gpio1[14] */ /* LED_A */
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{OFFSET(gpmc_ad15), (MODE(7) | PULLUDDIS)}, /* (U13) gpmc_ad15.gpio1[15] */ /* LED_B */
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{OFFSET(gpmc_a6), (MODE(7) | PULLUDDIS)}, /* (U15) gpmc_a6.gpio1[22] */ /* GSM_PWR_EN */
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{OFFSET(gpmc_a8), (MODE(7) | PULLUDDIS)}, /* (V16) gpmc_a8.gpio1[24] */ /* RST_GSM~ */
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/* Bank 2 */
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{OFFSET(lcd_pclk), (MODE(7) | PULLUDDIS)}, /* (V5) lcd_pclk.gpio2[24] */ /* EN_GPS_ANT */
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/* Bank 3 */
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{OFFSET(mii1_rxdv), (MODE(7) | PULLUDDIS)}, /* (J17) gmii1_rxdv.gpio3[4] */ /* BT_EN */
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{OFFSET(mii1_rxdv), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)}, /* (K18) gmii1_txclk.gpio3[9] */ /* WLAN_IRQ */
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{OFFSET(mii1_rxdv), (MODE(7) | PULLUDDIS)}, /* (L18) gmii1_rxclk.gpio3[10] */ /* WLAN_EN */
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{-1},
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};
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static struct module_pin_mux usb_netbird_pin_mux[] = {
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{OFFSET(usb0_drvvbus), (MODE(0) | PULLUDEN | PULLDOWN_EN)}, /* (F16) USB0_DRVVBUS.USB0_DRVVBUS */ /* PWM */
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{OFFSET(usb1_drvvbus), (MODE(0) | PULLUDDIS | PULLDOWN_EN)}, /* (F15) USB1_DRVVBUS.USB1_DRVVBUS */ /* RST_PHY~ */
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{-1},
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};
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@ -317,12 +361,20 @@ void enable_norboot_pin_mux(void)
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void enable_uart0_pin_mux(void)
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{
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configure_module_pin_mux(uart0_pin_mux);
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if (board_is_nbhw16()) {
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configure_module_pin_mux(uart0_netbird_pin_mux);
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} else {
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configure_module_pin_mux(uart0_pin_mux);
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}
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}
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void enable_uart1_pin_mux(void)
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{
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configure_module_pin_mux(uart1_pin_mux);
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if (board_is_nbhw16()) {
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configure_module_pin_mux(uart1_netbird_pin_mux);
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} else {
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configure_module_pin_mux(uart1_pin_mux);
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}
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}
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void enable_uart2_pin_mux(void)
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@ -438,10 +490,12 @@ void enable_board_pin_mux(void)
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#endif
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} else if (board_is_nbhw16()) {
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/* Netbird board */
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configure_module_pin_mux(rmii0_pin_mux_netbird);
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configure_module_pin_mux(rmii1_pin_mux_netbird);
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configure_module_pin_mux(mmc0_sdio_pin_mux_netbird);
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configure_module_pin_mux(mmc1_emmc_pin_mux_netbird);
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configure_module_pin_mux(gpio_netbird_pin_mux);
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configure_module_pin_mux(rmii0_netbird_pin_mux);
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configure_module_pin_mux(rmii1_netbird_pin_mux);
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configure_module_pin_mux(mmc0_sdio_netbird_pin_mux);
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configure_module_pin_mux(mmc1_emmc_netbird_pin_mux);
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configure_module_pin_mux(usb_netbird_pin_mux);
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} else if (board_is_icev2()) {
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configure_module_pin_mux(mmc0_pin_mux);
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configure_module_pin_mux(gpio0_18_pin_mux);
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