LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

rockchip: px30: Add support for using UART3 as debug UART 

Some generic PX30 SoMs found in the wild use UART3 as their debug output
instead of UART2 (used for MMC) and UART5.

Make it possible to use UART3 as early debug output, with the associated
clock and pinmux configuration. Two sets of output pins are supported (M0/M1).

Future users should also note that the pinmux default in the dts is to use
the M1 pins while the Kconfig option takes M0 as a default.

Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
This commit is contained in:
Paul Kocialkowski 2019-11-28 15:27:52 +01:00 committed by Kever Yang
parent ec4fafdf1f
commit c541bfda2f
2 changed files with 96 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
arch/arm/include/asm/arch-rockchip/cru_px30.h
View File

@ -357,6 +357,25 @@ enum {
UART2_DIVNP5_SHIFT = 0,
UART2_DIVNP5_MASK = 0x1f << UART2_DIVNP5_SHIFT,
/* CRU_CLK_SEL40_CON */
UART3_PLL_SEL_SHIFT = 14,
UART3_PLL_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT,
UART3_PLL_SEL_GPLL = 0,
UART3_PLL_SEL_24M,
UART3_PLL_SEL_480M,
UART3_PLL_SEL_NPLL,
UART3_DIV_CON_SHIFT = 0,
UART3_DIV_CON_MASK = 0x1f << UART3_DIV_CON_SHIFT,
/* CRU_CLK_SEL41_CON */
UART3_CLK_SEL_SHIFT = 14,
UART3_CLK_SEL_MASK = 3 << UART3_PLL_SEL_SHIFT,
UART3_CLK_SEL_UART3 = 0,
UART3_CLK_SEL_UART3_NP5,
UART3_CLK_SEL_UART3_FRAC,
UART3_DIVNP5_SHIFT = 0,
UART3_DIVNP5_MASK = 0x1f << UART3_DIVNP5_SHIFT,
/* CRU_CLK_SEL46_CON */
UART5_PLL_SEL_SHIFT = 14,
UART5_PLL_SEL_MASK = 3 << UART5_PLL_SEL_SHIFT,

77
arch/arm/mach-rockchip/px30/px30.c
View File

@ -37,6 +37,7 @@ static struct mm_region px30_mem_map[] = {
struct mm_region *mem_map = px30_mem_map;
#define PMU_PWRDN_CON 0xff000018
#define PMUGRF_BASE 0xff010000
#define GRF_BASE 0xff140000
#define CRU_BASE 0xff2b0000
#define VIDEO_PHY_BASE 0xff2e0000
@ -49,6 +50,23 @@ struct mm_region *mem_map = px30_mem_map;
#define QOS_PRIORITY_LEVEL(h, l) ((((h) & 3) << 8) | ((l) & 3))
/* GRF_GPIO1BH_IOMUX */
enum {
GPIO1B7_SHIFT = 12,
GPIO1B7_MASK = 0xf << GPIO1B7_SHIFT,
GPIO1B7_GPIO = 0,
GPIO1B7_FLASH_RDN,
GPIO1B7_UART3_RXM1,
GPIO1B7_SPI0_CLK,
GPIO1B6_SHIFT = 8,
GPIO1B6_MASK = 0xf << GPIO1B6_SHIFT,
GPIO1B6_GPIO = 0,
GPIO1B6_FLASH_CS1,
GPIO1B6_UART3_TXM1,
GPIO1B6_SPI0_CSN,
};
/* GRF_GPIO1CL_IOMUX */
enum {
GPIO1C1_SHIFT = 4,
@ -128,6 +146,23 @@ enum {
GPIO3A1_UART5_RX = 4,
};
/* PMUGRF_GPIO0CL_IOMUX */
enum {
GPIO0C1_SHIFT = 2,
GPIO0C1_MASK = 0x3 << GPIO0C1_SHIFT,
GPIO0C1_GPIO = 0,
GPIO0C1_PWM_3,
GPIO0C1_UART3_RXM0,
GPIO0C1_PMU_DEBUG4,
GPIO0C0_SHIFT = 0,
GPIO0C0_MASK = 0x3 << GPIO0C0_SHIFT,
GPIO0C0_GPIO = 0,
GPIO0C0_PWM_1,
GPIO0C0_UART3_TXM0,
GPIO0C0_PMU_DEBUG3,
};
int arch_cpu_init(void)
{
static struct px30_grf * const grf = (void *)GRF_BASE;
@ -175,6 +210,11 @@ int arch_cpu_init(void)
#ifdef CONFIG_DEBUG_UART_BOARD_INIT
void board_debug_uart_init(void)
{
#if defined(CONFIG_DEBUG_UART_BASE) && \
(CONFIG_DEBUG_UART_BASE == 0xff168000) && \
(CONFIG_DEBUG_UART_CHANNEL != 1)
static struct px30_pmugrf * const pmugrf = (void *)PMUGRF_BASE;
#endif
static struct px30_grf * const grf = (void *)GRF_BASE;
static struct px30_cru * const cru = (void *)CRU_BASE;
@ -191,6 +231,43 @@ void board_debug_uart_init(void)
GPIO1C1_MASK | GPIO1C0_MASK,
GPIO1C1_UART1_TX << GPIO1C1_SHIFT |
GPIO1C0_UART1_RX << GPIO1C0_SHIFT);
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff168000)
/* GRF_IOFUNC_CON0 */
enum {
CON_IOMUX_UART3SEL_SHIFT = 9,
CON_IOMUX_UART3SEL_MASK = 1 << CON_IOMUX_UART3SEL_SHIFT,
CON_IOMUX_UART3SEL_M0 = 0,
CON_IOMUX_UART3SEL_M1,
};
/* uart_sel_clk default select 24MHz */
rk_clrsetreg(&cru->clksel_con[40],
UART3_PLL_SEL_MASK | UART3_DIV_CON_MASK,
UART3_PLL_SEL_24M << UART3_PLL_SEL_SHIFT | 0);
rk_clrsetreg(&cru->clksel_con[41],
UART3_CLK_SEL_MASK,
UART3_CLK_SEL_UART3 << UART3_CLK_SEL_SHIFT);
#if (CONFIG_DEBUG_UART_CHANNEL == 1)
rk_clrsetreg(&grf->iofunc_con0,
CON_IOMUX_UART3SEL_MASK,
CON_IOMUX_UART3SEL_M1 << CON_IOMUX_UART3SEL_SHIFT);
rk_clrsetreg(&grf->gpio1bh_iomux,
GPIO1B7_MASK | GPIO1B6_MASK,
GPIO1B7_UART3_RXM1 << GPIO1B7_SHIFT |
GPIO1B6_UART3_TXM1 << GPIO1B6_SHIFT);
#else
rk_clrsetreg(&grf->iofunc_con0,
CON_IOMUX_UART3SEL_MASK,
CON_IOMUX_UART3SEL_M0 << CON_IOMUX_UART3SEL_SHIFT);
rk_clrsetreg(&pmugrf->gpio0cl_iomux,
GPIO0C1_MASK | GPIO0C0_MASK,
GPIO0C1_UART3_RXM0 << GPIO0C1_SHIFT |
GPIO0C0_UART3_TXM0 << GPIO0C0_SHIFT);
#endif /* CONFIG_DEBUG_UART_CHANNEL == 1 */
#elif defined(CONFIG_DEBUG_UART_BASE) && (CONFIG_DEBUG_UART_BASE == 0xff178000)
/* uart_sel_clk default select 24MHz */
rk_clrsetreg(&cru->clksel_con[46],