imx6: wandboard: convert to DM_I2C
Allow building with DM_I2C enabled. Signed-off-by: Anatolij Gustschin <agust@denx.de>
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					@ -355,8 +355,21 @@ static void do_enable_hdmi(struct display_info_t const *dev)
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static int detect_i2c(struct display_info_t const *dev)
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					static int detect_i2c(struct display_info_t const *dev)
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{
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					{
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					#ifdef CONFIG_DM_I2C
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						struct udevice *bus, *udev;
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						int rc;
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						rc = uclass_get_device_by_seq(UCLASS_I2C, dev->bus, &bus);
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						if (rc)
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							return rc;
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						rc = dm_i2c_probe(bus, dev->addr, 0, &udev);
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						if (rc)
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							return 0;
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						return 1;
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					#else
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	return (0 == i2c_set_bus_num(dev->bus)) &&
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						return (0 == i2c_set_bus_num(dev->bus)) &&
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			(0 == i2c_probe(dev->addr));
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								(0 == i2c_probe(dev->addr));
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					#endif
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}
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					}
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static void enable_fwadapt_7wvga(struct display_info_t const *dev)
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					static void enable_fwadapt_7wvga(struct display_info_t const *dev)
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					@ -547,13 +560,13 @@ int board_init(void)
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	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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						gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
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#if defined(CONFIG_VIDEO_IPUV3)
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					#if defined(CONFIG_VIDEO_IPUV3)
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	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
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						setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
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	if (is_mx6dq() || is_mx6dqp()) {
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						if (is_mx6dq() || is_mx6dqp()) {
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		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c2_pad_info);
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							setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6q_i2c2_pad_info);
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		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6q_i2c3_pad_info);
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							setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6q_i2c3_pad_info);
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	} else {
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						} else {
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		setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
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							setup_i2c(1, CONFIG_SYS_MXC_I2C1_SPEED, 0x7f, &mx6dl_i2c2_pad_info);
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		setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
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							setup_i2c(2, CONFIG_SYS_MXC_I2C2_SPEED, 0x7f, &mx6dl_i2c3_pad_info);
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	}
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						}
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	setup_display();
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						setup_display();
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					@ -39,6 +39,11 @@ CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
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CONFIG_DM=y
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					CONFIG_DM=y
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CONFIG_DWC_AHSATA=y
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					CONFIG_DWC_AHSATA=y
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CONFIG_DM_GPIO=y
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					CONFIG_DM_GPIO=y
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					CONFIG_DM_I2C=y
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					CONFIG_SYS_I2C_MXC=y
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					CONFIG_SYS_I2C_MXC_I2C1=y
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					CONFIG_SYS_I2C_MXC_I2C2=y
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					CONFIG_SYS_I2C_MXC_I2C3=y
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CONFIG_FSL_ESDHC=y
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					CONFIG_FSL_ESDHC=y
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CONFIG_PHYLIB=y
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					CONFIG_PHYLIB=y
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CONFIG_MII=y
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					CONFIG_MII=y
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					@ -32,14 +32,6 @@
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#define CONFIG_SYS_MEMTEST_START	0x10000000
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					#define CONFIG_SYS_MEMTEST_START	0x10000000
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#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
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					#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 500 * SZ_1M)
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/* I2C Configs */
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#define CONFIG_SYS_I2C
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#define CONFIG_SYS_I2C_MXC
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#define CONFIG_SYS_I2C_MXC_I2C1		/* enable I2C bus 1 */
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#define CONFIG_SYS_I2C_MXC_I2C2		/* enable I2C bus 2 */
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#define CONFIG_SYS_I2C_MXC_I2C3		/* enable I2C bus 3 */
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#define CONFIG_SYS_I2C_SPEED		100000
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/* MMC Configuration */
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					/* MMC Configuration */
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#define CONFIG_SYS_FSL_USDHC_NUM	2
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					#define CONFIG_SYS_FSL_USDHC_NUM	2
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#define CONFIG_SYS_FSL_ESDHC_ADDR	0
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					#define CONFIG_SYS_FSL_ESDHC_ADDR	0
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