ddr: j721e: Update DDRSS configuration for J721E

DDR configuration for a Jacinto specific board is generated using the
Jacinto 7 DDRSS RegConfig tool. Latest version of the tool is v0.9.1.
It can be obtained from https://www.ti.com/product/TDA4VM#tech-docs under
Technical Documentation > Application note > Jacinto7 DDRSS Register
Configuration Tool.

Updating to contain the generated config of the latest version of the tool.

Signed-off-by: Neha Malcom Francis <n-francis@ti.com>

arch/arm/dts/k3-j721e-ddr-evm-lp4-4266.dtsi

@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
- * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.6.0
- * This file was generated on 06/01/2021
+ * This file was generated by the Jacinto7_DDRSS_RegConfigTool, Revision: 0.9.1
+ * This file was generated on 07/17/2022
 */
 
 #define DDRSS_PLL_FHS_CNT 10
@@ -239,17 +239,17 @@
 #define DDRSS_CTL_226_DATA 0x00000000
 #define DDRSS_CTL_227_DATA 0x15110000
 #define DDRSS_CTL_228_DATA 0x00040C18
-#define DDRSS_CTL_229_DATA 0x00000000
-#define DDRSS_CTL_230_DATA 0x00000000
+#define DDRSS_CTL_229_DATA 0xF000C000
+#define DDRSS_CTL_230_DATA 0x0000F000
 #define DDRSS_CTL_231_DATA 0x00000000
 #define DDRSS_CTL_232_DATA 0x00000000
-#define DDRSS_CTL_233_DATA 0x00000000
-#define DDRSS_CTL_234_DATA 0x00000000
+#define DDRSS_CTL_233_DATA 0xC0000000
+#define DDRSS_CTL_234_DATA 0xF000F000
 #define DDRSS_CTL_235_DATA 0x00000000
 #define DDRSS_CTL_236_DATA 0x00000000
 #define DDRSS_CTL_237_DATA 0x00000000
-#define DDRSS_CTL_238_DATA 0x00000000
-#define DDRSS_CTL_239_DATA 0x00000000
+#define DDRSS_CTL_238_DATA 0xF000C000
+#define DDRSS_CTL_239_DATA 0x0000F000
 #define DDRSS_CTL_240_DATA 0x00000000
 #define DDRSS_CTL_241_DATA 0x00000000
 #define DDRSS_CTL_242_DATA 0x00030000
@@ -277,7 +277,7 @@
 #define DDRSS_CTL_264_DATA 0x00000040
 #define DDRSS_CTL_265_DATA 0x006B0003
 #define DDRSS_CTL_266_DATA 0x0100006B
-#define DDRSS_CTL_267_DATA 0x00000000
+#define DDRSS_CTL_267_DATA 0x03030303
 #define DDRSS_CTL_268_DATA 0x01010000
 #define DDRSS_CTL_269_DATA 0x00000202
 #define DDRSS_CTL_270_DATA 0x00000FFF
@@ -803,8 +803,8 @@
 #define DDRSS_PHY_29_DATA 0x00000808
 #define DDRSS_PHY_30_DATA 0x0F000000
 #define DDRSS_PHY_31_DATA 0x00000F0F
-#define DDRSS_PHY_32_DATA 0x10200000
-#define DDRSS_PHY_33_DATA 0x0C002007
+#define DDRSS_PHY_32_DATA 0x10400000
+#define DDRSS_PHY_33_DATA 0x0C002006
 #define DDRSS_PHY_34_DATA 0x00000000
 #define DDRSS_PHY_35_DATA 0x00000000
 #define DDRSS_PHY_36_DATA 0x55555555
@@ -1059,8 +1059,8 @@
 #define DDRSS_PHY_285_DATA 0x00000808
 #define DDRSS_PHY_286_DATA 0x0F000000
 #define DDRSS_PHY_287_DATA 0x00000F0F
-#define DDRSS_PHY_288_DATA 0x10200000
-#define DDRSS_PHY_289_DATA 0x0C002007
+#define DDRSS_PHY_288_DATA 0x10400000
+#define DDRSS_PHY_289_DATA 0x0C002006
 #define DDRSS_PHY_290_DATA 0x00000000
 #define DDRSS_PHY_291_DATA 0x00000000
 #define DDRSS_PHY_292_DATA 0x55555555
@@ -1315,8 +1315,8 @@
 #define DDRSS_PHY_541_DATA 0x00000808
 #define DDRSS_PHY_542_DATA 0x0F000000
 #define DDRSS_PHY_543_DATA 0x00000F0F
-#define DDRSS_PHY_544_DATA 0x10200000
-#define DDRSS_PHY_545_DATA 0x0C002007
+#define DDRSS_PHY_544_DATA 0x10400000
+#define DDRSS_PHY_545_DATA 0x0C002006
 #define DDRSS_PHY_546_DATA 0x00000000
 #define DDRSS_PHY_547_DATA 0x00000000
 #define DDRSS_PHY_548_DATA 0x55555555
@@ -1571,8 +1571,8 @@
 #define DDRSS_PHY_797_DATA 0x00000808
 #define DDRSS_PHY_798_DATA 0x0F000000
 #define DDRSS_PHY_799_DATA 0x00000F0F
-#define DDRSS_PHY_800_DATA 0x10200000
-#define DDRSS_PHY_801_DATA 0x0C002007
+#define DDRSS_PHY_800_DATA 0x10400000
+#define DDRSS_PHY_801_DATA 0x0C002006
 #define DDRSS_PHY_802_DATA 0x00000000
 #define DDRSS_PHY_803_DATA 0x00000000
 #define DDRSS_PHY_804_DATA 0x55555555