mtd: spi-nor-core: Do not start or end writes at odd address in DTR mode
On DTR capable flashes like Micron Xcella the writes cannot start or end at an odd address in DTR mode. Extra 0xff bytes need to be prepended or appended respectively to make sure both the start and end addresses are even. Signed-off-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Apurva Nandan <a-nandan@ti.com> Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
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@ -1760,11 +1760,62 @@ static int spi_nor_write(struct mtd_info *mtd, loff_t to, size_t len,
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if (ret < 0)
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if (ret < 0)
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return ret;
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return ret;
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#endif
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#endif
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write_enable(nor);
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write_enable(nor);
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ret = nor->write(nor, addr, page_remain, buf + i);
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if (ret < 0)
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/*
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goto write_err;
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* On DTR capable flashes like Micron Xcella the writes cannot
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written = ret;
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* start or end at an odd address in DTR mode. So we need to
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* append or prepend extra 0xff bytes to make sure the start
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* address and end address are even.
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*/
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if (spi_nor_protocol_is_dtr(nor->write_proto) &&
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((addr | page_remain) & 1)) {
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u_char *tmp;
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size_t extra_bytes = 0;
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tmp = kmalloc(nor->page_size, 0);
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if (!tmp) {
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ret = -ENOMEM;
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goto write_err;
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}
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/* Prepend a 0xff byte if the start address is odd. */
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if (addr & 1) {
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tmp[0] = 0xff;
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memcpy(tmp + 1, buf + i, page_remain);
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addr--;
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page_remain++;
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extra_bytes++;
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} else {
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memcpy(tmp, buf + i, page_remain);
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}
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/* Append a 0xff byte if the end address is odd. */
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if ((addr + page_remain) & 1) {
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tmp[page_remain + extra_bytes] = 0xff;
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extra_bytes++;
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page_remain++;
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}
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ret = nor->write(nor, addr, page_remain, tmp);
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kfree(tmp);
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if (ret < 0)
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goto write_err;
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/*
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* We write extra bytes but they are not part of the
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* original write.
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*/
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written = ret - extra_bytes;
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} else {
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ret = nor->write(nor, addr, page_remain, buf + i);
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if (ret < 0)
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goto write_err;
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written = ret;
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}
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ret = spi_nor_wait_till_ready(nor);
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ret = spi_nor_wait_till_ready(nor);
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if (ret)
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if (ret)
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