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Patches by Stephan Linz, 11 Dec 2003: 

- more documentation for NIOS port
- new struct nios_pio_t, struct nios_spi_t
- Reconfiguration for NIOS Development Kit DK1C20:
  o move board related code from board/dk1c20
    to board/altera/dk1c20
  o create a new common source path board/altera/common
    and move generic flash access stuff into it
  o change/expand configuration file DK1C20.h
- Add support for NIOS Development Kit DK1S10
- Add status LED support for NIOS systems
- Add dual 7-segment LED support for Altera NIOS DevKits
This commit is contained in:
wdenk 2004-01-03 19:43:48 +00:00
parent 3a473b2a65
commit c935d3bd8b
41 changed files with 4198 additions and 124 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
CHANGELOG
View File

@ -2,6 +2,19 @@
Changes since U-Boot 1.0.0:
======================================================================
* Patches by Stephan Linz, 11 Dec 2003:
- more documentation for NIOS port
- new struct nios_pio_t, struct nios_spi_t
- Reconfiguration for NIOS Development Kit DK1C20:
o move board related code from board/dk1c20
to board/altera/dk1c20
o create a new common source path board/altera/common
and move generic flash access stuff into it
o change/expand configuration file DK1C20.h
- Add support for NIOS Development Kit DK1S10
- Add status LED support for NIOS systems
- Add dual 7-segment LED support for Altera NIOS DevKits
* Patch by Ronen Shitrit, 10 Dec 2003:
Add support for the Marvell DB64360 / DB64460 development boards

5
CREDITS
View File

@ -208,6 +208,11 @@ E: team@leox.org
D: Support for LEOX boards, DS164x RTC
W: http://www.leox.org
N: Stephan Linz
E: linz@li-pro.net
D: Support for Nios Stratix Development Kit (DK-1S10)
W: http://www.li-pro.net
N: Raymond Lo
E: lo@routefree.com
D: Support for DOS partitions

4
MAINTAINERS
View File

@ -362,6 +362,10 @@ Thomas Lange <thomas@corelatus.se>
# Board CPU #
#########################################################################
Stephan Linz <linz@li-pro.net>
DK1S10 Nios-32
Scott McNutt <smcnutt@psyent.com>
DK1C20 Nios-32

10
MAKEALL
View File

@ -169,6 +169,15 @@ LIST_I486="sc520_cdp sc520_spunk sc520_spunk_rel"
LIST_x86="${LIST_I486}"
#########################################################################
## NIOS Systems
#########################################################################
LIST_nios=" \
DK1C20 DK1C20_standard_32 \
DK1S10 DK1S10_standard_32 \
"
#-----------------------------------------------------------------------
#----- for now, just run PPC by default -----
@ -194,6 +203,7 @@ do
ppc|5xx|5xxx|8xx|824x|8260|85xx|4xx|7xx|74xx| \
arm|SA|ARM7|ARM9|pxa|ixp| \
mips| \
nios| \
x86|I486)
for target in `eval echo '$LIST_'${arg}`
do

35
Makefile
View File

@ -1046,8 +1046,41 @@ purple_config : unconfig
## Nios32
#########################################################################
DK1C20_safe_32_config \
DK1C20_standard_32_config \
DK1C20_config: unconfig
@./mkconfig $(@:_config=) nios nios dk1c20
@ >include/config.h
@[ -z "$(findstring _safe_32,$@)" ] || \
{ echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \
echo "... NIOS 'safe_32' configuration" ; \
}
@[ -z "$(findstring _standard_32,$@)" ] || \
{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
echo "... NIOS 'standard_32' configuration" ; \
}
@[ -z "$(findstring DK1C20_config,$@)" ] || \
{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \
}
@./mkconfig -a DK1C20 nios nios dk1c20 altera
DK1S10_safe_32_config \
DK1S10_standard_32_config \
DK1S10_config: unconfig
@ >include/config.h
@[ -z "$(findstring _safe_32,$@)" ] || \
{ echo "#define CONFIG_NIOS_SAFE_32 1" >>include/config.h ; \
echo "... NIOS 'safe_32' configuration" ; \
}
@[ -z "$(findstring _standard_32,$@)" ] || \
{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
echo "... NIOS 'standard_32' configuration" ; \
}
@[ -z "$(findstring DK1S10_config,$@)" ] || \
{ echo "#define CONFIG_NIOS_STANDARD_32 1" >>include/config.h ; \
echo "... NIOS 'standard_32' configuration (DEFAULT)" ; \
}
@./mkconfig -a DK1S10 nios nios dk1s10 altera
#########################################################################

44
board/dk1c20/flash.c → board/altera/common/flash.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2000
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
@ -25,42 +25,8 @@
#include <common.h>
#include <nios.h>
/*---------------------------------------------------------------------*/
#define BANKSZ (8 * 1024 * 1024)
#define SECTSZ (64 * 1024)
#define USERFLASH (2 * 1024 * 1024) /* bottom 2 MB for user */
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
#define FLASH_WORD_SIZE unsigned char
/*---------------------------------------------------------------------*/
unsigned long flash_init (void)
{
int i;
unsigned long addr;
flash_info_t *fli = &flash_info[0];
fli->size = BANKSZ;
fli->sector_count = CFG_MAX_FLASH_SECT;
fli->flash_id = FLASH_MAN_AMD;
addr = CFG_FLASH_BASE;
for (i = 0; i < fli->sector_count; ++i) {
fli->start[i] = addr;
addr += SECTSZ;
/* Protect all but 2 MByte user area */
if (addr < (CFG_FLASH_BASE + USERFLASH))
fli->protect[i] = 0;
else
fli->protect[i] = 1;
}
return (BANKSZ);
}
/*--------------------------------------------------------------------*/
void flash_print_info (flash_info_t * info)
{
@ -102,8 +68,8 @@ void flash_print_info (flash_info_t * info)
int flash_erase (flash_info_t * info, int s_first, int s_last)
{
volatile FLASH_WORD_SIZE *addr = (FLASH_WORD_SIZE *) (info->start[0]);
volatile FLASH_WORD_SIZE *addr2;
volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
volatile CFG_FLASH_WORD_SIZE *addr2;
int prot, sect;
int any = 0;
unsigned oldpri;
@ -141,7 +107,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
*/
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
*addr = 0xaa;
*addr = 0x55;
*addr = 0x80;
@ -156,7 +122,7 @@ int flash_erase (flash_info_t * info, int s_first, int s_last)
* we wait.
*/
if (any) {
addr2 = (FLASH_WORD_SIZE *) (info->start[sect]);
addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
start = get_timer (0);
while (*addr2 != 0xff) {
udelay (1000 * 1000);

220
board/altera/common/sevenseg.c Normal file
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@ -0,0 +1,220 @@
/*
* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
* Stephan Linz <linz@li-pro.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* common/sevenseg.c
*
* NIOS PIO based seven segment led support functions
*/
#include <common.h>
#include <nios-io.h>
#ifdef CONFIG_SEVENSEG
#define SEVENDEG_MASK_DP ((SEVENSEG_DIGIT_DP << 8) | SEVENSEG_DIGIT_DP)
#ifdef SEVENSEG_WRONLY /* emulate read access */
#if (SEVENSEG_ACTIVE == 0)
static unsigned int sevenseg_portval = ~0;
#else
static unsigned int sevenseg_portval = 0;
#endif
#endif
static int sevenseg_init_done = 0;
static inline void __sevenseg_set_masked (unsigned int mask, int value)
{
nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
#ifdef SEVENSEG_WRONLY /* emulate read access */
#if (SEVENSEG_ACTIVE == 0)
if (value)
sevenseg_portval &= ~mask;
else
sevenseg_portval |= mask;
#else
if (value)
sevenseg_portval |= mask;
else
sevenseg_portval &= ~mask;
#endif
piop->data = sevenseg_portval;
#else /* !SEVENSEG_WRONLY */
#if (SEVENSEG_ACTIVE == 0)
if (value)
piop->data &= ~mask;
else
piop->data |= mask;
#else
if (value)
piop->data |= mask;
else
piop->data &= ~mask;
#endif
#endif /* SEVENSEG_WRONLY */
}
static inline void __sevenseg_toggle_masked (unsigned int mask)
{
nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
#ifdef SEVENSEG_WRONLY /* emulate read access */
sevenseg_portval ^= mask;
piop->data = sevenseg_portval;
#else /* !SEVENSEG_WRONLY */
piop->data ^= mask;
#endif /* SEVENSEG_WRONLY */
}
static inline void __sevenseg_set (unsigned int value)
{
nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
#ifdef SEVENSEG_WRONLY /* emulate read access */
#if (SEVENSEG_ACTIVE == 0)
sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
| ((~value) & (~SEVENDEG_MASK_DP));
#else
sevenseg_portval = (sevenseg_portval & SEVENDEG_MASK_DP)
| (value);
#endif
piop->data = sevenseg_portval;
#else /* !SEVENSEG_WRONLY */
#if (SEVENSEG_ACTIVE == 0)
piop->data = (piop->data & SEVENDEG_MASK_DP)
| ((~value) & (~SEVENDEG_MASK_DP));
#else
piop->data = (piop->data & SEVENDEG_MASK_DP)
| (value);
#endif
#endif /* SEVENSEG_WRONLY */
}
static inline void __sevenseg_init (void)
{
nios_pio_t *piop = (nios_pio_t*)SEVENSEG_BASE;
__sevenseg_set(0);
#ifndef SEVENSEG_WRONLY /* setup direction */
piop->direction |= mask;
#endif /* SEVENSEG_WRONLY */
}
void sevenseg_set(int value)
{
unsigned char digits[] = {
SEVENSEG_DIGITS_0,
SEVENSEG_DIGITS_1,
SEVENSEG_DIGITS_2,
SEVENSEG_DIGITS_3,
SEVENSEG_DIGITS_4,
SEVENSEG_DIGITS_5,
SEVENSEG_DIGITS_6,
SEVENSEG_DIGITS_7,
SEVENSEG_DIGITS_8,
SEVENSEG_DIGITS_9,
SEVENSEG_DIGITS_A,
SEVENSEG_DIGITS_B,
SEVENSEG_DIGITS_C,
SEVENSEG_DIGITS_D,
SEVENSEG_DIGITS_E,
SEVENSEG_DIGITS_F
};
if (!sevenseg_init_done) {
__sevenseg_init();
sevenseg_init_done++;
}
switch (value & SEVENSEG_MASK_CTRL) {
case SEVENSEG_RAW:
__sevenseg_set( (
(digits[((value & SEVENSEG_MASK_VAL) >> 4)] << 8) |
digits[((value & SEVENSEG_MASK_VAL) & 0xf)] ) );
return;
break; /* paranoia */
case SEVENSEG_OFF:
__sevenseg_set(0);
__sevenseg_set_masked(SEVENDEG_MASK_DP, 0);
return;
break; /* paranoia */
case SEVENSEG_SET_DPL:
__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 1);
return;
break; /* paranoia */
case SEVENSEG_SET_DPH:
__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 1);
return;
break; /* paranoia */
case SEVENSEG_RES_DPL:
__sevenseg_set_masked(SEVENSEG_DIGIT_DP, 0);
return;
break; /* paranoia */
case SEVENSEG_RES_DPH:
__sevenseg_set_masked((SEVENSEG_DIGIT_DP << 8), 0);
return;
break; /* paranoia */
case SEVENSEG_TOG_DPL:
__sevenseg_toggle_masked(SEVENSEG_DIGIT_DP);
return;
break; /* paranoia */
case SEVENSEG_TOG_DPH:
__sevenseg_toggle_masked((SEVENSEG_DIGIT_DP << 8));
return;
break; /* paranoia */
case SEVENSEG_LO:
case SEVENSEG_HI:
case SEVENSEG_STR:
default:
break;
}
}
#endif /* CONFIG_SEVENSEG */

142
board/altera/common/sevenseg.h Normal file
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@ -0,0 +1,142 @@
/*
* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
* Stephan Linz <linz@li-pro.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* common/sevenseg.h
*
* NIOS PIO based seven segment led support functions
*/
#ifndef __DK1S10_SEVENSEG_H__
#define __DK1S10_SEVENSEG_H__
#ifdef CONFIG_SEVENSEG
/*
* 15 8 7 0
* |-----------------------|--------|
* | controll value | value |
* ----------------------------------
*/
#define SEVENSEG_RAW (int)(0) /* write out byte value (hex) */
#define SEVENSEG_OFF (int)( 1 << 8) /* display switch off */
#define SEVENSEG_SET_DPL (int)( 2 << 8) /* set dp low nibble */
#define SEVENSEG_SET_DPH (int)( 3 << 8) /* set dp high nibble */
#define SEVENSEG_RES_DPL (int)( 4 << 8) /* reset dp low nibble */
#define SEVENSEG_RES_DPH (int)( 5 << 8) /* reset dp high nibble */
#define SEVENSEG_TOG_DPL (int)( 6 << 8) /* toggle dp low nibble */
#define SEVENSEG_TOG_DPH (int)( 7 << 8) /* toggle dp high nibble */
#define SEVENSEG_LO (int)( 8 << 8) /* write out low nibble only */
#define SEVENSEG_HI (int)( 9 << 8) /* write out high nibble only */
#define SEVENSEG_STR (int)(10 << 8) /* write out a string */
#define SEVENSEG_MASK_VAL (0xff) /* only used by SEVENSEG_RAW */
#define SEVENSEG_MASK_CTRL (~SEVENSEG_MASK_VAL)
#ifdef SEVENSEG_DIGIT_HI_LO_EQUAL
#define SEVENSEG_DIGITS_0 ( SEVENSEG_DIGIT_A \
| SEVENSEG_DIGIT_B \
| SEVENSEG_DIGIT_C \
| SEVENSEG_DIGIT_D \
| SEVENSEG_DIGIT_E \
| SEVENSEG_DIGIT_F )
#define SEVENSEG_DIGITS_1 ( SEVENSEG_DIGIT_B \
| SEVENSEG_DIGIT_C )
#define SEVENSEG_DIGITS_2 ( SEVENSEG_DIGIT_A \
| SEVENSEG_DIGIT_B \
| SEVENSEG_DIGIT_D \
| SEVENSEG_DIGIT_E \
| SEVENSEG_DIGIT_G )
#define SEVENSEG_DIGITS_3 ( SEVENSEG_DIGIT_A \
| SEVENSEG_DIGIT_B \
| SEVENSEG_DIGIT_C \
| SEVENSEG_DIGIT_D \
| SEVENSEG_DIGIT_G )
#define SEVENSEG_DIGITS_4 ( SEVENSEG_DIGIT_B \
| SEVENSEG_DIGIT_C \
| SEVENSEG_DIGIT_F \
| SEVENSEG_DIGIT_G )
#define SEVENSEG_DIGITS_5 ( SEVENSEG_DIGIT_A \
| SEVENSEG_DIGIT_C \
| SEVENSEG_DIGIT_D \
| SEVENSEG_DIGIT_F \
| SEVENSEG_DIGIT_G )
#define SEVENSEG_DIGITS_6 ( SEVENSEG_DIGIT_A \
| SEVENSEG_DIGIT_C \
| SEVENSEG_DIGIT_D \
| SEVENSEG_DIGIT_E \
| SEVENSEG_DIGIT_F \
| SEVENSEG_DIGIT_G )
#define SEVENSEG_DIGITS_7 ( SEVENSEG_DIGIT_A \
| SEVENSEG_DIGIT_B \
| SEVENSEG_DIGIT_C )
#define SEVENSEG_DIGITS_8 ( SEVENSEG_DIGIT_A \
| SEVENSEG_DIGIT_B \
| SEVENSEG_DIGIT_C \
| SEVENSEG_DIGIT_D \
| SEVENSEG_DIGIT_E \
| SEVENSEG_DIGIT_F \
| SEVENSEG_DIGIT_G )
#define SEVENSEG_DIGITS_9 ( SEVENSEG_DIGIT_A \
| SEVENSEG_DIGIT_B \
| SEVENSEG_DIGIT_C \
| SEVENSEG_DIGIT_D \
| SEVENSEG_DIGIT_F \
| SEVENSEG_DIGIT_G )
#define SEVENSEG_DIGITS_A ( SEVENSEG_DIGIT_A \
| SEVENSEG_DIGIT_B \
| SEVENSEG_DIGIT_C \
| SEVENSEG_DIGIT_E \
| SEVENSEG_DIGIT_F \
| SEVENSEG_DIGIT_G )
#define SEVENSEG_DIGITS_B ( SEVENSEG_DIGIT_C \
| SEVENSEG_DIGIT_D \
| SEVENSEG_DIGIT_E \
| SEVENSEG_DIGIT_F \
| SEVENSEG_DIGIT_G )
#define SEVENSEG_DIGITS_C ( SEVENSEG_DIGIT_D \
| SEVENSEG_DIGIT_E \
| SEVENSEG_DIGIT_G )
#define SEVENSEG_DIGITS_D ( SEVENSEG_DIGIT_B \
| SEVENSEG_DIGIT_C \
| SEVENSEG_DIGIT_D \
| SEVENSEG_DIGIT_E \
| SEVENSEG_DIGIT_G )
#define SEVENSEG_DIGITS_E ( SEVENSEG_DIGIT_A \
| SEVENSEG_DIGIT_D \
| SEVENSEG_DIGIT_E \
| SEVENSEG_DIGIT_F \
| SEVENSEG_DIGIT_G )
#define SEVENSEG_DIGITS_F ( SEVENSEG_DIGIT_A \
| SEVENSEG_DIGIT_E \
| SEVENSEG_DIGIT_F \
| SEVENSEG_DIGIT_G )
#else /* !SEVENSEG_DIGIT_HI_LO_EQUAL */
#error SEVENSEG: different pin asssignments not supported
#endif
void sevenseg_set(int value);
#endif /* CONFIG_SEVENSEG */
#endif /* __DK1S10_SEVENSEG_H__ */

4
board/dk1c20/Makefile → board/altera/dk1c20/Makefile
View File

@ -1,5 +1,5 @@
#
# (C) Copyright 2001
# (C) Copyright 2001-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o flash.o
OBJS := $(BOARD).o flash.o misc.o
SOBJS = vectors.o

0
board/dk1c20/config.mk → board/altera/dk1c20/config.mk
View File

5
board/dk1c20/dk1c20.c → board/altera/dk1c20/dk1c20.c
View File

@ -22,6 +22,9 @@
*/
#include <common.h>
#if defined(CONFIG_SEVENSEG)
#include "../common/sevenseg.h"
#endif
void _default_hdlr (void)
{
@ -30,6 +33,8 @@ void _default_hdlr (void)
int board_pre_init (void)
{
/* init seven segment led display and switch off */
sevenseg_set(SEVENSEG_OFF);
return 0;
}

62
board/altera/dk1c20/flash.c Normal file
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@ -0,0 +1,62 @@
/*
* (C) Copyright 2000
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <nios.h>
/*
* include common flash code (for altera boards)
*/
#include "../common/flash.c"
/*----------------------------------------------------------------------*/
#define BANKSZ CFG_FLASH_SIZE
#define SECTSZ (64 * 1024)
#define USERFLASH (2 * 1024 * 1024) /* bottom 2 MB for user */
/*----------------------------------------------------------------------*/
unsigned long flash_init (void)
{
int i;
unsigned long addr;
flash_info_t *fli = &flash_info[0];
fli->size = BANKSZ;
fli->sector_count = CFG_MAX_FLASH_SECT;
fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
addr = CFG_FLASH_BASE;
for (i = 0; i < fli->sector_count; ++i) {
fli->start[i] = addr;
addr += SECTSZ;
/* Protect all but 2 MByte user area */
if (addr < (CFG_FLASH_BASE + USERFLASH))
fli->protect[i] = 0;
else
fli->protect[i] = 1;
}
return (BANKSZ);
}

33
board/altera/dk1c20/misc.c Normal file
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@ -0,0 +1,33 @@
/*
* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
* Stephan Linz <linz@li-pro.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* board/altera/dk1s10/misc.c
*
* miscellaneous board interfaces / drivers
*/
#include <common.h>
#if defined(CONFIG_SEVENSEG)
#include "../common/sevenseg.h"
#include "../common/sevenseg.c"
#endif

0
board/dk1c20/u-boot.lds → board/altera/dk1c20/u-boot.lds
View File

0
board/dk1c20/vectors.S → board/altera/dk1c20/vectors.S
View File

48
board/altera/dk1s10/Makefile Normal file
View File

@ -0,0 +1,48 @@
#
# (C) Copyright 2001-2004
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = lib$(BOARD).a
OBJS := $(BOARD).o flash.o misc.o
SOBJS = vectors.o
$(LIB): $(OBJS) $(SOBJS)
$(AR) crv $@ $^
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c)
$(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@
-include .depend
#########################################################################

29
board/altera/dk1s10/config.mk Normal file
View File

@ -0,0 +1,29 @@
#
# (C) Copyright 2003
# Psyent Corporation
# Scott McNutt <smcnutt@psyent.com>
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
TEXT_BASE = 0x018c0000
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif

50
board/altera/dk1s10/dk1s10.c Normal file
View File

@ -0,0 +1,50 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#if defined(CONFIG_SEVENSEG)
#include "../common/sevenseg.h"
#endif
void _default_hdlr (void)
{
printf ("default_hdlr\n");
}
int board_pre_init (void)
{
/* init seven segment led display and switch off */
sevenseg_set(SEVENSEG_OFF);
return 0;
}
int checkboard (void)
{
puts ("Board: Altera Nios 1S10 Development Kit\n");
return 0;
}
long int initdram (int board_type)
{
return (0);
}

62
board/altera/dk1s10/flash.c Normal file
View File

@ -0,0 +1,62 @@
/*
* (C) Copyright 2000-2004
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <nios.h>
/*
* include common flash code (for altera boards)
*/
#include "../common/flash.c"
/*---------------------------------------------------------------------*/
#define BANKSZ (8 * 1024 * 1024)
#define SECTSZ (64 * 1024)
#define USERFLASH (2 * 1024 * 1024) /* bottom 2 MB for user */
/*---------------------------------------------------------------------*/
unsigned long flash_init (void)
{
int i;
unsigned long addr;
flash_info_t *fli = &flash_info[0];
fli->size = BANKSZ;
fli->sector_count = CFG_MAX_FLASH_SECT;
fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
addr = CFG_FLASH_BASE;
for (i = 0; i < fli->sector_count; ++i) {
fli->start[i] = addr;
addr += SECTSZ;
/* Protect all but 2 MByte user area */
if (addr < (CFG_FLASH_BASE + USERFLASH))
fli->protect[i] = 0;
else
fli->protect[i] = 1;
}
return (BANKSZ);
}

33
board/altera/dk1s10/misc.c Normal file
View File

@ -0,0 +1,33 @@
/*
* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
* Stephan Linz <linz@li-pro.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* board/altera/dk1s10/misc.c
*
* miscellaneous board interfaces / drivers
*/
#include <common.h>
#if defined(CONFIG_SEVENSEG)
#include "../common/sevenseg.h"
#include "../common/sevenseg.c"
#endif

69
board/altera/dk1s10/u-boot.lds Normal file
View File

@ -0,0 +1,69 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_FORMAT("elf32-nios")
OUTPUT_ARCH(nios)
ENTRY(_start)
SECTIONS
{
.text :
{
cpu/nios/start.o (.text)
*(.text)
}
__text_end = .;
. = ALIGN(4);
.rodata :
{
*(.rodata)
}
__rodata_end = .;
. = ALIGN(4);
.data :
{
*(.data)
}
. = ALIGN(4);
__data_end = .;
__u_boot_cmd_start = .;
.u_boot_cmd :
{
*(.u_boot_cmd)
}
. = ALIGN(4);
__u_boot_cmd_end = .;
__bss_start = .;
. = ALIGN(4);
.bss :
{
*(.bss)
}
. = ALIGN(4);
__bss_end = .;
}

122
board/altera/dk1s10/vectors.S Normal file
View File

@ -0,0 +1,122 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
/*************************************************************************
* Exception Vector Table
*
* This could have gone in the cpu soure tree, but the whole point of
* Nios is customization -- and polluting the cpu source tree with
* board-specific ifdef's really defeats the purpose, no? With this in
* the board-specific tree, each board has the freedom to organize
* vectors/traps, etc anyway it wants. The init code copies this table
* to the proper location.
*
* Each board can do what it likes here. But there are four "standard"
* handlers availble:
*
* _cwp_lolimit -Handles register window underflows.
* _cwp_hilimit -Handles register window overflows.
* _timebase_int -Increments the timebase.
* _def_xhandler -Default exception handler.
*
* _timebase_int handles a Nios Timer interrupt and increments the
* timestamp used for the get_timer(), reset_timer(), etc. routines. It
* expects the timer to be configured like the standard-32 low priority
* timer.
*
* _def_xhandler dispatches exceptions/traps via the external_interrupt()
* routine. This lets you use the irq_install_handler() and handle your
* interrupts/traps with code written in C.
************************************************************************/
.data
.global _vectors
.align 4
_vectors:
.long _def_xhandler@h /* Vector 0 - NMI */
.long _cwp_lolimit@h /* Vector 1 - underflow */
.long _cwp_hilimit@h /* Vector 2 - overflow */
.long _def_xhandler@h /* Vector 3 - GNUPro debug */
.long _def_xhandler@h /* Vector 4 - GNUPro debug */
.long _def_xhandler@h /* Vector 5 - GNUPro debug */
.long _def_xhandler@h /* Vector 6 - future reserved */
.long _def_xhandler@h /* Vector 7 - future reserved */
.long _def_xhandler@h /* Vector 8 - future reserved */
.long _def_xhandler@h /* Vector 9 - future reserved */
.long _def_xhandler@h /* Vector 10 - future reserved */
.long _def_xhandler@h /* Vector 11 - future reserved */
.long _def_xhandler@h /* Vector 12 - future reserved */
.long _def_xhandler@h /* Vector 13 - future reserved */
.long _def_xhandler@h /* Vector 14 - future reserved */
.long _def_xhandler@h /* Vector 15 - future reserved */
.long _def_xhandler@h /* Vector 16 */
.long _def_xhandler@h /* Vector 17 */
.long _def_xhandler@h /* Vector 18 */
.long _def_xhandler@h /* Vector 19 */
.long _def_xhandler@h /* Vector 20 */
.long _def_xhandler@h /* Vector 21 */
.long _def_xhandler@h /* Vector 22 */
.long _def_xhandler@h /* Vector 23 */
.long _def_xhandler@h /* Vector 24 */
.long _def_xhandler@h /* Vector 25 */
.long _def_xhandler@h /* Vector 26 */
.long _def_xhandler@h /* Vector 27 */
.long _def_xhandler@h /* Vector 28 */
.long _def_xhandler@h /* Vector 29 */
.long _def_xhandler@h /* Vector 30 */
.long _def_xhandler@h /* Vector 31 */
.long _def_xhandler@h /* Vector 32 */
.long _def_xhandler@h /* Vector 33 */
.long _def_xhandler@h /* Vector 34 */
.long _def_xhandler@h /* Vector 35 */
.long _def_xhandler@h /* Vector 36 */
.long _def_xhandler@h /* Vector 37 */
.long _def_xhandler@h /* Vector 38 */
.long _def_xhandler@h /* Vector 39 */
.long _def_xhandler@h /* Vector 40 */
.long _def_xhandler@h /* Vector 41 */
.long _def_xhandler@h /* Vector 42 */
.long _def_xhandler@h /* Vector 43 */
.long _def_xhandler@h /* Vector 44 */
.long _def_xhandler@h /* Vector 45 */
.long _def_xhandler@h /* Vector 46 */
.long _def_xhandler@h /* Vector 47 */
.long _def_xhandler@h /* Vector 48 */
.long _def_xhandler@h /* Vector 49 */
.long _timebase_int@h /* Vector 50 - lopri timer*/
.long _def_xhandler@h /* Vector 51 */
.long _def_xhandler@h /* Vector 52 */
.long _def_xhandler@h /* Vector 53 */
.long _def_xhandler@h /* Vector 54 */
.long _def_xhandler@h /* Vector 55 */
.long _def_xhandler@h /* Vector 56 */
.long _def_xhandler@h /* Vector 57 */
.long _def_xhandler@h /* Vector 58 */
.long _def_xhandler@h /* Vector 59 */
.long _def_xhandler@h /* Vector 60 */
.long _def_xhandler@h /* Vector 61 */
.long _def_xhandler@h /* Vector 62 */
.long _def_xhandler@h /* Vector 63 */

3
board/mpl/pati/plx9056.h
View File

@ -61,7 +61,6 @@
#endif
#define PCI_DEVICE_ID_PLX9056 0x9056
/* Local Configuration Registers Accessible via the PCI Base address + Variable */
@ -109,6 +108,4 @@
#define PCI9056_PERM_VENDOR_ID (0x070 + LOCAL_OFFSET)
#define PCI9056_REVISION_ID (0x074 + LOCAL_OFFSET)
#endif /* #ifndef __PLX9056_H_ */

6
cpu/nios/interrupts.c
View File

@ -30,6 +30,9 @@
#include <asm/ptrace.h>
#include <common.h>
#include <command.h>
#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#endif
/****************************************************************************/
@ -72,6 +75,9 @@ void timer_interrupt (struct pt_regs *regs)
nios_timer_t *tmr = (nios_timer_t *)CFG_NIOS_TMRBASE;
tmr->status = 0;
timestamp += CFG_NIOS_TMRMS;
#ifdef CONFIG_STATUS_LED
status_led_tick(timestamp);
#endif
}
#endif

7
disk/part.c
View File

@ -35,7 +35,8 @@
#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \
(CONFIG_COMMANDS & CFG_CMD_SCSI) || \
(CONFIG_COMMANDS & CFG_CMD_USB) )
(CONFIG_COMMANDS & CFG_CMD_USB) || \
(CONFIG_MMC) )
/* ------------------------------------------------------------------------- */
/*
@ -102,7 +103,11 @@ void dev_print (block_dev_desc_t *dev_desc)
puts (" Capacity: not available\n");
}
}
#endif /* CFG_CMD_IDE || CFG_CMD_SCSI || CFG_CMD_USB || CONFIG_MMC */
#if ((CONFIG_COMMANDS & CFG_CMD_IDE) || \
(CONFIG_COMMANDS & CFG_CMD_SCSI) || \
(CONFIG_COMMANDS & CFG_CMD_USB) )
#if defined(CONFIG_MAC_PARTITION) || \
defined(CONFIG_DOS_PARTITION) || \

365
doc/README.dk1c20_std32 Normal file
View File

@ -0,0 +1,365 @@
TODO: specify IDE i/f
specify ASMI i/f
specify OCI
===============================================================================
C P U , M E M O R Y , I N / O U T C O M P O N E N T S
===============================================================================
see also [1]-[6]
CPU: "standard_32"
32 bit NIOS for 50 MHz
256 Byte for register file (15 levels)
4 KByte instruction cache (2 bytes in each cache line)
4 KByte data cache (4 bytes in each cache line)
2 KByte On Chip ROM with GERMS boot monitor
no On Chip RAM
MSTEP multiplier
no Debug Core
On Chip Instrumentation (OCI) enabled
U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
CFG_NIOS_CPU_ICACHE = 4096
CFG_NIOS_CPU_DCACHE = 4096
CFG_NIOS_CPU_REG_NUMS = 256
CFG_NIOS_CPU_MUL = 0
CFG_NIOS_CPU_MSTEP = 1
CFG_NIOS_CPU_DBG_CORE = 0
OCI: (TODO)
IRQ: Nr. | used by
------+--------------------------------------------------------
16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16
25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25
30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30
35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35
40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40
45 | ASMI | CFG_NIOS_CPU_ASMI0_IRQ = 45
50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50
MEMORY: 8 MByte Flash
1 MByte SRAM
16 MByte SDRAM
ASMI: (TODO) <-- ASMI part is 4M bits
Timer: TIMER0: high priority programmable timer (IRQ16)
TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1
CFG_NIOS_CPU_USER_TIMER = 0
PIO: Nr. | description
------+--------------------------------------------------------
PIO0 | BUTTON: 4 inputs for user push buttons (IRQ40)
PIO1 | LCD: 11 in/outputs for ASCII LCD
PIO2 | LED: 8 outputs for user LEDs
PIO3 | SEVENSEG: 16 outputs for user seven segment display
PIO4 | RECONF: 1 in/output for . . . . . . . . . . . .
PIO5 | CFPRESENT: 1 input for CF present event (IRQ35)
PIO6 | CFPOWER: 1 output to controll CF power supply
PIO7 | CFATASEL: 1 output to controll CF ATA card select
U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0
CFG_NIOS_CPU_LCD_PIO = 1
CFG_NIOS_CPU_LED_PIO = 2
CFG_NIOS_CPU_SEVENSEG_PIO = 3
CFG_NIOS_CPU_RECONF_PIO = 4
CFG_NIOS_CPU_CFPRESENT_PIO = 5
CFG_NIOS_CPU_CFPOWER_PIO = 6
CFG_NIOS_CPU_CFATASEL_PIO = 7
UART: UART0: fixed baudrate of 115200, fixed protocol 8N1,
without handshake RTS/CTS (IRQ25)
LAN: SMsC LAN91C111 with:
- offset 0x300 (LAN91C111_REGISTERS_OFFSET)
- data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
IDE: (TODO)
===============================================================================
M E M O R Y M A P
===============================================================================
- - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - -
0x02000000 ---32-----------16|15------------0-
| : | \
| : | |
SDRAM | : | > CFG_NIOS_CPU_SRAM_SIZE
| : | | = 0x01000000
| : | /
0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
| |
: gap :
: :
- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
: :
: gap :
| |
0x________ ---32-----------16|15------------0-
| | | \
: (real size : : |
ASMI i/f : and content : : > 0x________
[5] : unknown) : : |
| | | /
0x00920b00 ---32-----------16|15------------0- CFG_NIOS_CPU_ASMI0
| |
: gap :
| |
0x00920a80 ---32-----------16|15------------0-
| | | \
: (real size : : |
IDE i/f : and content : : > 0x00000080
[6] : unknown) : : |
| | | /
0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0
| (unused) | \
+ 0x1c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x18 |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x14 |- - - - - - - - - - - - - - - -| |
TIMER1 | (unused) | |
[3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
| (unused) | |
+ 0x0c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x08 |- - - - - - - - - - - - - - - -| |
| control (1 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| status (2 bit) (rw) | /
0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO7 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (1 bit) (wo) | /
0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO6 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (1 bit) (wo) | /
0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6
| edgecapture (1 bit) (rw) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO5 | interruptmask (1 bit) (rw) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (1 bit) (ro) | /
0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO4 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| direction (1 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (1 bit) (rw) | /
0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO3 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (16 bit) (wo) | /
0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO2 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (8 bit) (wo) | /
0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO1 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| direction (11 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (11 bit) (rw) | /
0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
| edgecapture (4 bit) (rw) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO0 | interruptmask (4 bit) (rw) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (4 bit) (ro) | /
0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
| (unused) | \
+ 0x1c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x18 |- - - - - - - - - - - - - - - -| |
| snaph (16 bit) (rw) | |
+ 0x14 |- - - - - - - - - - - - - - - -| |
TIMER0 | snapl (16 bit) (rw) | |
[3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
| periodh (16 bit) (rw) | |
+ 0x0c |- - - - - - - - - - - - - - - -| |
| periodl (16 bit) (rw) | |
+ 0x08 |- - - - - - - - - - - - - - - -| |
| control (4 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| status (2 bit) (rw) | /
0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
| | \
: gap : > (space for UART1)
| | /
0x00920920 ---32-----------16|15------------0-
| (unused) | \
+ 0x1c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x18 |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x14 |- - - - - - - - - - - - - - - -| |
UART0 | (unused) | > 0x00000020
[2] + 0x10 |- - - - - - - - - - - - - - - -| |
| control (10 bit) (rw) | |
+ 0x0c |- - - - - - - - - - - - - - - -| |
| status (10 bit) (rw) | |
+ 0x08 |- - - - - - - - - - - - - - - -| |
| txdata (8 bit) (wo) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| rxdata (8 bit) (ro) | /
0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
- - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - -
0x00920900 -----------------------------------
| | \
: (real size : |
OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE
: unknown) : | = 0x00000100
| | /
0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE
- - - - - - - - - - - on chip memory - - - - - - - - - - -
0x00920800 ---32-----------16|15------------0-
| : | \
| : | |
GERMS | : | > CFG_NIOS_CPU_ROM_SIZE
| : | | = 0x00000800
| : | /
0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE
- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
0x00920000 ---32-----------16|15------------0-
| gap | \
0x00910310 --+-------------------------------| |
| | |
| register bank (size = 0x10) | |
| +--------.---.---.--- | |
| | bank 0 \ 1 \ 2 \ 3 \ | |
| |---------------------------+ | |
LAN91C111 | | BANK | RESERVED | | |
| |- - - - - - -|- - - - - - -| | > na_lan91c111_size
| | RPCR | MIR | | | = 0x00010000
| |- - - - - - -|- - - - - - -| | |
| | COUNTER | RCR | | |
| |- - - - - - -|- - - - - - -| | |
| | EPH STATUS | TCR | | |
| +---------------------------+ | |
0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
| gap | /
0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE
| |
: gap :
: :
- - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - -
: :
: gap :
| |
0x00900000 ---32-----------16|15------------0-
0x00900000 --+32-----------16|15------------0+
| : | \ \
| : | | |
| : | | > CFG_NIOS_CPU_VEC_SIZE
| : | | | = 0x00000100
| : | | /
0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE
0x008fff00 |- - - - - - - -:- - - - - - - -+-|- CFG_NIOS_CPU_STACK
| : | | \
| : | | |
| : | | > stack area
| : | | |
| : | | V
| : | |
SRAM | : | > CFG_NIOS_CPU_SRAM_SIZE
| : | | = 0x00100000
| : | /
0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
0x00800000 ---8-------------4|3-------------0-
| sector 127 | \
+ 0x7f0000 |- - - - - - - - - - - - - - - -| |
| : | |
Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE
| sector 1 : | | = 0x00800000
+ 0x010000 |- - - - - - - - - - - - - - - -| |
| sector 0 (size = 0x10000) | /
0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE
===============================================================================
F L A S H M E M O R Y A L L O C A T I O N
===============================================================================
0x00800000 ---8-------------4|3-------------0-
| : | \
SAFE | : | > 1 MByte
FPGA conf. | : | / (NOT usable by software)
0x00700000 --+- - - - - - - -:- - - - - - - -+-
| : | \
USER | : | > 1 MByte
FPGA conf. | : | / (NOT usable by software)
0x00600000 --+- - - - - - - -:- - - - - - - -+-
| : | \
| : | |
WEB pages | : | > 2 MByte
| : | | (provisory usable)
| : | /
0x00400000 --+- - - - - - - -:- - - - - - - -+-
| : | \
| : | |
| : | |
| : | > 4 MByte free for use
| : | |
0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
| : | /
0x00000000 ---8-------------4|3-------------0-
===============================================================================
R E F E R E N C E S
===============================================================================
[1] http://www.altera.com/literature/manual/mnl_nios_board_cyclone_1c20.pdf
[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
[5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf
http://www.altera.com/literature/wp/wp_epcs_cyc.pdf
[6] http://www.opencores.org/projects/ata/
http://www.t13.org/index.html
===============================================================================
Stephan Linz <linz@li-pro.net>

353
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TODO: specify IDE i/f
specify OCI
===============================================================================
C P U , M E M O R Y , I N / O U T C O M P O N E N T S
===============================================================================
see also [1]-[5]
CPU: "standard_32"
32 bit NIOS for 50 MHz
256 Byte for register file (15 levels)
4 KByte instruction cache (4 bytes in each cache line)
4 KByte data cache (4 bytes in each cache line)
2 KByte On Chip ROM with GERMS boot monitor
64 KByte On Chip RAM
MSTEP multiplier
no Debug Core
On Chip Instrumentation (OCI) enabled
U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
CFG_NIOS_CPU_ICACHE = 4096
CFG_NIOS_CPU_DCACHE = 4096
CFG_NIOS_CPU_REG_NUMS = 256
CFG_NIOS_CPU_MUL = 0
CFG_NIOS_CPU_MSTEP = 1
CFG_NIOS_CPU_DBG_CORE = 0
OCI: (TODO)
IRQ: Nr. | used by
------+--------------------------------------------------------
16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16
25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25
30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30
35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35
40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40
50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50
MEMORY: 8 MByte Flash
1 MByte SRAM
16 MByte SDRAM
Timer: TIMER0: high priority programmable timer (IRQ16)
TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1
CFG_NIOS_CPU_USER_TIMER = 0
PIO: Nr. | description
------+--------------------------------------------------------
PIO0 | BUTTON: 4 inputs for user push buttons (IRQ40)
PIO1 | LCD: 11 in/outputs for ASCII LCD
PIO2 | LED: 8 outputs for user LEDs
PIO3 | SEVENSEG: 16 outputs for user seven segment display
PIO4 | RECONF: 1 in/output for . . . . . . . . . . . .
PIO5 | CFPRESENT: 1 input for CF present event (IRQ35)
PIO6 | CFPOWER: 1 output to controll CF power supply
PIO7 | CFATASEL: 1 output to controll CF ATA card select
U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0
CFG_NIOS_CPU_LCD_PIO = 1
CFG_NIOS_CPU_LED_PIO = 2
CFG_NIOS_CPU_SEVENSEG_PIO = 3
CFG_NIOS_CPU_RECONF_PIO = 4
CFG_NIOS_CPU_CFPRESENT_PIO = 5
CFG_NIOS_CPU_CFPOWER_PIO = 6
CFG_NIOS_CPU_CFATASEL_PIO = 7
UART: UART0: fixed baudrate of 115200, fixed protocol 8N1,
without handshake RTS/CTS (IRQ25)
LAN: SMsC LAN91C111 with:
- offset 0x300 (LAN91C111_REGISTERS_OFFSET)
- data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
IDE: (TODO)
===============================================================================
M E M O R Y M A P
===============================================================================
- - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - -
0x02000000 ---32-----------16|15------------0-
| : | \
| : | |
SDRAM | : | > CFG_NIOS_CPU_SRAM_SIZE
| : | | = 0x01000000
| : | /
0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
| |
: gap :
: :
- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
: :
: gap :
| |
0x00920a80 ---32-----------16|15------------0-
| | | \
: (real size : : |
IDE i/f : and content : : > 0x00000080
[5] : unknown) : : |
| | | /
0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0
| (unused) | \
+ 0x1c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x18 |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x14 |- - - - - - - - - - - - - - - -| |
TIMER1 | (unused) | |
[3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
| (unused) | |
+ 0x0c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x08 |- - - - - - - - - - - - - - - -| |
| control (1 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| status (2 bit) (rw) | /
0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO7 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (1 bit) (wo) | /
0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO6 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (1 bit) (wo) | /
0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6
| edgecapture (1 bit) (rw) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO5 | interruptmask (1 bit) (rw) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (1 bit) (ro) | /
0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO4 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| direction (1 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (1 bit) (rw) | /
0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO3 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (16 bit) (wo) | /
0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO2 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (8 bit) (wo) | /
0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO1 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| direction (11 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (11 bit) (rw) | /
0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
| edgecapture (4 bit) (rw) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO0 | interruptmask (4 bit) (rw) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (4 bit) (ro) | /
0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
| (unused) | \
+ 0x1c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x18 |- - - - - - - - - - - - - - - -| |
| snaph (16 bit) (rw) | |
+ 0x14 |- - - - - - - - - - - - - - - -| |
TIMER0 | snapl (16 bit) (rw) | |
[3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
| periodh (16 bit) (rw) | |
+ 0x0c |- - - - - - - - - - - - - - - -| |
| periodl (16 bit) (rw) | |
+ 0x08 |- - - - - - - - - - - - - - - -| |
| control (4 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| status (2 bit) (rw) | /
0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
| | \
: gap : > (space for UART1)
| | /
0x00920920 ---32-----------16|15------------0-
| (unused) | \
+ 0x1c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x18 |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x14 |- - - - - - - - - - - - - - - -| |
UART0 | (unused) | > 0x00000020
[2] + 0x10 |- - - - - - - - - - - - - - - -| |
| control (10 bit) (rw) | |
+ 0x0c |- - - - - - - - - - - - - - - -| |
| status (10 bit) (rw) | |
+ 0x08 |- - - - - - - - - - - - - - - -| |
| txdata (8 bit) (wo) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| rxdata (8 bit) (ro) | /
0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
- - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - -
0x00920900 -----------------------------------
| | \
: (real size : |
OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE
: unknown) : | = 0x00000100
| | /
0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE
- - - - - - - - - - - on chip memory 2 - - - - - - - - - - -
0x00920800 ---32-----------16|15------------0-
| : | \
| : | |
GERMS | : | > CFG_NIOS_CPU_ROM_SIZE
| : | | = 0x00000800
| : | /
0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE
- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
0x00920000 ---32-----------16|15------------0-
| gap | \
0x00910310 --+-------------------------------| |
| | |
| register bank (size = 0x10) | |
| +--------.---.---.--- | |
| | bank 0 \ 1 \ 2 \ 3 \ | |
| |---------------------------+ | |
LAN91C111 | | BANK | RESERVED | | |
| |- - - - - - -|- - - - - - -| | > na_lan91c111_size
| | RPCR | MIR | | | = 0x00010000
| |- - - - - - -|- - - - - - -| | |
| | COUNTER | RCR | | |
| |- - - - - - -|- - - - - - -| | |
| | EPH STATUS | TCR | | |
| +---------------------------+ | |
0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
| gap | /
0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE
- - - - - - - - - - - on chip memory 1 - - - - - - - - - - -
0x00910000 ---32-----------16|15------------0-
| : | \
| : | |
onchip RAM | : | > CFG_NIOS_CPU_RAM_SIZE
| : | | = 0x00010000
| : | /
0x00900000 ---32-----------16|15------------0- CFG_NIOS_CPU_RAM_BASE
- - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - -
0x00900000 ---32-----------16|15------------0-
0x00900000 --+32-----------16|15------------0+
| . | \ \
| . | | |
| . | | > CFG_NIOS_CPU_VEC_SIZE
| . | | | = 0x00000100
| . | | /
0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE
0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK
| . | | \
| . | | |
| . | | > stack area
| . | | |
| . | | V
| . | |
SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE
| . | | = 0x00100000
| | /
0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
0x00800000 ---8-------------4|3-------------0-
| sector 127 | \
+ 0x7f0000 |- - - - - - - - - - - - - - - -| |
| : | |
Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE
| sector 1 : | | = 0x00800000
+ 0x010000 |- - - - - - - - - - - - - - - -| |
| sector 0 (size = 0x10000) | /
0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE
===============================================================================
F L A S H M E M O R Y A L L O C A T I O N
===============================================================================
0x00800000 ---8-------------4|3-------------0-
| : | \
SAFE | : | > 1 MByte
FPGA conf. | : | / (NOT usable by software)
0x00700000 --+- - - - - - - -:- - - - - - - -+-
| : | \
USER | : | > 1 MByte
FPGA conf. | : | / (NOT usable by software)
0x00600000 --+- - - - - - - -:- - - - - - - -+-
| : | \
| : | |
WEB pages | : | > 2 MByte
| : | | (provisory usable)
| : | /
0x00400000 --+- - - - - - - -:- - - - - - - -+-
| : | \
| : | |
| : | |
| : | > 4 MByte free for use
| : | |
0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
| : | /
0x00000000 ---8-------------4|3-------------0-
===============================================================================
R E F E R E N C E S
===============================================================================
[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s10.pdf
[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
[5] http://www.opencores.org/projects/ata/
http://www.t13.org/index.html
===============================================================================
Stephan Linz <linz@li-pro.net>

355
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View File

@ -0,0 +1,355 @@
TODO: specify IDE i/f
specify OCI
===============================================================================
C P U , M E M O R Y , I N / O U T C O M P O N E N T S
===============================================================================
see also [1]-[5]
CPU: "standard_32"
32 bit NIOS for 50 MHz
256 Byte for register file (15 levels)
4 KByte instruction cache (4 bytes in each cache line)
4 KByte data cache (4 bytes in each cache line)
2 KByte On Chip ROM with GERMS boot monitor
64 KByte On Chip RAM
MSTEP multiplier
no Debug Core
On Chip Instrumentation (OCI) enabled
U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
CFG_NIOS_CPU_ICACHE = 4096
CFG_NIOS_CPU_DCACHE = 4096
CFG_NIOS_CPU_REG_NUMS = 256
CFG_NIOS_CPU_MUL = 0
CFG_NIOS_CPU_MSTEP = 1
CFG_NIOS_CPU_DBG_CORE = 0
OCI: (TODO)
IRQ: Nr. | used by
------+--------------------------------------------------------
16 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 16
25 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 25
30 | LAN91C111 | CFG_NIOS_CPU_LAN0_IRQ = 30
35 | PIO5 | CFG_NIOS_CPU_PIO5_IRQ = 35
40 | PIO0 | CFG_NIOS_CPU_PIO0_IRQ = 40
50 | TIMER1 | CFG_NIOS_CPU_TIMER1_IRQ = 50
MEMORY: 8 MByte Flash
1 MByte SRAM
16 MByte SDRAM
Timer: TIMER0: high priority programmable timer (IRQ16)
TIMER1: low priority fixed timer for 10 ms @ 50 MHz (IRQ50)
U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 1
CFG_NIOS_CPU_USER_TIMER = 0
PIO: Nr. | description
------+--------------------------------------------------------
PIO0 | BUTTON: 4 inputs for user push buttons (IRQ40)
PIO1 | LCD: 11 in/outputs for ASCII LCD
PIO2 | LED: 8 outputs for user LEDs
PIO3 | SEVENSEG: 16 outputs for user seven segment display
PIO4 | RECONF: 1 in/output for . . . . . . . . . . . .
PIO5 | CFPRESENT: 1 input for CF present event (IRQ35)
PIO6 | CFPOWER: 1 output to controll CF power supply
PIO7 | CFATASEL: 1 output to controll CF ATA card select
U-Boot CFG: CFG_NIOS_CPU_BUTTON_PIO = 0
CFG_NIOS_CPU_LCD_PIO = 1
CFG_NIOS_CPU_LED_PIO = 2
CFG_NIOS_CPU_SEVENSEG_PIO = 3
CFG_NIOS_CPU_RECONF_PIO = 4
CFG_NIOS_CPU_CFPRESENT_PIO = 5
CFG_NIOS_CPU_CFPOWER_PIO = 6
CFG_NIOS_CPU_CFATASEL_PIO = 7
UART: UART0: fixed baudrate of 115200, fixed protocol 8N1,
without handshake RTS/CTS (IRQ25)
LAN: SMsC LAN91C111 with:
- offset 0x300 (LAN91C111_REGISTERS_OFFSET)
- data bus width 32 bit (LAN91C111_DATA_BUS_WIDTH)
IDE: (TODO)
===============================================================================
M E M O R Y M A P
===============================================================================
- - - - - - - - - - - external memory 2 - - - - - - - - - - - - - - - - - - -
0x02000000 ---32-----------16|15------------0-
| : | \
| : | |
SDRAM | : | > CFG_NIOS_CPU_SRAM_SIZE
| : | | = 0x01000000
| : | /
0x01000000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
| |
: gap :
: :
- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
: :
: gap :
| |
0x00920a80 ---32-----------16|15------------0-
| | | \
: (real size : : |
IDE i/f : and content : : > 0x00000080
[5] : unknown) : : |
| | | /
0x00920a00 ---32-----------16|15------------0- CFG_NIOS_CPU_IDE0
| (unused) | \
+ 0x1c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x18 |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x14 |- - - - - - - - - - - - - - - -| |
TIMER1 | (unused) | |
[3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
| (unused) | |
+ 0x0c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x08 |- - - - - - - - - - - - - - - -| |
| control (1 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| status (2 bit) (rw) | /
0x009209e0 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER1
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO7 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (1 bit) (wo) | /
0x009209d0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO7
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO6 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (1 bit) (wo) | /
0x009209c0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO6
| edgecapture (1 bit) (rw) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO5 | interruptmask (1 bit) (rw) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (1 bit) (ro) | /
0x009209b0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO5
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO4 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| direction (1 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (1 bit) (rw) | /
0x009209a0 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO4
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO3 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (16 bit) (wo) | /
0x00920990 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO2 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (8 bit) (wo) | /
0x00920980 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO1 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| direction (11 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (11 bit) (rw) | /
0x00920970 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
| edgecapture (4 bit) (rw) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO0 | interruptmask (4 bit) (rw) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (4 bit) (ro) | /
0x00920960 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
| (unused) | \
+ 0x1c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x18 |- - - - - - - - - - - - - - - -| |
| snaph (16 bit) (rw) | |
+ 0x14 |- - - - - - - - - - - - - - - -| |
TIMER0 | snapl (16 bit) (rw) | |
[3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
| periodh (16 bit) (rw) | |
+ 0x0c |- - - - - - - - - - - - - - - -| |
| periodl (16 bit) (rw) | |
+ 0x08 |- - - - - - - - - - - - - - - -| |
| control (4 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| status (2 bit) (rw) | /
0x00920940 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
| | \
: gap : > (space for UART1)
| | /
0x00920920 ---32-----------16|15------------0-
| (unused) | \
+ 0x1c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x18 |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x14 |- - - - - - - - - - - - - - - -| |
UART0 | (unused) | > 0x00000020
[2] + 0x10 |- - - - - - - - - - - - - - - -| |
| control (10 bit) (rw) | |
+ 0x0c |- - - - - - - - - - - - - - - -| |
| status (10 bit) (rw) | |
+ 0x08 |- - - - - - - - - - - - - - - -| |
| txdata (8 bit) (wo) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| rxdata (8 bit) (ro) | /
0x00920900 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
- - - - - - - - - - - on chip debugging - - - - - - - - - - - - - - - - - - -
0x00920900 -----------------------------------
| | \
: (real size : |
OCI Debug : and content : > CFG_NIOS_CPU_OCI_SIZE
: unknown) : | = 0x00000100
| | /
0x00920800 ----------------------------------- CFG_NIOS_CPU_OCI_BASE
- - - - - - - - - - - on chip memory 2 - - - - - - - - - - -
0x00920800 ---32-----------16|15------------0-
| : | \
| : | |
GERMS | : | > CFG_NIOS_CPU_ROM_SIZE
| : | | = 0x00000800
| : | /
0x00920000 |- - - - - - - - - - - - - - - -+- - CFG_NIOS_CPU_RST_VECT
0x00920000 ---32-----------16|15------------0- CFG_NIOS_CPU_ROM_BASE
- - - - - - - - - - - external i/o - - - - - - - - - - - - - - - - - - -
0x00920000 ---32-----------16|15------------0-
| gap | \
0x00910310 --+-------------------------------| |
| | |
| register bank (size = 0x10) | |
| +--------.---.---.--- | |
| | bank 0 \ 1 \ 2 \ 3 \ | |
| |---------------------------+ | |
LAN91C111 | | BANK | RESERVED | | |
| |- - - - - - -|- - - - - - -| | > na_lan91c111_size
| | RPCR | MIR | | | = 0x00010000
| |- - - - - - -|- - - - - - -| | |
| | COUNTER | RCR | | |
| |- - - - - - -|- - - - - - -| | |
| | EPH STATUS | TCR | | |
| +---------------------------+ | |
0x00910300 --+--LAN91C111_REGISTERS_OFFSET---| |
| gap | /
0x00910000 ---32-----------16|15------------0- CFG_NIOS_CPU_LAN0_BASE
- - - - - - - - - - - on chip memory 1 - - - - - - - - - - -
0x00910000 ---32-----------16|15------------0-
| : | \
| : | |
onchip RAM | : | > CFG_NIOS_CPU_RAM_SIZE
| : | | = 0x00010000
| : | /
0x00900000 ---32-----------16|15------------0- CFG_NIOS_CPU_RAM_BASE
- - - - - - - - - - - external memory 1 - - - - - - - - - - - - - - - - - - -
0x00900000 ---32-----------16|15------------0-
0x00900000 --+32-----------16|15------------0+
| . | \ \
| . | | |
| . | | > CFG_NIOS_CPU_VEC_SIZE
| . | | | = 0x00000100
| . | | /
0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE
0x008fff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK
| . | | \
| . | | |
| . | | > stack area
| . | | |
| . | | V
| . | |
SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE
| . | | = 0x00100000
| | /
0x00800000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
0x00800000 ---8-------------4|3-------------0-
| sector 127 | \
+ 0x7f0000 |- - - - - - - - - - - - - - - -| |
| : | |
Flash |- - - - : - - - -| > CFG_NIOS_CPU_FLASH_SIZE
| sector 1 : | | = 0x00800000
+ 0x010000 |- - - - - - - - - - - - - - - -| |
| sector 0 (size = 0x10000) | /
0x00000000 ---8-------------4|3-------------0- CFG_NIOS_CPU_FLASH_BASE
===============================================================================
F L A S H M E M O R Y A L L O C A T I O N
===============================================================================
0x00800000 ---8-------------4|3-------------0-
| : | \
| : | |
SAFE | : | > 2 MByte
FPGA conf. | : | | (NOT usable by software)
| : | /
0x00600000 --+- - - - - - - -:- - - - - - - -+-
| : | \
| : | |
USER | : | > 2 MByte
FPGA conf. | : | | (NOT usable by software)
| : | /
0x00400000 --+- - - - - - - -:- - - - - - - -+-
| : | \
| : | |
WEB pages | : | > 2 MByte
| : | | (provisory usable)
| : | /
0x00200000 --+- - - - - - - -:- - - - - - - -+-
| : | \
| : | |
| : | > 2 MByte free for use
0x00040000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
| : | /
0x00000000 ---8-------------4|3-------------0-
===============================================================================
R E F E R E N C E S
===============================================================================
[1] http://www.altera.com/literature/manual/mnl_nios_board_stratix_1s40.pdf
[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
[5] http://www.opencores.org/projects/ata/
http://www.t13.org/index.html
===============================================================================
Stephan Linz <linz@li-pro.net>

242
doc/README.dk20k200_std32 Normal file
View File

@ -0,0 +1,242 @@
===============================================================================
C P U , M E M O R Y , I N / O U T C O M P O N E N T S
===============================================================================
see also [1]-[4]
CPU: "standard_32"
32 bit NIOS for 33.333 MHz (nasys_clock_freq = 33333000)
256 Byte for register file (15 levels)
no instruction cache
no data cache
1 KByte On Chip ROM with GERMS boot monitor
no On Chip RAM
MSTEP multiplier
no Debug Core
no On Chip Instrumentation (OCI) enabled
U-Boot CFG: CFG_NIOS_CPU_CLK = 50000000
CFG_NIOS_CPU_ICACHE = 0
CFG_NIOS_CPU_DCACHE = 0
CFG_NIOS_CPU_REG_NUMS = 256
CFG_NIOS_CPU_MUL = 0
CFG_NIOS_CPU_MSTEP = 1
CFG_NIOS_CPU_DBG_CORE = 0
IRQ: Nr. | used by
------+--------------------------------------------------------
25 | TIMER0 | CFG_NIOS_CPU_TIMER0_IRQ = 25
26 | UART0 | CFG_NIOS_CPU_UART0_IRQ = 26
27 | PIO2 | CFG_NIOS_CPU_PIO2_IRQ = 27
28 | UART1 | CFG_NIOS_CPU_UART1_IRQ = 28 (debug)
MEMORY: 1 MByte Flash
256 KByte SRAM
(SDRAM with standard SODIMM only)
Timer: TIMER0: high priority programmable timer (IRQ25)
U-Boot CFG: CFG_NIOS_CPU_TICK_TIMER = 0
PIO: Nr. | description
------+--------------------------------------------------------
PIO0 | SEVENSEG: 16 outputs for user seven segment display
PIO1 | LED: 8 outputs for user LEDs
PIO2 | BUTTON: 4 inputs for user push buttons (IRQ27)
PIO3 | LCD: 11 in/outputs for ASCII LCD
U-Boot CFG: CFG_NIOS_CPU_SEVENSEG_PIO = 0
CFG_NIOS_CPU_LED_PIO = 1
CFG_NIOS_CPU_BUTTON_PIO = 2
CFG_NIOS_CPU_LCD_PIO = 3
UART: UART0: fixed baudrate of 115200, fixed protocol 8N2,
without handshake RTS/CTS (IRQ26)
UART1: fixed baudrate of 115200, fixed protocol 8N1,
without handshake RTS/CTS (IRQ28)
===============================================================================
M E M O R Y M A P
===============================================================================
- - - - - - - - - - - external memory - - - - - - - - - - - - - - - - - - -
0x00200000 ---15------------8|7-------------0-
| sector 18 | \
+ 0x0f0000 |- - - - - - - - - - - - - - - -| |
| : | |
Flash |- - - - : - - - -| |
| sector 5 : | |
+ 0x020000 |- - - - - - - - -| |
| sector 4 (size = 0x10000) | |
+ 0x010000 |- - - - - - - - - - - - - - - -| > CFG_NIOS_CPU_FLASH_SIZE
| sector 3 (size = 0x08000) | | = 0x00100000
+ 0x008000 |- - - - - - - - - - - - - - - -| |
| sector 2 (size = 0x02000) | |
+ 0x006000 |- - - - - - - - - - - - - - - -| |
| sector 1 (size = 0x02000) | |
+ 0x004000 |- - - - - - - - - - - - - - - -| |
| sector 0 (size = 0x04000) | /
0x00100000 ---15------------8|7-------------0- CFG_NIOS_CPU_FLASH_BASE
| |
: gap :
| |
0x00080000 ---32-----------16|15------------0-
0x00080000 --+32-----------16|15------------0+
| . | \ \
| . | | |
| . | | > CFG_NIOS_CPU_VEC_SIZE
| . | | | = 0x00000100
| . | | /
0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_VEC_BASE
0x0007ff00 |- - - - - - - - - - - - - - - -+-|- CFG_NIOS_CPU_STACK
| . | | \
| . | | |
| . | | > stack area
| . | | |
| . | | V
| . | |
SRAM | . | > CFG_NIOS_CPU_SRAM_SIZE
| . | | = 0x00040000
| | /
0x00040000 ---32-----------16|15------------0- CFG_NIOS_CPU_SRAM_BASE
| |
: gap :
: :
- - - - - - - - - - - on chip i/o - - - - - - - - - - - - - - - - - - -
: :
: gap :
| |
0x00000400 ---32-----------16|15------------0-
| (unused) | \
+ 0x1c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x18 |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x14 |- - - - - - - - - - - - - - - -| |
UART0 | (unused) | > 0x00000020
[2] + 0x10 |- - - - - - - - - - - - - - - -| |
| control (10 bit) (rw) | |
+ 0x0c |- - - - - - - - - - - - - - - -| |
| status (10 bit) (rw) | |
+ 0x08 |- - - - - - - - - - - - - - - -| |
| txdata (8 bit) (wo) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| rxdata (8 bit) (ro) | /
0x000004c0 ---32-----------16|15------------0- CFG_NIOS_CPU_UART1
| |
: gap :
| |
0x00000490 ---32-----------16|15------------0-
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO3 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| direction (11 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (11 bit) (rw) | /
0x00000480 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO3
| edgecapture (12 bit) (rw) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO2 | interruptmask (12 bit) (rw) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (12 bit) (ro) | /
0x00000470 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO2
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO1 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| direction (2 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (2 bit) (rw) | /
0x00000460 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO1
| (unused) | \
+ 0x1c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x18 |- - - - - - - - - - - - - - - -| |
| snaph (16 bit) (rw) | |
+ 0x14 |- - - - - - - - - - - - - - - -| |
TIMER0 | snapl (16 bit) (rw) | |
[3] + 0x10 |- - - - - - - - - - - - - - - -| > 0x00000020
| periodh (16 bit) (rw) | |
+ 0x0c |- - - - - - - - - - - - - - - -| |
| periodl (16 bit) (rw) | |
+ 0x08 |- - - - - - - - - - - - - - - -| |
| control (4 bit) (rw) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| status (2 bit) (rw) | /
0x00000440 ---32-----------16|15------------0- CFG_NIOS_CPU_TIMER0
| (unused) | \
+ 0x0c |- - - - - - - - - - - - - - - -| |
PIO0 | (unused) | |
[4] + 0x08 |- - - - - - - - - - - - - - - -| > 0x00000010
| (unused) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| data (16 bit) (wo) | /
0x00000420 ---32-----------16|15------------0- CFG_NIOS_CPU_PIO0
| (unused) | \
+ 0x1c |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x18 |- - - - - - - - - - - - - - - -| |
| (unused) | |
+ 0x14 |- - - - - - - - - - - - - - - -| |
UART0 | (unused) | > 0x00000020
[2] + 0x10 |- - - - - - - - - - - - - - - -| |
| control (10 bit) (rw) | |
+ 0x0c |- - - - - - - - - - - - - - - -| |
| status (10 bit) (rw) | |
+ 0x08 |- - - - - - - - - - - - - - - -| |
| txdata (8 bit) (wo) | |
+ 0x04 |- - - - - - - - - - - - - - - -| |
| rxdata (8 bit) (ro) | /
0x00000400 ---32-----------16|15------------0- CFG_NIOS_CPU_UART0
- - - - - - - - - - - on chip memory - - - - - - - - - - -
0x00000400 ---32-----------16|15------------0-
| : | \
| : | |
GERMS | : | > na_boot_monitor_rom_size
| : | | = 0x00000400
| : | /
0x00000000 |- - - - - - - - - - - - - - - -+- - nasys_reset_address
0x00000000 ---32-----------16|15------------0- na_boot_monitor_rom
===============================================================================
F L A S H M E M O R Y A L L O C A T I O N
===============================================================================
0x00200000 ---15------------8|7-------------0-
| : | \
SAFE | : | > 256 KByte
FPGA conf. | : | / (NOT usable by software)
0x001c0000 --+- - - - - - - -:- - - - - - - -+-
| : | \
USER | : | > 256 KByte
FPGA conf. | : | / (NOT usable by software)
0x00180000 --+- - - - - - - -:- - - - - - - -+-
| : | \
| : | |
| : | > 512 KByte free for use
0x00140000 --+- - - - - - - -:- - - - - - - -+-|- u-boot _start()
| : | /
0x00100000 ---15------------8|7-------------0-
===============================================================================
R E F E R E N C E S
===============================================================================
[1] http://www.altera.com/literature/ds/ds_nios_board_apex_20k200e.pdf
[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
===============================================================================
Stephan Linz <linz@li-pro.net>

98
doc/README.nios
View File

@ -1,12 +1,27 @@
U-Boot for Nios-32
Last Update: October 15, 2003
Last Update: November 30, 2003
====================================================================
This file contains information regarding U-Boot and the Altera
Nios CPU. For information regarding U-Boot and the Nios Development
Kit, Cyclone Edition (DK-1C20), see doc/README.dk1c20.
Kits see:
* Cyclone Edition (DK-1C20), see doc/README.dk1c20
* Stratix Edition (DK-1S10), see doc/README.dk1s10 (TODO)
* Stratix Edition (DK-1S40), see doc/README.dk1s40 (TODO)
* Stratix Edition (DK-20K200), see doc/README.dk20k200 (TODO)
For informations regarding Nios Development Kit hardware overview
and the NIOS CPU standard configuration of all known boards made by
Altera see:
* Development Kit (DK) hardware overview, see doc/README.nios_DK
* NIOS CPU standard_32 at DK-1C20, see doc/README.dk1c20_std32
* NIOS CPU standard_32 at DK-1S10, see doc/README.dk1s10_std32
* NIOS CPU standard_32 at DK-1S40, see doc/README.dk1s40_std32
* NIOS CPU standard_32 at DK-20K200, see doc/README.dk20k200_std32
For those interested in contributing ... see HELP WANTED below.
@ -50,16 +65,25 @@ structure definitions from the Nios SDK.
2.1 Nios-specific Options/Settings
-----------------------------------
All configuration options/settings that are specific to Nios begin
with "CONFIG_NIOS_" or "CFG_NIOS_". The following is a list of
currently defined Nios-specific options/parameters. If any options
are related to Standard-32 Nios SDK excalibur.h definitions, the
related definition follows the description).
with "CONFIG_NIOS_", "CFG_NIOS_", or "CFG_NIOS_CPU_".
The configuration follows a two-stage process. In the first stage
the NIOS CPU core will defined like defined in Alteras SOPC Builder.
At this point we use the "CFG_NIOS_CPU_" defines exclusively. For
more informations about all the definitions you have to setup see
into current board configurations and doc/README.nios_CFG_NIOS_CPU.
In second stage we bring the NIOS CPU configuration in relation to
U-Boot configuration options/settings. The following is a list of
currently defined Nios-specific options/parameters used inside of
U-Boot. If any options are related to Standard-32 Nios SDK
excalibur.h definitions, the related definition follows the
description).
CONFIG_NIOS -- defined for all Nios-32 boards.
CFG_NIOS_CONSOLE -- the base address of the console UART.
(standard-32: na_uart1_base).
(standard-32: nasys_uart_0 resp. na_uart1_base).
CFG_NIOS_FIXEDBAUD -- defined if the console UART PTF fixed_baud
parameter is set to '1'.
@ -71,10 +95,11 @@ CFG_NIOS_MULT_MSTEP -- use hardware assisted multiply using the
CFG_NIOS_TMRBASE -- the base address of the timer used to support
xxx_timer routines (e.g. set_timer(), get_timer(), etc.).
(standard-32: na_lo_priority_timer2_base).
(standard-32: nasys_timer_1 resp. na_lo_priority_timer2_base).
CFG_NIOS_TMRIRQ -- the interrupt request (vector number) assigned to
the timer. (standard-32: na_low_priority_timer2_irq).
the timer. (standard-32: nasys_timer_1_irq resp.
na_low_priority_timer2_irq).
CFG_NIOS_TMRMS -- the period of the timer in milliseconds.
@ -105,20 +130,56 @@ is an alias for 'subi %rB,1' that is supported by the assembler
but does not appear in the programmer's manual.
4. BRAIN DAMAGE
4. BOOT PROCESS
---------------
4.1 Boot process over GERMS
---------------------------
When the NIOS CPU catch a reset signal it will begin to be running
code from CFG_NIOS_CPU_RST_VECT. Normally at this place it will
find the GERMS monitor. That's the case for the generic NIOS CPU
configuration "standard_32". When the GERMS monitor starts running,
it performs important system initializations and then looks for
executable code in flash, using the following steps:
1. Examining the two bytes at CFG_NIOS_CPU_FLASH_BASE + 0x04000C.
2. Examining the button 0 on the PIO CFG_NIOS_CPU_BUTTON_PIO.
3. If the button is not pressed and the two bytes contain 'N'
and 'i', the monitor executes a CALL to location
CFG_NIOS_CPU_FLASH_BASE + 0x040000.
4. If the code is not executed in step 3 or the code returns,
then prints an 8-digit version number to STDOUT and waits for
user commands from STDIN.
In normal case, for "standard_32", STDIN and STDOUT are the first
serial port.
4.2 Return to GERMS command line
--------------------------------
During the boot process, the GERMS monitor checks for the existence
of application software in flash memory. If found, the processor
immediately executes the code. To return program execution to the
GERMS monitor (that is, avoid running code stored in flash memory):
1. Hold down CFG_NIOS_CPU_BUTTON_PIO, button number 0.
2. Press then release the CPU reset button.
3. Release CFG_NIOS_CPU_BUTTON_PIO, button number 0.
5. BRAIN DAMAGE
----------------
This section describes some of the unfortunate and avoidable aspects
of working with the Nios CPU ... and some things you can do to
reduce your pain.
4.1 GERMS doesn't work with Hyperterminal
5.1 GERMS doesn't work with Hyperterminal
------------------------------------------
GERMS doesn't do CR/LF mapping that is compatible with Hyperterminal
(or minicom) -- geez. Regardless of you opion of Hyperterminal, this
sad design decision is remedied by using U-Boot.
4.2 cygwin Incompatibility
5.2 cygwin Incompatibility
---------------------------
The version of cygwin distributed with the nios GNUPro toolchain is
out-of-date and incompatible with the latest cygwin distributions.
@ -131,7 +192,7 @@ topic).
The solution ... well, you can wait for Altera ... or build as
set of tools for linux.
4.3 No native gcc
5.3 No native gcc
------------------
I'm not sure how this one slipped through the cracks ... but it is
a real pain. Basically, if you want to build anything for the native
@ -140,9 +201,11 @@ and the old version of cygwin makes locating one challenging.
The solution ... same as above. Just download the gcc source from
Altera and build up a set of cross tools for your favorite linux
distro.
distro. Anybody who wants to use an already precompiled NIOS cross
toolchain can it found in the CDK4NIOS project hosted by Source
Forge at http://cdk4nios.sourceforge.net.
4.4 Can't build default U-Boot
5.4 Can't build default U-Boot
-------------------------------
By default, when you build U-Boot you will be building some native
tools along with the target elf, bin, and srec files. Without a
@ -167,7 +230,7 @@ environment.o: environment.c ../tools/envcrc
BTW, thats a 'zero' ... not the letter 'O'.
5. HELP WANTED
6. HELP WANTED
---------------
There are plenty of areas where help is needed. Here's are some ideas
@ -190,3 +253,6 @@ Regards,
--Scott
<smcnutt@psyent.com>
--Stephan
<linz@li-pro.net>

140
doc/README.nios_CFG_NIOS_CPU Normal file
View File

@ -0,0 +1,140 @@
===============================================================================
C F G _ N I O S _ C P U _ * v s . N I O S S D K
===============================================================================
When ever you have to make a new NIOS CPU configuration you can use this table
as a reference list to the original NIOS SDK symbols made by Alteras SOPC
Builder. Look into excalibur.h and excalibur.s in your SDK path cpu_sdk/inc.
Symbols beginning with a '[ptf]:' are coming from your SOPC sytem description
(PTF file) in sections WIZARD_SCRIPT_ARGUMENTS or SYSTEM_BUILDER_INFO.
C O R E N I O S S D K [1],[7]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_CLK nasys_clock_freq
CFG_NIOS_CPU_ICACHE nasys_icache_size
CFG_NIOS_CPU_DCACHE nasys_dcache_size
CFG_NIOS_CPU_REG_NUMS nasys_nios_num_regs
CFG_NIOS_CPU_MUL __nios_use_multiply__
CFG_NIOS_CPU_MSTEP __nios_use_mstep__
CFG_NIOS_CPU_STACK nasys_stack_top
CFG_NIOS_CPU_VEC_BASE nasys_vector_table
CFG_NIOS_CPU_VEC_SIZE nasys_vector_table_size
CFG_NIOS_CPU_VEC_NUMS
CFG_NIOS_CPU_RST_VECT nasys_reset_address
CFG_NIOS_CPU_DBG_CORE nasys_debug_core
CFG_NIOS_CPU_RAM_BASE na_onchip_ram_64_kbytes
CFG_NIOS_CPU_RAM_SIZE na_onchip_ram_64_kbytes_size
CFG_NIOS_CPU_ROM_BASE na_boot_monitor_rom
CFG_NIOS_CPU_ROM_SIZE na_boot_monitor_rom_size
CFG_NIOS_CPU_OCI_BASE nasys_oci_core
CFG_NIOS_CPU_OCI_SIZE
CFG_NIOS_CPU_SRAM_BASE na_ext_ram nasys_program_mem
nasys_data_mem
CFG_NIOS_CPU_SRAM_SIZE na_ext_ram_size nasys_program_mem_size
nasys_data_mem_size
CFG_NIOS_CPU_SDRAM_BASE na_sdram
CFG_NIOS_CPU_SDRAM_SIZE na_sdram_size
CFG_NIOS_CPU_FLASH_BASE na_ext_flash nasys_main_flash
nasys_am29lv065d_flash_0
nasys_flash_0
CFG_NIOS_CPU_FLASH_SIZE na_ext_flash_size nasys_main_flash_size
T I M E R N I O S S D K [3]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_TIMER_NUMS nasys_timer_count
CFG_NIOS_CPU_TIMER[0-9] nasys_timer_[0-9]
CFG_NIOS_CPU_TIMER[0-9]_IRQ nasys_timer_[0-9]_irq
CFG_NIOS_CPU_TIMER[0-9]_PER [ptf]:period
[ptf]:period_units
[ptf]:mult
CFG_NIOS_CPU_TIMER[0-9]_AR [ptf]:always_run
CFG_NIOS_CPU_TIMER[0-9]_FP [ptf]:fixed_period
CFG_NIOS_CPU_TIMER[0-9]_SS [ptf]:snapshot
U A R T N I O S S D K [2]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_UART_NUMS nasys_uart_count
CFG_NIOS_CPU_UART[0-9] nasys_uart_[0-9]
CFG_NIOS_CPU_UART[0-9]_IRQ nasys_uart_[0-9]_irq
CFG_NIOS_CPU_UART[0-9]_BR [ptf]:baud
CFG_NIOS_CPU_UART[0-9]_DB [ptf]:data_bits
CFG_NIOS_CPU_UART[0-9]_SB [ptf]:stop_bits
CFG_NIOS_CPU_UART[0-9]_PA [ptf]:parity
CFG_NIOS_CPU_UART[0-9]_HS [ptf]:use_cts_rts
CFG_NIOS_CPU_UART[0-9]_EOP [ptf]:use_eop_register
P I O N I O S S D K [4]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_PIO_NUMS nasys_pio_count
CFG_NIOS_CPU_PIO[0-9] nasys_pio_[0-9]
CFG_NIOS_CPU_PIO[0-9]_IRQ nasys_pio_[0-9]_irq
CFG_NIOS_CPU_PIO[0-9]_BITS [ptf]:Data_Width
CFG_NIOS_CPU_PIO[0-9]_TYPE [ptf]:has_tri
[ptf]:has_out
[ptf]:has_in
CFG_NIOS_CPU_PIO[0-9]_CAP [ptf]:capture
CFG_NIOS_CPU_PIO[0-9]_EDGE [ptf]:edge_type
CFG_NIOS_CPU_PIO[0-9]_ITYPE [ptf]:irq_type
S P I N I O S S D K [6]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_SPI_NUMS nasys_spi_count
CFG_NIOS_CPU_SPI[0-9] nasys_spi_[0-9]
CFG_NIOS_CPU_SPI[0-9]_IRQ nasys_spi_[0-9]_irq
CFG_NIOS_CPU_SPI[0-9]_BITS [ptf]:databits
CFG_NIOS_CPU_SPI[0-9]_MA [ptf]:ismaster
CFG_NIOS_CPU_SPI[0-9]_SLN [ptf]:numslaves
CFG_NIOS_CPU_SPI[0-9]_TCLK [ptf]:targetclock
CFG_NIOS_CPU_SPI[0-9]_TDELAY [ptf]:targetdelay
CFG_NIOS_CPU_SPI[0-9]_* [ptf]:*
I D E N I O S S D K
-------------------------------------------------------------------------------
CFG_NIOS_CPU_IDE_NUMS nasys_usersocket_count
CFG_NIOS_CPU_IDE[0-9] nasys_usersocket_[0-9]
A S M I N I O S S D K [5]
-------------------------------------------------------------------------------
CFG_NIOS_CPU_ASMI_NUMS nasys_asmi_count
CFG_NIOS_CPU_ASMI[0-9] nasys_asmi_[0-9]
CFG_NIOS_CPU_ASMI[0-9]_IRQ nasys_asmi_[0-9]_irq
E t h e r n e t ( L A N ) N I O S S D K
-------------------------------------------------------------------------------
CFG_NIOS_CPU_LAN_NUMS
CFG_NIOS_CPU_LAN[0-9]_BASE na_lan91c111
CFG_NIOS_CPU_LAN[0-9]_OFFS LAN91C111_REGISTERS_OFFSET
CFG_NIOS_CPU_LAN[0-9]_IRQ na_lan91c111_irq
CFG_NIOS_CPU_LAN[0-9]_BUSW LAN91C111_DATA_BUS_WIDTH
CFG_NIOS_CPU_LAN[0-9]_TYPE
s y s t e m c o m p o s i n g N I O S S D K
-------------------------------------------------------------------------------
CFG_NIOS_CPU_TICK_TIMER (na_low_priority_timer2)
CFG_NIOS_CPU_USER_TIMER (na_timer1)
CFG_NIOS_CPU_BUTTON_PIO (na_button_pio)
CFG_NIOS_CPU_LCD_PIO (na_lcd_pio)
CFG_NIOS_CPU_LED_PIO (na_led_pio)
CFG_NIOS_CPU_SEVENSEG_PIO (na_seven_seg_pio)
CFG_NIOS_CPU_RECONF_PIO (na_reconfig_request_pio)
CFG_NIOS_CPU_CFPRESENT_PIO (na_cf_present_pio)
CFG_NIOS_CPU_CFPOWER_PIO (na_cf_power_pio)
CFG_NIOS_CPU_CFATASEL_PIO (na_cf_ata_select_pio)
CFG_NIOS_CPU_USER_SPI (na_spi)
===============================================================================
R E F E R E N C E S
===============================================================================
[1] http://www.altera.com/literature/ds/ds_nioscpu.pdf
[2] http://www.altera.com/literature/ds/ds_nios_uart.pdf
[3] http://www.altera.com/literature/ds/ds_nios_timer.pdf
[4] http://www.altera.com/literature/ds/ds_nios_pio.pdf
[5] http://www.altera.com/literature/ds/ds_nios_asmi.pdf
[6] http://www.altera.com/literature/ds/ds_nios_spi.pdf
[7] http://www.altera.com/literature/ds/ds_legacy_sdram_ctrl.pdf
===============================================================================
Stephan Linz <linz@li-pro.net>

192
doc/README.nios_DK Normal file
View File

@ -0,0 +1,192 @@
===============================================================================
H A R D W A R E O V E R V I E W
===============================================================================
===============|===============|===============|===============|===============
| DK20K200 | DK1C20 | DK1S10 | DK1S40
---------------|---------------|---------------|---------------|---------------
| | | |
Schem. Nr. | Nios Dev.Brd. | P06-08713-00 | P06-08468-01 | P06-09178-00
Rev. | pilot. | 01 | 01 | 00
Date | 2001/02/06 | 2003/02/20 | 2003/02/14 | 2003/05/14
[1] | | | |
===============|===============|===============|===============|===============
| | | |
FPGA | "APEX" | "Cyclon" | "Stratix" | "Stratix"
| EP20K200E | EP1C20 | EP1S10 | EP1S40
| | |
| (484 FBGA) | (400 FBGA) | (780 FBGA)
[2],[3],[4] | | |
---------------|---------------|---------------|---------------|---------------
| |
Clock (OSC) | 33.333 MHz | 50 MHz
| | (with ext. supply)
|
| PI49FCT3805
[5] |
---------------|---------------|---------------|---------------|---------------
| |
Flash | 1 MByte | 8 MByte
| |
| AM29LV800BB | AM29LV065DU120REI
| 8/16 bit bus | 8 bit bus
| 1 chip | 1 chip
[6],[7] | |
---------------|---------------|---------------|---------------|---------------
| | |
serial | no such | 4 MBits | no such
Flash | | |
| | EPCS4SI8 |
[8] | | |
---------------|---------------|---------------|---------------|---------------
| |
Compact | no such, as | see below: prototype adapter
Flash (CF) | module only |
| |
---------------|---------------|---------------|---------------|---------------
| |
SRAM | 256 KByte | 1 MByte
| |
| IDT71V016S | IDT71V416S10PH
| 32 bit bus | 32 bit bus
| 2 chips | 2 chips
| interlaced | interlaced
[9],[10] | |
---------------|---------------|---------------|---------------|---------------
| |
SDRAM | SODIMM only | 16 MByte
| |
| | MT48LC4M32B2TG-7
| 64 bit bus | 32 bit bus
| | 1 chip
[11] | |
===============|===============|===============|===============|===============
| |
serial I/O | 1 RS232 | 2 RS232
| |
| LTC1386 | MAX3237CAI
| |
| port 1: | port 1:
| RxD / TxD, | RxD / TxD,
| RTS / CTS | RTS / CTS, DTR / DSR, DCD, RI
| |
| ! ! ! ! ! ! | port 2: | port 2:
| RTS/CTS can | RxD / TxD | RxD / TxD
| be RxD/TxD | | RTS / CTS, DTR / DSR
| of 2nd port | | DCD, RI
[12],[13] | ! ! ! ! ! ! | |
---------------|---------------|---------------|---------------|---------------
| |
Ethernet | no such, as | 1 10BaseT / 100BaseT
| module only |
| | LAN91C111-NE
| | 32 bit bus
| | no external EEPROM
| | LEDA# for link
| | LEDB# for Rx / Tx
[14] | |
===============|===============|===============|===============|===============
| |
user | 8 | no such
switches | SW[7..0] |
| |
---------------|---------------|---------------|---------------|---------------
|
user push | 4
buttons | PB[3..0]
|
---------------|---------------|---------------|---------------|---------------
| |
user LEDs | 2 | 8
| LED[1..0] | LED[7..0]
| |
---------------|---------------|---------------|---------------|---------------
|
user seven | 2
segment | HEX[1..0][G..A,DP]
|
===============|===============|===============|===============|===============
| |
3.3V proto- | w/o level | no such -- only 5V
type adapter | shift buffer |
| |
| 40 I/O pins |
| 1 card sel. |
| 1 reset out. |
| 1 OSC clock |
| 1 CPU clock |
| 1 clock out. |
| |
---------------|---------------|---------------|---------------|---------------
| |
5V prototype | with level | 2 ports -- both card ports supplied with its
adapter | shift buffer | own level shift buffer
| |
| 40 I/O pins | port 1 & 2:
| 1 card sel. | 41 I/O pins
| 1 Vee ? ? ? | 1 card select
| 1 reset out. | 1 reset output (from dev/board)
| 1 OSC clock | 1 OSC clock (from dev/board)
| 1 CPU clock | 1 CPU clock (from dev/board)
| 1 clock inp. | 1 clock input (to dev/board)
| |
| | (special) port 1:
| | 1 CF select
| | 1 CF present
| | 1 CF ATA select
| | 1 CF power
| |
| | NOTE: Both card ports are prepared for raw
| | IDE working. You can connect such
| | devices directly to the 40 pin header.
| | The signal PDIAG (passed diagnostic)
| | is not connected to any I/O signal.
| | Card port 1 is hard wired to the on
| | board Copact Flash adapter together
| | with all other signals needed by CF
| | cards. Hot plug should be working too.
[15],[16] | |
===============|===============|===============|===============|===============
| |
config. CPLD | EPM7064 | EPM7128
| |
(alternative | decition by | decision by
FPGA conf.) | jumper | push button
| |
| FPGA config. | FPGA config. | FPGA config.
| from Flash | from Flash | from Flash
| only | and EPCS4 | only
| | |
===============|===============|===============|===============|===============
===============================================================================
===============================================================================
R E F E R E N C E S
===============================================================================
[1] http://www.altera.com/literature/lit-nio.jsp
[2] http://www.altera.com/literature/lit-apx.jsp
[3] http://www.altera.com/literature/lit-cyc.jsp
[4] http://www.altera.com/literature/lit-stx.jsp
[5] http://www.pericom.com/pdf/datasheets/PI49FCT3805.pdf
http://www.pericom.com/products/clock/psempart.php?productID=PI49FCT3805
[6] http://www.amd.com/us-en/FlashMemory/ProductInformation/0,,37_1447_1623_1468^1532,00.html
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/21490.pdf
[7] http://www.amd.com/us-en/FlashMemory/ProductInformation/0,,37_1447_1623_1468^1596,00.html
http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/23544b.pdf
[8] http://www.altera.com/literature/lit-config.html
http://preview.altera.com/literature/ds/micron.pdf
[9] http://www.idt.com/products/pages/Asynchronous_SRAMs-71V016SA.html
[10] http://www.idt.com/products/pages/Asynchronous_SRAMs-71V416SL.html
[11] http://www.micron.com/products/dram/sdram/part.aspx?part=MT48LC4M32B2TG-7
[12] http://www.linear.com/prod/datasheet.html?datasheet=33
http://www.linear.com/pdf/1386fa.pdf
[13] http://www.maxim-ic.com/quick_view2.cfm/qv_pk/1068/ln/en
http://pdfserv.maxim-ic.com/en/ds/MAX3222-MAX3241.pdf
[14] http://www.smsc.com/main/catalog/lan91c111.html
[15] http://www.t13.org/index.html
[16] http://www.compactflash.org/faqs/faq.htm
===============================================================================
Stephan Linz <linz@li-pro.net>

2
drivers/dataflash.c
View File

@ -159,7 +159,7 @@ void dataflash_print_info (void)
dataflash_info[i].Device.pages_size,
(unsigned int) dataflash_info[i].logical_address);
for (j=0; j< NB_DATAFLASH_AREA; j++) {
printf ("Area %i:\t%08X to %08X %s\n", j,
printf ("Area %i:\t%08lX to %08lX %s\n", j,
dataflash_info[i].Device.area_list[j].start,
dataflash_info[i].Device.area_list[j].end,
(dataflash_info[i].Device.area_list[j].protected ==

40
drivers/dc2114x.c
View File

@ -27,7 +27,6 @@
#include <net.h>
#include <pci.h>
#undef DEBUG
#undef DEBUG_SROM
#undef DEBUG_SROM2
@ -162,16 +161,20 @@ static int tx_new; /* TX descriptor ring pointer */
static char rxRingSize;
static char txRingSize;
#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
static void sendto_srom(struct eth_device* dev, u_int command, u_long addr);
static int getfrom_srom(struct eth_device* dev, u_long addr);
static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len);
static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, int addr_len);
static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr,int cmd,int cmd_len);
static int do_read_eeprom(struct eth_device *dev,u_long ioaddr,int location,int addr_len);
#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
#ifdef UPDATE_SROM
static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value);
static void update_srom(struct eth_device *dev, bd_t *bis);
#endif
#ifndef CONFIG_TULIP_FIX_DAVICOM
static int read_srom(struct eth_device *dev, u_long ioaddr, int index);
static void read_hw_addr(struct eth_device* dev, bd_t * bis);
#endif /* CONFIG_TULIP_FIX_DAVICOM */
static void send_setup_frame(struct eth_device* dev, bd_t * bis);
static int dc21x4x_init(struct eth_device* dev, bd_t* bis);
@ -276,10 +279,7 @@ int dc21x4x_initialize(bd_t *bis)
pci_read_config_dword(devbusfn, PCI_BASE_ADDRESS_1, &iobase);
iobase &= PCI_BASE_ADDRESS_MEM_MASK;
#endif
#ifdef DEBUG
printf("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
#endif
debug ("dc21x4x: DEC 21142 PCI Device @0x%x\n", iobase);
dev = (struct eth_device*) malloc(sizeof *dev);
@ -530,9 +530,9 @@ Done:
return;
}
#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
/* SROM Read and write routines.
*/
static void
sendto_srom(struct eth_device* dev, u_int command, u_long addr)
{
@ -604,10 +604,13 @@ static int do_read_eeprom(struct eth_device *dev, u_long ioaddr, int location, i
return retval;
}
#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
/* This executes a generic EEPROM command, typically a write or write enable.
It returns the data output from the EEPROM, and thus may also be used for
reads. */
/* This executes a generic EEPROM command, typically a write or write
* enable. It returns the data output from the EEPROM, and thus may
* also be used for reads.
*/
#if defined(UPDATE_SROM) || !defined(CONFIG_TULIP_FIX_DAVICOM)
static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd_len)
{
unsigned retval = 0;
@ -643,7 +646,9 @@ static int do_eeprom_cmd(struct eth_device *dev, u_long ioaddr, int cmd, int cmd
return retval;
}
#endif /* UPDATE_SROM || !CONFIG_TULIP_FIX_DAVICOM */
#ifndef CONFIG_TULIP_FIX_DAVICOM
static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
{
int ee_addr_size = do_read_eeprom(dev, ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
@ -652,6 +657,7 @@ static int read_srom(struct eth_device *dev, u_long ioaddr, int index)
(((SROM_READ_CMD << ee_addr_size) | index) << 16)
| 0xffff, 3 + ee_addr_size + 16);
}
#endif /* CONFIG_TULIP_FIX_DAVICOM */
#ifdef UPDATE_SROM
static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_value)
@ -699,6 +705,7 @@ static int write_srom(struct eth_device *dev, u_long ioaddr, int index, int new_
}
#endif
#ifndef CONFIG_TULIP_FIX_DAVICOM
static void read_hw_addr(struct eth_device *dev, bd_t *bis)
{
u_short tmp, *p = (short *)(&dev->enetaddr[0]);
@ -712,9 +719,7 @@ static void read_hw_addr(struct eth_device *dev, bd_t *bis)
if ((j == 0) || (j == 0x2fffd)) {
memset (dev->enetaddr, 0, ETH_ALEN);
#ifdef DEBUG
printf("Warning: can't read HW address from SROM.\n");
#endif
debug ("Warning: can't read HW address from SROM.\n");
goto Done;
}
@ -726,6 +731,7 @@ Done:
#endif
return;
}
#endif /* CONFIG_TULIP_FIX_DAVICOM */
#ifdef UPDATE_SROM
static void update_srom(struct eth_device *dev, bd_t *bis)
@ -760,6 +766,6 @@ static void update_srom(struct eth_device *dev, bd_t *bis)
write_srom(dev, DE4X5_APROM, i, eeprom[i]);
}
}
#endif
#endif /* UPDATE_SROM */
#endif
#endif /* CFG_CMD_NET && CONFIG_NET_MULTI && CONFIG_TULIP */

2
drivers/smc91111.h
View File

@ -306,7 +306,7 @@ typedef unsigned long int dword;
#define RPC_LED_100 (0x05) /* LED = 100Mbps link dectect */
#define RPC_LED_TX (0x06) /* LED = TX packet occurred */
#define RPC_LED_RX (0x07) /* LED = RX packet occurred */
#if defined(CONFIG_DK1C20)
#if defined(CONFIG_DK1C20) || defined(CONFIG_DK1S10)
/* buggy schematic: LEDa -> yellow, LEDb --> green */
#define RPC_DEFAULT ( RPC_SPEED | RPC_DPLX | RPC_ANEG \
| (RPC_LED_TX_RX << RPC_LSXA_SHFT) \

132
include/asm-nios/status_led.h Normal file
View File

@ -0,0 +1,132 @@
/*
* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
* Stephan Linz <linz@li-pro.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* asm-nios/status_led.h
*
* NIOS PIO based status led support functions
*/
#ifndef __ASM_STATUS_LED_H__
#define __ASM_STATUS_LED_H__
#include <nios-io.h>
/* led_id_t is unsigned int mask */
typedef unsigned int led_id_t;
#ifdef STATUS_LED_WRONLY /* emulate read access */
static led_id_t __led_portval = 0;
#endif
static inline void __led_init (led_id_t mask, int state)
{
nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE;
#ifdef STATUS_LED_WRONLY /* emulate read access */
#if (STATUS_LED_ACTIVE == 0)
if (state == STATUS_LED_ON)
__led_portval &= ~mask;
else
__led_portval |= mask;
#else
if (state == STATUS_LED_ON)
__led_portval |= mask;
else
__led_portval &= ~mask;
#endif
piop->data = __led_portval;
#else /* !STATUS_LED_WRONLY */
#if (STATUS_LED_ACTIVE == 0)
if (state == STATUS_LED_ON)
piop->data &= ~mask;
else
piop->data |= mask;
#else
if (state == STATUS_LED_ON)
piop->data |= mask;
else
piop->data &= ~mask;
#endif
piop->direction |= mask;
#endif /* STATUS_LED_WRONLY */
}
static inline void __led_toggle (led_id_t mask)
{
nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE;
#ifdef STATUS_LED_WRONLY /* emulate read access */
__led_portval ^= mask;
piop->data = __led_portval;
#else /* !STATUS_LED_WRONLY */
piop->data ^= mask;
#endif /* STATUS_LED_WRONLY */
}
static inline void __led_set (led_id_t mask, int state)
{
nios_pio_t *piop = (nios_pio_t*)STATUS_LED_BASE;
#ifdef STATUS_LED_WRONLY /* emulate read access */
#if (STATUS_LED_ACTIVE == 0)
if (state == STATUS_LED_ON)
__led_portval &= ~mask;
else
__led_portval |= mask;
#else
if (state == STATUS_LED_ON)
__led_portval |= mask;
else
__led_portval &= ~mask;
#endif
piop->data = __led_portval;
#else /* !STATUS_LED_WRONLY */
#if (STATUS_LED_ACTIVE == 0)
if (state == STATUS_LED_ON)
piop->data &= ~mask;
else
piop->data |= mask;
#else
if (state == STATUS_LED_ON)
piop->data |= mask;
else
piop->data &= ~mask;
#endif
#endif /* STATUS_LED_WRONLY */
}
#endif /* __ASM_STATUS_LED_H__ */

595
include/configs/DK1C20.h
View File

@ -1,6 +1,7 @@
/*
* (C) Copyright 2003, Psyent Corporation <www.psyent.com>
* Scott McNutt <smcnutt@psyent.com>
* Stephan Linz <linz@li-pro.net>
*
* See file CREDITS for list of people who contributed to this
* project.
@ -24,22 +25,293 @@
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* NIOS CPU configuration.
*
* Here we must define CPU dependencies. Any unsupported option have to
* be defined with zero, example CPU without data cache / OCI:
*
* #define CFG_NIOS_CPU_ICACHE 4096
* #define CFG_NIOS_CPU_DCACHE 0
* #define CFG_NIOS_CPU_OCI_BASE 0
* #define CFG_NIOS_CPU_OCI_SIZE 0
*/
#if defined(CONFIG_NIOS_SAFE_32)
/* TODO */
#elif defined(CONFIG_NIOS_STANDARD_32)
/* CPU core */
#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */
#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */
#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */
#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */
#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */
#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */
#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */
#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */
#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */
#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */
/* yes(1) */
/* on-chip extensions */
#define CFG_NIOS_CPU_RAM_BASE 0 /* on chip RAM addr */
#define CFG_NIOS_CPU_RAM_SIZE 0 /* size */
#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */
#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */
#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */
#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */
/* timer */
#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */
#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */
#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */
#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */
#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */
#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */
#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */
#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */
/* yes(1) */
/* serial i/o */
#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */
#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */
#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */
#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */
#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */
#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */
#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */
/* odd(1) */
/* even(2) */
#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */
/* crts(1) */
#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */
/* yes(1) */
/* parallel i/o */
#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */
#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */
#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */
#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */
#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */
#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */
#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */
#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */
#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */
#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */
#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */
#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */
#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */
#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */
#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */
#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */
#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */
#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */
#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */
#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */
#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */
#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */
#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */
#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */
#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */
#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
/* IDE i/f */
#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */
#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */
/* active serial memory i/f */
#define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */
#define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */
#define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */
/* memory accessibility */
#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */
#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */
#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */
#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */
#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */
#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */
/* LAN */
#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */
#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */
#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */
#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */
#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/
#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */
/* cs8900(1) */
/* ex: alteramac(2) */
/* symbolic redefinition (undef, if not present) */
#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */
#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/
#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */
#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */
#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */
#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */
#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */
#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */
#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */
#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */
#else
#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
#endif
/*------------------------------------------------------------------------
* BOARD/CPU -- TOP-LEVEL
*----------------------------------------------------------------------*/
#define CONFIG_NIOS 1 /* NIOS-32 core */
#define CONFIG_DK1C20 1 /* Cyclone DK-1C20 board*/
#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clock */
#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
#define CFG_HZ 1000 /* 1 msec time tick */
#undef CFG_CLKS_IN_HZ
#define CONFIG_BOARD_PRE_INIT 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
* BASE ADDRESSES
* BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
*----------------------------------------------------------------------*/
#define CFG_FLASH_BASE 0x00000000 /* Flash memory base */
#define CFG_SRAM_BASE 0x00800000 /* External SRAM */
#define CFG_SRAM_SIZE 0x00100000 /* 1 MByte */
#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */
#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */
#define CFG_VECT_BASE 0x008fff00 /* Vector table addr */
#if (CFG_NIOS_CPU_SDRAM_SIZE != 0)
#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE
#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE
#else
#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
#endif
#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE
#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE
#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE
/*------------------------------------------------------------------------
* MEMORY ORGANIZATION - For the most part, you can put things pretty
@ -53,59 +325,322 @@
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
#define CFG_ENV_SIZE 0x10000 /* 64 KByte (1 sector) */
#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE -CFG_GBL_DATA_SIZE)
#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
/*------------------------------------------------------------------------
* FLASH
* FLASH (AM29LV065D)
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE
#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE
#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */
#else
#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
#endif
/*------------------------------------------------------------------------
* ENVIRONMENT
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
#define CFG_ENV_ADDR 0x00000000 /* Mem addr of env */
#define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */
#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */
#else
#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */
#endif
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
#define CFG_NIOS_CONSOLE 0x00920900 /* Cons uart base addr */
#if (CFG_NIOS_CPU_UART_NUMS != 0)
#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
#if (CFG_NIOS_CPU_UART0_BR != 0)
#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR
#else
#undef CFG_NIOS_FIXEDBAUD
#define CONFIG_BAUDRATE 115200
#endif
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#else
#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
#endif
/*------------------------------------------------------------------------
* TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT,
* so an avalon bus timer is required.
*----------------------------------------------------------------------*/
#define CFG_NIOS_TMRBASE 0x009209e0
#define CFG_NIOS_TMRIRQ 50
#define CFG_NIOS_TMRMS 10
#if (CFG_NIOS_CPU_TIMER_NUMS != 0)
#if (CFG_NIOS_CPU_TICK_TIMER == 0)
#error *** CFG_ERROR: tick timer at TIMER0 not supported, expand your config.h
#elif (CFG_NIOS_CPU_TICK_TIMER == 1)
#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
#else
#error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ
#endif
#endif /* CFG_NIOS_CPU_TICK_TIMER */
#else
#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
#endif
/*------------------------------------------------------------------------
* Ethernet -- needs work!
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_LAN_NUMS == 1)
#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
/****************************************************/
/* !!! LAN91C111 works for NIOS with patch only !!! */
/****************************************************/
#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
#define CONFIG_SMC91111_BASE 0x00910300 /* Base address */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC_USE_32_BIT /* 32-bit data rd/wr */
#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
#define CONFIG_SMC_USE_32_BIT 1
#else /* no */
#undef CONFIG_SMC_USE_32_BIT
#endif
#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */
/********************************************/
/* !!! CS8900 is __not__ tested on NIOS !!! */
/********************************************/
#define CONFIG_DRIVER_CS8900 /* Using CS8900 */
#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
#undef CS8900_BUS16
#define CS8900_BUS32 1
#else /* no */
#define CS8900_BUS16 1
#undef CS8900_BUS32
#endif
#else
#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
#endif
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
#else
#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
#endif
/*------------------------------------------------------------------------
* STATUS LEDs
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_PIO_NUMS != 0)
#if (CFG_NIOS_CPU_LED_PIO == 0)
#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 1)
#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 2)
#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2
#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS
#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
#if (CFG_NIOS_CPU_PIO2_TYPE == 1)
#define STATUS_LED_WRONLY 1
#else
#undef STATUS_LED_WRONLY
#endif
#elif (CFG_NIOS_CPU_LED_PIO == 3)
#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 4)
#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 5)
#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 6)
#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 7)
#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 8)
#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 9)
#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
#else
#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
#endif
#define CONFIG_STATUS_LED 1 /* enable status led driver */
#define STATUS_LED_BIT (1 << 0) /* LED[0] */
#define STATUS_LED_STATE STATUS_LED_BLINKING
#define STATUS_LED_BOOT_STATE STATUS_LED_OFF
#define STATUS_LED_PERIOD (CFG_HZ / 10) /* ca. 1 Hz */
#define STATUS_LED_BOOT 0 /* boot LED */
#if (STATUS_LED_BITS > 1)
#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */
#define STATUS_LED_STATE1 STATUS_LED_OFF
#define STATUS_LED_PERIOD1 (CFG_HZ / 50) /* ca. 5 Hz */
#define STATUS_LED_RED 1 /* fail LED */
#endif
#if (STATUS_LED_BITS > 2)
#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */
#define STATUS_LED_STATE2 STATUS_LED_OFF
#define STATUS_LED_PERIOD2 (CFG_HZ / 10) /* ca. 1 Hz */
#define STATUS_LED_YELLOW 2 /* info LED */
#endif
#if (STATUS_LED_BITS > 3)
#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */
#define STATUS_LED_STATE3 STATUS_LED_OFF
#define STATUS_LED_PERIOD3 (CFG_HZ / 10) /* ca. 1 Hz */
#define STATUS_LED_GREEN 3 /* info LED */
#endif
#define STATUS_LED_PAR 1 /* makes status_led.h happy */
#endif /* CFG_NIOS_CPU_PIO_NUMS */
/*------------------------------------------------------------------------
* SEVEN SEGMENT LED DISPLAY
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_PIO_NUMS != 0)
#if (CFG_NIOS_CPU_SEVENSEG_PIO == 0)
#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1)
#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2)
#error *** CFG_ERROR: status LEDs at PIO2 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3)
#define SEVENSEG_BASE CFG_NIOS_CPU_PIO3
#define SEVENSEG_BITS CFG_NIOS_CPU_PIO3_BITS
#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */
#if (CFG_NIOS_CPU_PIO3_TYPE == 1)
#define SEVENSEG_WRONLY 1
#else
#undef SEVENSEG_WRONLY
#endif
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4)
#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5)
#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6)
#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7)
#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8)
#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9)
#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
#else
#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
#endif
#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */
/*
* Dual 7-Segment Display pin assignment -- read more in your
* "Nios Development Board Reference Manual"
*
*
* (U8) HI:D[15..8] (U9) LO:D[7..0]
* ______ ______
* | D14 | | D6 |
* | | | |
* D9| |D13 D1| |D5
* |______| |______| ___
* | D8 | | D0 | | A |
* | | | | F|___|B
* D10| |D12 D2| |D4 | G |
* |______| |______| E|___|C
* D11 * D3 * D *
* D15 D7 DP
*
*/
#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */
#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */
#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */
#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */
#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */
#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */
#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */
#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */
#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */
#endif /* CFG_NIOS_CPU_PIO_NUMS */
/*------------------------------------------------------------------------
* COMMANDS
*----------------------------------------------------------------------*/
@ -152,17 +687,25 @@
* MISC
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "==> " /* Monitor Command Prompt */
#define CFG_PROMPT "DK1C20 > " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args */
#define CFG_MAXARGS 16 /* max number of command args*/
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#undef CFG_CLKS_IN_HZ
#define CFG_HZ 1000 /* decr freq: 1ms ticks */
#define CFG_LOAD_ADDR 0x00800000 /* Default load address */
#define CFG_MEMTEST_START 0x00000000
#define CFG_MEMTEST_END 0x00000000
#if (CFG_SRAM_SIZE != 0)
#define CFG_LOAD_ADDR CFG_SRAM_BASE /* Default load address */
#else
#undef CFG_LOAD_ADDR
#endif
#if (CFG_SDRAM_SIZE != 0)
#define CFG_MEMTEST_START CFG_SDRAM_BASE /* SDRAM til stack area */
#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */
#else
#undef CFG_MEMTEST_START
#undef CFG_MEMTEST_END
#endif
#endif /* __CONFIG_H */

710
include/configs/DK1S10.h Normal file
View File

@ -0,0 +1,710 @@
/*
* (C) Copyright 2003, Li-Pro.Net <www.li-pro.net>
* Stephan Linz <linz@li-pro.net>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#ifndef __CONFIG_H
#define __CONFIG_H
/*
* NIOS CPU configuration.
*
* Here we must define CPU dependencies. Any unsupported option have to
* be defined with zero, example CPU without data cache / OCI:
*
* #define CFG_NIOS_CPU_ICACHE 4096
* #define CFG_NIOS_CPU_DCACHE 0
* #define CFG_NIOS_CPU_OCI_BASE 0
* #define CFG_NIOS_CPU_OCI_SIZE 0
*/
#if defined(CONFIG_NIOS_SAFE_32)
/* TODO */
#elif defined(CONFIG_NIOS_STANDARD_32)
/* CPU core */
#define CFG_NIOS_CPU_CLK 50000000 /* NIOS CPU clock */
#define CFG_NIOS_CPU_ICACHE (4 * 1024) /* instruction cache */
#define CFG_NIOS_CPU_DCACHE (4 * 1024) /* data cache */
#define CFG_NIOS_CPU_REG_NUMS 256 /* number of register */
#define CFG_NIOS_CPU_MUL 0 /* 16x16 MUL: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_MSTEP 1 /* 16x16 MSTEP: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_STACK 0x008fff00 /* stack top addr */
#define CFG_NIOS_CPU_VEC_BASE 0x008fff00 /* IRQ vectors addr */
#define CFG_NIOS_CPU_VEC_SIZE 256 /* size */
#define CFG_NIOS_CPU_VEC_NUMS 64 /* numbers */
#define CFG_NIOS_CPU_RST_VECT 0x00920000 /* RESET vector addr */
#define CFG_NIOS_CPU_DBG_CORE 0 /* CPU debug: no(0) */
/* yes(1) */
/* on-chip extensions */
#define CFG_NIOS_CPU_RAM_BASE 0x00900000 /* on chip RAM addr */
#define CFG_NIOS_CPU_RAM_SIZE (64 * 1024) /* 64 KB size */
#define CFG_NIOS_CPU_ROM_BASE 0x00920000 /* on chip ROM addr */
#define CFG_NIOS_CPU_ROM_SIZE (2 * 1024) /* 2 KB size */
#define CFG_NIOS_CPU_OCI_BASE 0x00920800 /* OCI core addr */
#define CFG_NIOS_CPU_OCI_SIZE 256 /* size */
/* timer */
#define CFG_NIOS_CPU_TIMER_NUMS 2 /* number of timer */
#define CFG_NIOS_CPU_TIMER0 0x00920940 /* TIMER0 addr */
#define CFG_NIOS_CPU_TIMER0_IRQ 16 /* IRQ */
#define CFG_NIOS_CPU_TIMER0_PER 1000 /* periode usec */
#define CFG_NIOS_CPU_TIMER0_AR 0 /* always run: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_TIMER0_FP 0 /* fixed per: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_TIMER0_SS 1 /* snaphot: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_TIMER1 0x009209e0 /* TIMER1 addr */
#define CFG_NIOS_CPU_TIMER1_IRQ 50 /* IRQ */
#define CFG_NIOS_CPU_TIMER1_PER 10000 /* periode usec */
#define CFG_NIOS_CPU_TIMER1_AR 1 /* always run: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_TIMER1_FP 1 /* fixed per: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_TIMER1_SS 0 /* snaphot: no(0) */
/* yes(1) */
/* serial i/o */
#define CFG_NIOS_CPU_UART_NUMS 1 /* number of uarts */
#define CFG_NIOS_CPU_UART0 0x00920900 /* UART0 addr */
#define CFG_NIOS_CPU_UART0_IRQ 25 /* IRQ */
#define CFG_NIOS_CPU_UART0_BR 115200 /* baudrate var(0) */
#define CFG_NIOS_CPU_UART0_DB 8 /* data bit */
#define CFG_NIOS_CPU_UART0_SB 1 /* stop bit */
#define CFG_NIOS_CPU_UART0_PA 0 /* parity none(0) */
/* odd(1) */
/* even(2) */
#define CFG_NIOS_CPU_UART0_HS 0 /* handshake: no(0) */
/* crts(1) */
#define CFG_NIOS_CPU_UART0_EOP 0 /* eop reg: no(0) */
/* yes(1) */
/* parallel i/o */
#define CFG_NIOS_CPU_PIO_NUMS 8 /* number of parports */
#define CFG_NIOS_CPU_PIO0 0x00920960 /* PIO0 addr */
#define CFG_NIOS_CPU_PIO0_IRQ 40 /* IRQ */
#define CFG_NIOS_CPU_PIO0_BITS 4 /* number of bits */
#define CFG_NIOS_CPU_PIO0_TYPE 2 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO0_CAP 1 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO0_EDGE 3 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO0_ITYPE 2 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO1 0x00920970 /* PIO1 addr */
#undef CFG_NIOS_CPU_PIO1_IRQ /* w/o IRQ */
#define CFG_NIOS_CPU_PIO1_BITS 11 /* number of bits */
#define CFG_NIOS_CPU_PIO1_TYPE 0 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO1_CAP 0 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO1_EDGE 0 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO1_ITYPE 0 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO2 0x00920980 /* PIO2 addr */
#undef CFG_NIOS_CPU_PIO2_IRQ /* w/o IRQ */
#define CFG_NIOS_CPU_PIO2_BITS 8 /* number of bits */
#define CFG_NIOS_CPU_PIO2_TYPE 1 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO2_CAP 0 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO2_EDGE 0 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO2_ITYPE 0 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO3 0x00920990 /* PIO3 addr */
#undef CFG_NIOS_CPU_PIO3_IRQ /* w/o IRQ */
#define CFG_NIOS_CPU_PIO3_BITS 16 /* number of bits */
#define CFG_NIOS_CPU_PIO3_TYPE 1 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO3_CAP 0 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO3_EDGE 0 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO3_ITYPE 0 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO4 0x009209a0 /* PIO4 addr */
#undef CFG_NIOS_CPU_PIO4_IRQ /* w/o IRQ */
#define CFG_NIOS_CPU_PIO4_BITS 1 /* number of bits */
#define CFG_NIOS_CPU_PIO4_TYPE 0 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO4_CAP 0 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO4_EDGE 0 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO4_ITYPE 0 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO5 0x009209b0 /* PIO5 addr */
#define CFG_NIOS_CPU_PIO5_IRQ 35 /* IRQ */
#define CFG_NIOS_CPU_PIO5_BITS 1 /* number of bits */
#define CFG_NIOS_CPU_PIO5_TYPE 2 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO5_CAP 1 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO5_EDGE 3 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO5_ITYPE 2 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO6 0x009209c0 /* PIO6 addr */
#undef CFG_NIOS_CPU_PIO6_IRQ /* w/o IRQ */
#define CFG_NIOS_CPU_PIO6_BITS 1 /* number of bits */
#define CFG_NIOS_CPU_PIO6_TYPE 1 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO6_CAP 0 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO6_EDGE 0 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO6_ITYPE 0 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
#define CFG_NIOS_CPU_PIO7 0x009209d0 /* PIO7 addr */
#undef CFG_NIOS_CPU_PIO7_IRQ /* w/o IRQ */
#define CFG_NIOS_CPU_PIO7_BITS 1 /* number of bits */
#define CFG_NIOS_CPU_PIO7_TYPE 1 /* io type: tris(0) */
/* out(1) */
/* in(2) */
#define CFG_NIOS_CPU_PIO7_CAP 0 /* capture: no(0) */
/* yes(1) */
#define CFG_NIOS_CPU_PIO7_EDGE 0 /* edge type: none(0) */
/* fall(1) */
/* rise(2) */
/* any(3) */
#define CFG_NIOS_CPU_PIO7_ITYPE 0 /* IRQ type: none(0) */
/* level(1)*/
/* edge(2) */
/* IDE i/f */
#define CFG_NIOS_CPU_IDE_NUMS 1 /* number of IDE contr. */
#define CFG_NIOS_CPU_IDE0 0x00920a00 /* IDE0 addr */
/* active serial memory i/f */
#define CFG_NIOS_CPU_ASMI_NUMS 1 /* number of ASMI */
#define CFG_NIOS_CPU_ASMI0 0x00920b00 /* ASMI0 addr */
#define CFG_NIOS_CPU_ASMI0_IRQ 45 /* IRQ */
/* memory accessibility */
#define CFG_NIOS_CPU_SRAM_BASE 0x00800000 /* board SRAM addr */
#define CFG_NIOS_CPU_SRAM_SIZE (1024 * 1024) /* 1 MB size */
#define CFG_NIOS_CPU_SDRAM_BASE 0x01000000 /* board SDRAM addr */
#define CFG_NIOS_CPU_SDRAM_SIZE (16*1024*1024) /* 16 MB size */
#define CFG_NIOS_CPU_FLASH_BASE 0x00000000 /* board Flash addr */
#define CFG_NIOS_CPU_FLASH_SIZE (8*1024*1024) /* 8 MB size */
/* LAN */
#define CFG_NIOS_CPU_LAN_NUMS 1 /* number of LAN i/f */
#define CFG_NIOS_CPU_LAN0_BASE 0x00910000 /* LAN0 addr */
#define CFG_NIOS_CPU_LAN0_OFFS 0x0300 /* offset */
#define CFG_NIOS_CPU_LAN0_IRQ 30 /* IRQ */
#define CFG_NIOS_CPU_LAN0_BUSW 32 /* buswidth*/
#define CFG_NIOS_CPU_LAN0_TYPE 0 /* smc91111(0) */
/* cs8900(1) */
/* ex: alteramac(2) */
/* symbolic redefinition (undef, if not present) */
#define CFG_NIOS_CPU_USER_TIMER 0 /* TIMER0: users choice */
#define CFG_NIOS_CPU_TICK_TIMER 1 /* TIMER1: tick (needed)*/
#define CFG_NIOS_CPU_BUTTON_PIO 0 /* PIO0: buttons */
#define CFG_NIOS_CPU_LCD_PIO 1 /* PIO1: ASCII LCD */
#define CFG_NIOS_CPU_LED_PIO 2 /* PIO2: LED bar */
#define CFG_NIOS_CPU_SEVENSEG_PIO 3 /* PIO3: 7-seg. display */
#define CFG_NIOS_CPU_RECONF_PIO 4 /* PIO4: reconf pin */
#define CFG_NIOS_CPU_CFPRESENT_PIO 5 /* PIO5: CF present IRQ */
#define CFG_NIOS_CPU_CFPOWER_PIO 6 /* PIO6: CF power/sw. */
#define CFG_NIOS_CPU_CFATASEL_PIO 7 /* PIO7: CF ATA select */
#else
#error *** CFG_ERROR: you have to setup right NIOS CPU configuration
#endif
/*------------------------------------------------------------------------
* BOARD/CPU -- TOP-LEVEL
*----------------------------------------------------------------------*/
#define CONFIG_NIOS 1 /* NIOS-32 core */
#define CONFIG_DK1S10 1 /* Stratix DK-1S10 board*/
#define CONFIG_SYS_CLK_FREQ CFG_NIOS_CPU_CLK/* 50 MHz core clock */
#define CFG_HZ 1000 /* 1 msec time tick */
#undef CFG_CLKS_IN_HZ
#define CONFIG_BOARD_PRE_INIT 1 /* enable early board-spec. init*/
/*------------------------------------------------------------------------
* BASE ADDRESSES / SIZE (Flash, SRAM, SDRAM)
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_SDRAM_SIZE != 0)
#define CFG_SDRAM_BASE CFG_NIOS_CPU_SDRAM_BASE
#define CFG_SDRAM_SIZE CFG_NIOS_CPU_SDRAM_SIZE
#else
#error *** CFG_ERROR: you have to setup any SDRAM in NIOS CPU config
#endif
#define CFG_SRAM_BASE CFG_NIOS_CPU_SRAM_BASE
#define CFG_SRAM_SIZE CFG_NIOS_CPU_SRAM_SIZE
#define CFG_VECT_BASE CFG_NIOS_CPU_VEC_BASE
/*------------------------------------------------------------------------
* MEMORY ORGANIZATION - For the most part, you can put things pretty
* much anywhere. This is pretty flexible for Nios. So here we make some
* arbitrary choices & assume that the monitor is placed at the end of
* a memory resource (so you must make sure TEXT_BASE is chosen
* appropriately).
*
* -The heap is placed below the monitor.
* -Global data is placed below the heap.
* -The stack is placed below global data (&grows down).
*----------------------------------------------------------------------*/
#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */
#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/
#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP CFG_GBL_DATA_OFFSET
/*------------------------------------------------------------------------
* FLASH (AM29LV065D)
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
#define CFG_FLASH_BASE CFG_NIOS_CPU_FLASH_BASE
#define CFG_FLASH_SIZE CFG_NIOS_CPU_FLASH_SIZE
#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */
#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */
#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */
#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */
#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */
#else
#error *** CFG_ERROR: you have to setup any Flash memory in NIOS CPU config
#endif
/*------------------------------------------------------------------------
* ENVIRONMENT
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_FLASH_SIZE != 0)
#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */
#define CFG_ENV_ADDR CFG_FLASH_BASE /* Mem addr of env */
#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */
#define CONFIG_ENV_OVERWRITE /* Serial/eth change Ok */
#else
#define CFG_ENV_IS_NOWHERE 1 /* NO Environment */
#endif
/*------------------------------------------------------------------------
* CONSOLE
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_UART_NUMS != 0)
#define CFG_NIOS_CONSOLE CFG_NIOS_CPU_UART0 /* 1st UART is Cons. */
#if (CFG_NIOS_CPU_UART0_BR != 0)
#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */
#define CONFIG_BAUDRATE CFG_NIOS_CPU_UART0_BR
#else
#undef CFG_NIOS_FIXEDBAUD
#define CONFIG_BAUDRATE 115200
#endif
#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
#else
#error *** CFG_ERROR: you have to setup at least one UART in NIOS CPU config
#endif
/*------------------------------------------------------------------------
* TIMER FOR TIMEBASE -- Nios doesn't have the equivalent of ppc PIT,
* so an avalon bus timer is required.
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_TIMER_NUMS != 0)
#if (CFG_NIOS_CPU_TICK_TIMER == 0)
#error *** CFG_ERROR: tick timer at TIMER0 not supported, expand your config.h
#elif (CFG_NIOS_CPU_TICK_TIMER == 1)
#define CFG_NIOS_TMRBASE CFG_NIOS_CPU_TIMER1 /* TIMER1 as tick */
#define CFG_NIOS_TMRIRQ CFG_NIOS_CPU_TIMER1_IRQ
#if (CFG_NIOS_CPU_TIMER1_PER >= CFG_HZ)
#define CFG_NIOS_TMRMS (CFG_NIOS_CPU_TIMER1_PER / CFG_HZ)
#else
#error *** CFG_ERROR: you have to use a timer periode of more than CFG_HZ
#endif
#endif /* CFG_NIOS_CPU_TICK_TIMER */
#else
#error *** CFG_ERROR: you have to setup at least one TIMER in NIOS CPU config
#endif
/*------------------------------------------------------------------------
* Ethernet -- needs work!
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_LAN_NUMS == 1)
#if (CFG_NIOS_CPU_LAN0_TYPE == 0) /* LAN91C111 */
/****************************************************/
/* !!! LAN91C111 works for NIOS with patch only !!! */
/****************************************************/
#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */
#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */
#define CONFIG_SMC91111_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
#define CONFIG_SMC_USE_32_BIT 1
#else /* no */
#undef CONFIG_SMC_USE_32_BIT
#endif
#elif (CFG_NIOS_CPU_LAN0_TYPE == 1) /* CS8900A */
/********************************************/
/* !!! CS8900 is __not__ tested on NIOS !!! */
/********************************************/
#define CONFIG_DRIVER_CS8900 /* Using CS8900 */
#define CS8900_BASE (CFG_NIOS_CPU_LAN0_BASE + CFG_NIOS_CPU_LAN0_OFFS)
#if (CFG_NIOS_CPU_LAN0_BUSW == 32)
#undef CS8900_BUS16
#define CS8900_BUS32 1
#else /* no */
#define CS8900_BUS16 1
#undef CS8900_BUS32
#endif
#else
#error *** CFG_ERROR: invalid LAN0 chip type, check your NIOS CPU config
#endif
#define CONFIG_ETHADDR 08:00:3e:26:0a:5b
#define CONFIG_NETMASK 255.255.255.0
#define CONFIG_IPADDR 192.168.2.21
#define CONFIG_SERVERIP 192.168.2.16
#else
#error *** CFG_ERROR: you have to setup just one LAN only or expand your config.h
#endif
/*------------------------------------------------------------------------
* STATUS LEDs
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_PIO_NUMS != 0)
#if (CFG_NIOS_CPU_LED_PIO == 0)
#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 1)
#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 2)
#define STATUS_LED_BASE CFG_NIOS_CPU_PIO2
#define STATUS_LED_BITS CFG_NIOS_CPU_PIO2_BITS
#define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */
#if (CFG_NIOS_CPU_PIO2_TYPE == 1)
#define STATUS_LED_WRONLY 1
#else
#undef STATUS_LED_WRONLY
#endif
#elif (CFG_NIOS_CPU_LED_PIO == 3)
#error *** CFG_ERROR: status LEDs at PIO3 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 4)
#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 5)
#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 6)
#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 7)
#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 8)
#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
#elif (CFG_NIOS_CPU_LED_PIO == 9)
#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
#else
#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_LED_PIO in right case
#endif
#define CONFIG_STATUS_LED 1 /* enable status led driver */
#define STATUS_LED_BIT (1 << 0) /* LED[0] */
#define STATUS_LED_STATE STATUS_LED_BLINKING
#define STATUS_LED_BOOT_STATE STATUS_LED_OFF
#define STATUS_LED_PERIOD (CFG_HZ / 10) /* ca. 1 Hz */
#define STATUS_LED_BOOT 0 /* boot LED */
#if (STATUS_LED_BITS > 1)
#define STATUS_LED_BIT1 (1 << 1) /* LED[1] */
#define STATUS_LED_STATE1 STATUS_LED_OFF
#define STATUS_LED_PERIOD1 (CFG_HZ / 50) /* ca. 5 Hz */
#define STATUS_LED_RED 1 /* fail LED */
#endif
#if (STATUS_LED_BITS > 2)
#define STATUS_LED_BIT2 (1 << 2) /* LED[2] */
#define STATUS_LED_STATE2 STATUS_LED_OFF
#define STATUS_LED_PERIOD2 (CFG_HZ / 10) /* ca. 1 Hz */
#define STATUS_LED_YELLOW 2 /* info LED */
#endif
#if (STATUS_LED_BITS > 3)
#define STATUS_LED_BIT3 (1 << 3) /* LED[3] */
#define STATUS_LED_STATE3 STATUS_LED_OFF
#define STATUS_LED_PERIOD3 (CFG_HZ / 10) /* ca. 1 Hz */
#define STATUS_LED_GREEN 3 /* info LED */
#endif
#define STATUS_LED_PAR 1 /* makes status_led.h happy */
#endif /* CFG_NIOS_CPU_PIO_NUMS */
/*------------------------------------------------------------------------
* SEVEN SEGMENT LED DISPLAY
*----------------------------------------------------------------------*/
#if (CFG_NIOS_CPU_PIO_NUMS != 0)
#if (CFG_NIOS_CPU_SEVENSEG_PIO == 0)
#error *** CFG_ERROR: status LEDs at PIO0 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 1)
#error *** CFG_ERROR: status LEDs at PIO1 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 2)
#error *** CFG_ERROR: status LEDs at PIO2 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 3)
#define SEVENSEG_BASE CFG_NIOS_CPU_PIO3
#define SEVENSEG_BITS CFG_NIOS_CPU_PIO3_BITS
#define SEVENSEG_ACTIVE 0 /* LED on for bit == 1 */
#if (CFG_NIOS_CPU_PIO3_TYPE == 1)
#define SEVENSEG_WRONLY 1
#else
#undef SEVENSEG_WRONLY
#endif
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 4)
#error *** CFG_ERROR: status LEDs at PIO4 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 5)
#error *** CFG_ERROR: status LEDs at PIO5 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 6)
#error *** CFG_ERROR: status LEDs at PIO6 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 7)
#error *** CFG_ERROR: status LEDs at PIO7 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 8)
#error *** CFG_ERROR: status LEDs at PIO8 not supported, expand your config.h
#elif (CFG_NIOS_CPU_SEVENSEG_PIO == 9)
#error *** CFG_ERROR: status LEDs at PIO9 not supported, expand your config.h
#else
#error *** CFG_ERROR: you have to set CFG_NIOS_CPU_SEVENSEG_PIO in right case
#endif
#define CONFIG_SEVENSEG 1 /* enable seven segment led driver */
/*
* Dual 7-Segment Display pin assignment -- read more in your
* "Nios Development Board Reference Manual"
*
*
* (U8) HI:D[15..8] (U9) LO:D[7..0]
* ______ ______
* | D14 | | D6 |
* | | | |
* D9| |D13 D1| |D5
* |______| |______| ___
* | D8 | | D0 | | A |
* | | | | F|___|B
* D10| |D12 D2| |D4 | G |
* |______| |______| E|___|C
* D11 * D3 * D *
* D15 D7 DP
*
*/
#define SEVENSEG_DIGIT_HI_LO_EQUAL 1 /* high nibble equal low nibble */
#define SEVENSEG_DIGIT_A (1 << 6) /* bit 6 is segment A */
#define SEVENSEG_DIGIT_B (1 << 5) /* bit 5 is segment B */
#define SEVENSEG_DIGIT_C (1 << 4) /* bit 4 is segment C */
#define SEVENSEG_DIGIT_D (1 << 3) /* bit 3 is segment D */
#define SEVENSEG_DIGIT_E (1 << 2) /* bit 2 is segment E */
#define SEVENSEG_DIGIT_F (1 << 1) /* bit 1 is segment F */
#define SEVENSEG_DIGIT_G (1 << 0) /* bit 0 is segment G */
#define SEVENSEG_DIGIT_DP (1 << 7) /* bit 7 is decimal point */
#endif /* CFG_NIOS_CPU_PIO_NUMS */
/*------------------------------------------------------------------------
* COMMANDS
*----------------------------------------------------------------------*/
#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \
CFG_CMD_ASKENV | \
CFG_CMD_BEDBUG | \
CFG_CMD_BMP | \
CFG_CMD_BSP | \
CFG_CMD_CACHE | \
CFG_CMD_DATE | \
CFG_CMD_DOC | \
CFG_CMD_DTT | \
CFG_CMD_EEPROM | \
CFG_CMD_ELF | \
CFG_CMD_FAT | \
CFG_CMD_FDC | \
CFG_CMD_FDOS | \
CFG_CMD_HWFLOW | \
CFG_CMD_IDE | \
CFG_CMD_I2C | \
CFG_CMD_JFFS2 | \
CFG_CMD_KGDB | \
CFG_CMD_NAND | \
CFG_CMD_MMC | \
CFG_CMD_MII | \
CFG_CMD_PCI | \
CFG_CMD_PCMCIA | \
CFG_CMD_SCSI | \
CFG_CMD_SPI | \
CFG_CMD_VFD | \
CFG_CMD_USB ) )
#include <cmd_confdefs.h>
/*------------------------------------------------------------------------
* KGDB
*----------------------------------------------------------------------*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE 9600
#endif
/*------------------------------------------------------------------------
* MISC
*----------------------------------------------------------------------*/
#define CFG_LONGHELP /* undef to save memory */
#define CFG_PROMPT "DK1S10 > " /* Monitor Command Prompt */
#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS 16 /* max number of command args*/
#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
#if (CFG_SRAM_SIZE != 0)
#define CFG_LOAD_ADDR CFG_SRAM_BASE /* Default load address */
#else
#undef CFG_LOAD_ADDR
#endif
#if (CFG_SDRAM_SIZE != 0)
#define CFG_MEMTEST_START CFG_SDRAM_BASE /* SDRAM til stack area */
#define CFG_MEMTEST_END (CFG_INIT_SP - (1024 * 1024)) /* 1MB stack */
#else
#undef CFG_MEMTEST_START
#undef CFG_MEMTEST_END
#endif
#endif /* __CONFIG_H */

48
include/nios-io.h
View File

@ -29,7 +29,7 @@
#define __NIOSIO_H__
/*------------------------------------------------------------------------
* UART
* UART (http://www.altera.com/literature/ds/ds_nios_uart.pdf)
*----------------------------------------------------------------------*/
typedef volatile struct nios_uart_t {
unsigned rxdata; /* Rx data reg */
@ -71,7 +71,7 @@ typedef volatile struct nios_uart_t {
/*------------------------------------------------------------------------
* TIMER
* TIMER (http://www.altera.com/literature/ds/ds_nios_timer.pdf)
*----------------------------------------------------------------------*/
typedef volatile struct nios_timer_t {
unsigned status; /* Timer status reg */
@ -92,4 +92,48 @@ typedef volatile struct nios_timer_t {
#define NIOS_TIMER_START (1 << 2) /* Start timer */
#define NIOS_TIMER_STOP (1 << 3) /* Stop timer */
/*------------------------------------------------------------------------
* PIO (http://www.altera.com/literature/ds/ds_nios_pio.pdf)
*----------------------------------------------------------------------*/
typedef volatile struct nios_pio_t {
unsigned int data; /* Data value at each PIO in/out */
unsigned int direction; /* Data direct. for each PIO bit */
unsigned int interruptmask; /* Per-bit IRQ enable/disable */
unsigned int edgecapture; /* Per-bit sync. edge detect & hold */
}nios_pio_t;
/* direction register */
#define NIOS_PIO_OUT (1) /* PIO bit is output */
#define NIOS_PIO_IN (0) /* PIO bit is input */
/*------------------------------------------------------------------------
* SPI (http://www.altera.com/literature/ds/ds_nios_spi.pdf)
*----------------------------------------------------------------------*/
typedef volatile struct nios_spi_t {
unsigned rxdata; /* Rx data reg */
unsigned txdata; /* Tx data reg */
unsigned status; /* Status reg */
unsigned control; /* Control reg */
unsigned reserved; /* (master only) */
unsigned slaveselect; /* SPI slave selct mask (master only) */
}nios_spi_t;
/* status register */
#define NIOS_SPI_ROE (1 << 3) /* rx overrun */
#define NIOS_SPI_TOE (1 << 4) /* tx overrun */
#define NIOS_SPI_TMT (1 << 5) /* tx empty */
#define NIOS_SPI_TRDY (1 << 6) /* tx ready */
#define NIOS_SPI_RRDY (1 << 7) /* rx ready */
#define NIOS_SPI_E (1 << 8) /* exception */
/* control register */
#define NIOS_SPI_IROE (1 << 3) /* rx overrun int ena */
#define NIOS_SPI_ITOE (1 << 4) /* tx overrun int ena */
#define NIOS_SPI_ITRDY (1 << 6) /* tx ready int ena */
#define NIOS_SPI_IRRDY (1 << 7) /* rx ready int ena */
#define NIOS_SPI_IE (1 << 8) /* exception int ena */
#define NIOS_SPI_SSO (1 << 10) /* override SS_n output */
#endif /* __NIOSIO_H__ */

12
lib_nios/board.c
View File

@ -28,6 +28,9 @@
#include <devices.h>
#include <watchdog.h>
#include <net.h>
#ifdef CONFIG_STATUS_LED
#include <status_led.h>
#endif
/*
@ -159,6 +162,11 @@ void board_init (void)
*/
interrupt_init ();
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING);
#endif
/* main_loop */
for (;;) {
WATCHDOG_RESET ();
@ -171,6 +179,10 @@ void board_init (void)
void hang (void)
{
#ifdef CONFIG_STATUS_LED
status_led_set(STATUS_LED_BOOT, STATUS_LED_OFF);
status_led_set(STATUS_LED_RED, STATUS_LED_BLINKING);
#endif
puts("### ERROR ### Please reset board ###\n");
for (;;);
}