From cb0f4af3ae3abb0ace3c7eb1de6094b2636628cb Mon Sep 17 00:00:00 2001 From: Han Xu Date: Tue, 8 May 2018 21:14:02 -0500 Subject: [PATCH] MLK-18240 imx8qxb0: change the i.MX8QXPB0 NAND iomux settings Set the corrrect NAND IOMXU for i.MX8QXPB0. Signed-off-by: Han Xu (cherry picked from commit ca9b0a95ad428bd3f06c58cdf0cfe41f5fa2190d) --- board/freescale/imx8qxp_arm2/imx8qxp_arm2.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c index a244da7c33..0e3de9f772 100644 --- a/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c +++ b/board/freescale/imx8qxp_arm2/imx8qxp_arm2.c @@ -368,8 +368,8 @@ static iomux_cfg_t gpmi_nand_pads[] = { SC_P_USDHC1_DATA0 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), /* i.MX8QXP NAND use nand_re_dqs_pins */ - SC_P_EMMC0_CMD | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), - SC_P_USDHC1_DATA1 | MUX_MODE_ALT(1) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), + SC_P_USDHC1_VSELECT | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPMI_NAND_PAD_CTRL), };