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* Patch by Stephen Williams, 15 July 2004 

Set the PCI class code for JSE board as part of PCI interface setup

* Patch by Michael Bendzick, 15 Jul 2004:
  Fix problem with writes with odd sizes in drivers/cfi_flash.c when
  CFG_FLASH_USE_BUFFER_WRITE is set
This commit is contained in:
wdenk 2004-09-28 19:00:19 +00:00
parent 66ca92a5ba
commit cce625e557
4 changed files with 16 additions and 5 deletions
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7
CHANGELOG
View File

@ -2,6 +2,13 @@
Changes since U-Boot 1.1.1:
======================================================================
* Patch by Stephen Williams, 15 July 2004
Set the PCI class code for JSE board as part of PCI interface setup
* Patch by Michael Bendzick, 15 Jul 2004:
Fix problem with writes with odd sizes in drivers/cfi_flash.c when
CFG_FLASH_USE_BUFFER_WRITE is set
* Patch by Yuli Barcohen, 13 Jul 2004:
Allow clock setting on MPC866/MPC885 series chips according to
environment variable `cpuclk'

7
board/jse/host_bridge.c
View File

@ -40,9 +40,12 @@ void host_bridge_init (void)
pci_dev_t dev = PCI_BDF (0, 10, 0);
int rc;
u32 val32;
rc = pci_read_config_dword (dev, 0, &val32);
/* Set PCI Class code --
The primary side sees this class code at 0x08 in the
primary config space. This must be something other then a
bridge, or MS Windows starts doing weird stuff to me. */
pci_write_config_dword (dev, 0x48, 0x04800000);
/* Set subsystem ID --
The primary side sees this value at 0x2c. We set it here so

3
drivers/cfi_flash.c
View File

@ -517,6 +517,7 @@ int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
i = buffered_size > cnt ? cnt : buffered_size;
if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
return rc;
i -= (i % info->portwidth);
wp += i;
src += i;
cnt -= i;
@ -1231,5 +1232,5 @@ static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
return retcode;
}
#endif /* CFG_USE_FLASH_BUFFER_WRITE */
#endif /* CFG_FLASH_USE_BUFFER_WRITE */
#endif /* CFG_FLASH_CFI */

4
include/configs/NC650.h
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@ -44,7 +44,7 @@
/*
* 10 MHz - PLL input clock
*/
#define CFG_8xx_OSCCLK 10000000
#define CONFIG_8xx_OSCLK 10000000
/*
* 50 MHz - default CPU clock
@ -62,7 +62,7 @@
#define CFG_8xx_CPUCLK_MAX 133000000
#define CFG_MEASURE_CPUCLK
#define CFG_8XX_XIN CFG_8xx_OSCCLK
#define CFG_8XX_XIN CONFIG_8xx_OSCLK
#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */