MLK-14418-8 imx: mx7dsabresd: add epdc support
Add epdc support from v2016.03. Add a epdc specified DTS file for using epdc Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> (cherry picked from commit ab2f9e136f5da034a8335dc8ca276a54367132e8)
This commit is contained in:
Peng Fan
Ye Li
parent
a9678f1645
commit
ccfa28aec4
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@ -411,7 +411,8 @@ dtb-$(CONFIG_MX6) += imx6ull-14x14-evk.dtb \
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imx6ul-opos6uldev.dtb
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dtb-$(CONFIG_MX7) += imx7-colibri.dtb \
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imx7d-sdb.dtb
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imx7d-sdb.dtb \
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imx7d-sdb-epdc.dtb
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dtb-$(CONFIG_ARCH_MX7ULP) += imx7ulp-evk.dtb
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@ -0,0 +1,9 @@
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "imx7d-sdb.dts"
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#include "imx7d-sdb-epdc.dtsi"
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@ -0,0 +1,54 @@
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/*
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* Copyright (C) 2015 Freescale Semiconductor, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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&epdc {
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status = "okay";
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};
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&fec1 {
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status = "disabled";
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};
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&fec2 {
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status = "disabled";
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};
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&flexcan2 {
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status = "disabled";
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};
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&max17135 {
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status = "okay";
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};
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&sii902x {
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status = "disabled";
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};
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&sim1 {
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status = "disabled";
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};
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&uart5 {
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status = "disabled";
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};
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&i2c3 {
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elan@10 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_epdc_elan_touch>;
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compatible = "elan,elan-touch";
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reg = <0x10>;
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interrupt-parent = <&gpio6>;
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interrupts = <12 IRQ_TYPE_EDGE_FALLING>;
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gpio_elan_cs = <&gpio6 13 0>;
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gpio_elan_rst = <&gpio6 15 0>;
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gpio_intr = <&gpio6 12 0>;
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status = "okay";
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};
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};
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@ -23,6 +23,10 @@
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#include <i2c.h>
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#include <asm/mach-imx/mxc_i2c.h>
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#include <asm/arch/crm_regs.h>
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#if defined(CONFIG_MXC_EPDC)
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#include <lcd.h>
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#include <mxc_epdc_fb.h>
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#endif
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DECLARE_GLOBAL_DATA_PTR;
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@ -47,6 +51,8 @@ DECLARE_GLOBAL_DATA_PTR;
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#define NAND_PAD_READY0_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU5KOHM)
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#define EPDC_PAD_CTRL 0x0
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#ifdef CONFIG_MXC_SPI
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static iomux_v3_cfg_t const ecspi3_pads[] = {
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MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
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@ -328,6 +334,221 @@ int board_qspi_init(void)
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}
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#endif
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#ifdef CONFIG_MXC_EPDC
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iomux_v3_cfg_t const epdc_en_pads[] = {
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MX7D_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(NO_PAD_CTRL),
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};
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static iomux_v3_cfg_t const epdc_enable_pads[] = {
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MX7D_PAD_EPDC_DATA00__EPDC_DATA0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_DATA01__EPDC_DATA1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_DATA02__EPDC_DATA2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_DATA03__EPDC_DATA3 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_DATA04__EPDC_DATA4 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_DATA05__EPDC_DATA5 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_DATA06__EPDC_DATA6 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_DATA07__EPDC_DATA7 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_SDCLK__EPDC_SDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_SDLE__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_SDOE__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_SDSHR__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_SDCE0__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_SDCE1__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_GDCLK__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_GDOE__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_GDRL__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_GDSP__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_BDR0__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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MX7D_PAD_EPDC_BDR1__EPDC_BDR1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),
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};
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static iomux_v3_cfg_t const epdc_disable_pads[] = {
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MX7D_PAD_EPDC_DATA00__GPIO2_IO0,
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MX7D_PAD_EPDC_DATA01__GPIO2_IO1,
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MX7D_PAD_EPDC_DATA02__GPIO2_IO2,
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MX7D_PAD_EPDC_DATA03__GPIO2_IO3,
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MX7D_PAD_EPDC_DATA04__GPIO2_IO4,
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MX7D_PAD_EPDC_DATA05__GPIO2_IO5,
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MX7D_PAD_EPDC_DATA06__GPIO2_IO6,
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MX7D_PAD_EPDC_DATA07__GPIO2_IO7,
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MX7D_PAD_EPDC_SDCLK__GPIO2_IO16,
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MX7D_PAD_EPDC_SDLE__GPIO2_IO17,
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MX7D_PAD_EPDC_SDOE__GPIO2_IO18,
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MX7D_PAD_EPDC_SDSHR__GPIO2_IO19,
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MX7D_PAD_EPDC_SDCE0__GPIO2_IO20,
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MX7D_PAD_EPDC_SDCE1__GPIO2_IO21,
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MX7D_PAD_EPDC_GDCLK__GPIO2_IO24,
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MX7D_PAD_EPDC_GDOE__GPIO2_IO25,
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MX7D_PAD_EPDC_GDRL__GPIO2_IO26,
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MX7D_PAD_EPDC_GDSP__GPIO2_IO27,
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MX7D_PAD_EPDC_BDR0__GPIO2_IO28,
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MX7D_PAD_EPDC_BDR1__GPIO2_IO29,
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};
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vidinfo_t panel_info = {
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.vl_refresh = 85,
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.vl_col = 1024,
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.vl_row = 758,
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.vl_pixclock = 40000000,
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.vl_left_margin = 12,
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.vl_right_margin = 76,
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.vl_upper_margin = 4,
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.vl_lower_margin = 5,
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.vl_hsync = 12,
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.vl_vsync = 2,
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.vl_sync = 0,
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.vl_mode = 0,
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.vl_flag = 0,
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.vl_bpix = 3,
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.cmap = 0,
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};
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struct epdc_timing_params panel_timings = {
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.vscan_holdoff = 4,
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.sdoed_width = 10,
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.sdoed_delay = 20,
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.sdoez_width = 10,
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.sdoez_delay = 20,
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.gdclk_hp_offs = 524,
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.gdsp_offs = 327,
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.gdoe_offs = 0,
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.gdclk_offs = 19,
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.num_ce = 1,
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};
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static void setup_epdc_power(void)
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{
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/* IOMUX_GPR1: bit30: Disable On-chip RAM EPDC Function */
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struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs
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= (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR;
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clrsetbits_le32(&iomuxc_gpr_regs->gpr[1],
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IOMUXC_GPR_GPR1_GPR_ENABLE_OCRAM_EPDC_MASK, 0);
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/* Setup epdc voltage */
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/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
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imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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gpio_request(IMX_GPIO_NR(2, 31), "epdc_pwrstat");
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gpio_direction_input(IMX_GPIO_NR(2, 31));
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/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
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imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* Set as output */
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gpio_request(IMX_GPIO_NR(4, 14), "epdc_vcom");
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gpio_direction_output(IMX_GPIO_NR(4, 14), 1);
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/* EPDC_PWRWAKEUP - GPIO2[23] for EPD PMIC WAKEUP */
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imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* Set as output */
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gpio_request(IMX_GPIO_NR(2, 23), "epdc_pmic");
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gpio_direction_output(IMX_GPIO_NR(2, 23), 1);
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/* EPDC_PWRCTRL0 - GPIO2[30] for EPD PWR CTL0 */
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imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* Set as output */
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gpio_request(IMX_GPIO_NR(2, 30), "epdc_pwr_ctl0");
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gpio_direction_output(IMX_GPIO_NR(2, 30), 1);
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}
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static void epdc_enable_pins(void)
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{
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/* epdc iomux settings */
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imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
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ARRAY_SIZE(epdc_enable_pads));
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}
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static void epdc_disable_pins(void)
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{
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/* Configure MUX settings for EPDC pins to GPIO and drive to 0 */
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imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
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ARRAY_SIZE(epdc_disable_pads));
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}
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static void setup_epdc(void)
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{
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/*** epdc Maxim PMIC settings ***/
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/* EPDC_PWRSTAT - GPIO2[31] for PWR_GOOD status */
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imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_STAT__GPIO2_IO31 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* EPDC_VCOM0 - GPIO4[14] for VCOM control */
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imx_iomux_v3_setup_pad(MX7D_PAD_I2C4_SCL__GPIO4_IO14 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* EPDC_PWRWAKEUP - GPIO4[23] for EPD PMIC WAKEUP */
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imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_SDCE3__GPIO2_IO23 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* EPDC_PWRCTRL0 - GPIO4[20] for EPD PWR CTL0 */
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imx_iomux_v3_setup_pad(MX7D_PAD_EPDC_PWR_COM__GPIO2_IO30 |
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MUX_PAD_CTRL(EPDC_PAD_CTRL));
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/* Set pixel clock rates for EPDC in clock.c */
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panel_info.epdc_data.wv_modes.mode_init = 0;
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panel_info.epdc_data.wv_modes.mode_du = 1;
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panel_info.epdc_data.wv_modes.mode_gc4 = 3;
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panel_info.epdc_data.wv_modes.mode_gc8 = 2;
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panel_info.epdc_data.wv_modes.mode_gc16 = 2;
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panel_info.epdc_data.wv_modes.mode_gc32 = 2;
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panel_info.epdc_data.epdc_timings = panel_timings;
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setup_epdc_power();
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}
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void epdc_power_on(void)
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{
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unsigned int reg;
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struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
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/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
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gpio_set_value(IMX_GPIO_NR(2, 30), 1);
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udelay(1000);
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/* Enable epdc signal pin */
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epdc_enable_pins();
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/* Set PMIC Wakeup to high - enable Display power */
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gpio_set_value(IMX_GPIO_NR(2, 23), 1);
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/* Wait for PWRGOOD == 1 */
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while (1) {
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reg = readl(&gpio_regs->gpio_psr);
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if (!(reg & (1 << 31)))
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break;
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udelay(100);
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}
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/* Enable VCOM */
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gpio_set_value(IMX_GPIO_NR(4, 14), 1);
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udelay(500);
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}
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void epdc_power_off(void)
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{
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/* Set PMIC Wakeup to low - disable Display power */
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gpio_set_value(IMX_GPIO_NR(2, 23), 0);
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/* Disable VCOM */
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gpio_set_value(IMX_GPIO_NR(4, 14), 0);
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epdc_disable_pins();
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/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
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gpio_set_value(IMX_GPIO_NR(2, 30), 0);
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}
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#endif
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int board_early_init_f(void)
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{
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setup_iomux_uart();
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@ -356,6 +577,21 @@ int board_init(void)
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board_qspi_init();
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#endif
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#ifdef CONFIG_MXC_EPDC
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if (mx7sabre_rev() >= BOARD_REV_B) {
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/*
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* On RevB, GPIO1_IO04 is used for ENET2 EN,
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* so set its output to high to isolate the
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* ENET2 signals for EPDC
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*/
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imx_iomux_v3_setup_multiple_pads(epdc_en_pads,
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ARRAY_SIZE(epdc_en_pads));
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gpio_request(IMX_GPIO_NR(1, 4), "epdc_en");
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gpio_direction_output(IMX_GPIO_NR(1, 4), 1);
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}
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setup_epdc();
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#endif
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#ifdef CONFIG_MXC_SPI
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setup_spi();
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#endif
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@ -0,0 +1,76 @@
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CONFIG_ARM=y
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CONFIG_ARCH_MX7=y
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CONFIG_TARGET_MX7DSABRESD=y
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CONFIG_ARMV7_BOOT_SEC_DEFAULT=y
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# CONFIG_ARMV7_VIRT is not set
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CONFIG_IMX_RDC=y
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CONFIG_IMX_BOOTAUX=y
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CONFIG_DEFAULT_DEVICE_TREE="imx7d-sdb"
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CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx7dsabresd/imximage.cfg"
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CONFIG_MXC_EPDC=y
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CONFIG_LCD=y
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CONFIG_BOOTDELAY=3
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# CONFIG_CONSOLE_MUX is not set
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CONFIG_SYS_CONSOLE_IS_IN_ENV=y
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CONFIG_HUSH_PARSER=y
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CONFIG_CMD_BOOTZ=y
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# CONFIG_CMD_IMI is not set
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# CONFIG_CMD_IMLS is not set
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# CONFIG_CMD_XIMG is not set
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# CONFIG_CMD_EXPORTENV is not set
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# CONFIG_CMD_IMPORTENV is not set
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CONFIG_CMD_MEMTEST=y
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CONFIG_CMD_DFU=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_I2C=y
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CONFIG_CMD_MMC=y
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CONFIG_CMD_SF=y
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CONFIG_CMD_USB=y
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CONFIG_CMD_USB_MASS_STORAGE=y
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CONFIG_CMD_NET=y
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CONFIG_CMD_DHCP=y
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CONFIG_CMD_PING=y
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CONFIG_CMD_CACHE=y
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CONFIG_CMD_PMIC=y
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CONFIG_CMD_REGULATOR=y
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CONFIG_CMD_EXT2=y
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CONFIG_CMD_EXT4=y
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CONFIG_CMD_EXT4_WRITE=y
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CONFIG_CMD_FAT=y
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CONFIG_OF_CONTROL=y
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CONFIG_DFU_MMC=y
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CONFIG_DFU_RAM=y
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CONFIG_DM_GPIO=y
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CONFIG_DM_74X164=y
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CONFIG_DM_I2C=y
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CONFIG_DM_MMC=y
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CONFIG_MMC_IO_VOLTAGE=y
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CONFIG_MMC_UHS_SUPPORT=y
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CONFIG_MMC_HS200_SUPPORT=y
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CONFIG_SPI_FLASH=y
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CONFIG_SPI_FLASH_EON=y
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CONFIG_PINCTRL=y
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CONFIG_PINCTRL_IMX7=y
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CONFIG_DM_PMIC=y
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CONFIG_DM_PMIC_PFUZE100=y
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CONFIG_DM_REGULATOR=y
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||||
CONFIG_DM_REGULATOR_PFUZE100=y
|
||||
CONFIG_DM_REGULATOR_FIXED=y
|
||||
CONFIG_DM_REGULATOR_GPIO=y
|
||||
CONFIG_DM_SPI=y
|
||||
CONFIG_SOFT_SPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_DM_USB=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_MXC_USB_OTG_HACTIVE=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_GADGET=y
|
||||
CONFIG_USB_GADGET_MANUFACTURER="FSL"
|
||||
CONFIG_USB_GADGET_VENDOR_NUM=0x0525
|
||||
CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
|
||||
CONFIG_CI_UDC=y
|
||||
CONFIG_USB_GADGET_DOWNLOAD=y
|
||||
CONFIG_USB_HOST_ETHER=y
|
||||
CONFIG_USB_ETHER_ASIX=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_ERRNO_STR=y
|
||||
|
|
@ -20,6 +20,7 @@
|
|||
#define CONFIG_SYS_MALLOC_LEN (32 * SZ_1M)
|
||||
|
||||
/* Network */
|
||||
#ifdef CONFIG_DM_ETH
|
||||
#define CONFIG_FEC_MXC
|
||||
#define CONFIG_MII
|
||||
#define CONFIG_FEC_XCV_TYPE RGMII
|
||||
|
|
@ -38,6 +39,7 @@
|
|||
#endif
|
||||
|
||||
#define CONFIG_FEC_MXC_MDIO_BASE ENET_IPS_BASE_ADDR
|
||||
#endif
|
||||
|
||||
/* MMC Config*/
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR 0
|
||||
|
|
@ -236,6 +238,31 @@
|
|||
#define CONFIG_VIDEO_BMP_LOGO
|
||||
#endif
|
||||
|
||||
/* #define CONFIG_SPLASH_SCREEN*/
|
||||
/* #define CONFIG_MXC_EPDC*/
|
||||
|
||||
/*
|
||||
* SPLASH SCREEN Configs
|
||||
*/
|
||||
#if defined(CONFIG_SPLASH_SCREEN) && defined(CONFIG_MXC_EPDC)
|
||||
/*
|
||||
* Framebuffer and LCD
|
||||
*/
|
||||
#define CONFIG_CMD_BMP
|
||||
#define CONFIG_LCD
|
||||
|
||||
#undef LCD_TEST_PATTERN
|
||||
/* #define CONFIG_SPLASH_IS_IN_MMC 1 */
|
||||
#define LCD_BPP LCD_MONOCHROME
|
||||
/* #define CONFIG_SPLASH_SCREEN_ALIGN 1 */
|
||||
|
||||
#define CONFIG_WAVEFORM_BUF_SIZE 0x400000
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_MXC_EPDC) && defined(CONFIG_SYS_USE_QSPI)
|
||||
#error "EPDC Pins conflicts QSPI, Either EPDC or QSPI can be enabled!"
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FSL_QSPI
|
||||
#define CONFIG_SPI_FLASH
|
||||
#define CONFIG_SPI_FLASH_MACRONIX
|
||||
|
|
|
|||
Loading…
Reference in New Issue