LM
/
u-boot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

m68k: move dspi bus control functions into cf_spi.c driver 

This patches move dspi bus-related operations into more
proper location, to avoid the driver to declares them as externs.

Signed-off-by: Angelo Dureghello <angelo@sysam.it>
This commit is contained in:
Angelo Dureghello 2019-03-13 21:46:52 +01:00 committed by Tom Rini
parent abe0f87999
commit cd3b0717ba
2 changed files with 41 additions and 166 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

65
arch/m68k/cpu/mcf5227x/cpu_init.c
View File

@ -16,6 +16,15 @@
#include <asm/rtc.h>
#include <linux/compiler.h>
void cfspi_port_conf(void)
{
gpio_t *gpio = (gpio_t *)MMAP_GPIO;
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
}
/*
* Breath some life into the CPU...
*
@ -93,6 +102,8 @@ void cpu_init_f(void)
#endif
icache_enable();
cfspi_port_conf();
}
/*
@ -137,57 +148,3 @@ void uart_port_conf(int port)
break;
}
}
#ifdef CONFIG_CF_DSPI
void cfspi_port_conf(void)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN | GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
}
int cfspi_claim_bus(uint bus, uint cs)
{
dspi_t *dspi = (dspi_t *) MMAP_DSPI;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
return -1;
/* Clear FIFO and resume transfer */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_UNMASK);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 2:
clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
setbits_8(&gpio->par_timer, GPIO_PAR_TIMER_T2IN_DSPIPCS2);
break;
}
return 0;
}
void cfspi_release_bus(uint bus, uint cs)
{
dspi_t *dspi = (dspi_t *) MMAP_DSPI;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Clear FIFO */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 2:
clrbits_8(&gpio->par_timer, ~GPIO_PAR_TIMER_T2IN_UNMASK);
break;
}
}
#endif

142
arch/m68k/cpu/mcf5445x/cpu_init.c
View File

@ -66,6 +66,32 @@ void init_fbcs(void)
#endif
}
#ifdef CONFIG_CF_DSPI
void cfspi_port_conf(void)
{
gpio_t *gpio = (gpio_t *)MMAP_GPIO;
#ifdef CONFIG_MCF5445x
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN |
GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
#endif
#ifdef CONFIG_MCF5441x
pm_t *pm = (pm_t *)MMAP_PM;
out_8(&gpio->par_dspi0,
GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
GPIO_PAR_DSPI0_SCK_DSPI0SCK);
out_8(&gpio->srcr_dspiow, 3);
/* DSPI0 */
out_8(&pm->pmcr0, 23);
#endif
}
#endif
/*
* Breath some life into the CPU...
*
@ -204,6 +230,10 @@ void cpu_init_f(void)
GPIO_PAR_FBCTL_OE | GPIO_PAR_FBCTL_TA_TA |
GPIO_PAR_FBCTL_RW_RW | GPIO_PAR_FBCTL_TS_TS);
#ifdef CONFIG_CF_SPI
cfspi_port_conf();
#endif
#ifdef CONFIG_SYS_FSL_I2C
out_be16(&gpio->par_feci2c,
GPIO_PAR_FECI2C_SCL_SCL | GPIO_PAR_FECI2C_SDA_SDA);
@ -433,115 +463,3 @@ int fecpin_setclear(struct eth_device *dev, int setclear)
}
#endif
#ifdef CONFIG_CF_DSPI
void cfspi_port_conf(void)
{
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
#ifdef CONFIG_MCF5445x
out_8(&gpio->par_dspi,
GPIO_PAR_DSPI_SIN_SIN |
GPIO_PAR_DSPI_SOUT_SOUT |
GPIO_PAR_DSPI_SCK_SCK);
#endif
#ifdef CONFIG_MCF5441x
pm_t *pm = (pm_t *) MMAP_PM;
out_8(&gpio->par_dspi0,
GPIO_PAR_DSPI0_SIN_DSPI0SIN | GPIO_PAR_DSPI0_SOUT_DSPI0SOUT |
GPIO_PAR_DSPI0_SCK_DSPI0SCK);
out_8(&gpio->srcr_dspiow, 3);
/* DSPI0 */
out_8(&pm->pmcr0, 23);
#endif
}
int cfspi_claim_bus(uint bus, uint cs)
{
dspi_t *dspi = (dspi_t *) MMAP_DSPI;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
if ((in_be32(&dspi->sr) & DSPI_SR_TXRXS) != DSPI_SR_TXRXS)
return -1;
/* Clear FIFO and resume transfer */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 1:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
break;
case 2:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
break;
case 3:
clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
setbits_8(&gpio->par_dma, GPIO_PAR_DMA_DACK0_PCS3);
break;
case 5:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
setbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
#endif
#ifdef CONFIG_MCF5441x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi0, ~GPIO_PAR_DSPI0_PCS0_MASK);
setbits_8(&gpio->par_dspi0, GPIO_PAR_DSPI0_PCS0_DSPI0PCS0);
break;
case 1:
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
setbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
break;
}
#endif
return 0;
}
void cfspi_release_bus(uint bus, uint cs)
{
dspi_t *dspi = (dspi_t *) MMAP_DSPI;
gpio_t *gpio = (gpio_t *) MMAP_GPIO;
/* Clear FIFO */
clrbits_be32(&dspi->mcr, DSPI_MCR_CTXF | DSPI_MCR_CRXF);
#ifdef CONFIG_MCF5445x
switch (cs) {
case 0:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS0_PCS0);
break;
case 1:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS1_PCS1);
break;
case 2:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS2_PCS2);
break;
case 3:
clrbits_8(&gpio->par_dma, ~GPIO_PAR_DMA_DACK0_UNMASK);
break;
case 5:
clrbits_8(&gpio->par_dspi, GPIO_PAR_DSPI_PCS5_PCS5);
break;
}
#endif
#ifdef CONFIG_MCF5441x
if (cs == 1)
clrbits_8(&gpio->par_dspiow, GPIO_PAR_DSPIOW_DSPI0PSC1);
#endif
}
#endif