tegra: clock: Adjust PLL access to avoid a warning
A harmless but confusing warning is displayed when looking up the DisplayPort PLL. Correct this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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					@ -84,7 +84,7 @@ static struct clk_pll *get_pll(enum clock_id clkid)
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	assert(clock_id_is_pll(clkid));
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						assert(clock_id_is_pll(clkid));
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	if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
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						if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
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		debug("%s: Invalid PLL\n", __func__);
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							debug("%s: Invalid PLL %d\n", __func__, clkid);
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		return NULL;
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							return NULL;
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	}
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						}
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	return &clkrst->crc_pll[clkid];
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						return &clkrst->crc_pll[clkid];
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					@ -120,9 +120,12 @@ int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
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					unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
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		u32 divp, u32 cpcon, u32 lfcon)
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							u32 divp, u32 cpcon, u32 lfcon)
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{
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					{
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	struct clk_pll *pll = get_pll(clkid);
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						struct clk_pll *pll = NULL;
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	u32 misc_data, data;
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						u32 misc_data, data;
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						if (clkid < (enum clock_id)TEGRA_CLK_PLLS)
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							pll = get_pll(clkid);
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	/*
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						/*
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	 * We cheat by treating all PLL (except PLLU) in the same fashion.
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						 * We cheat by treating all PLL (except PLLU) in the same fashion.
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	 * This works only because:
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						 * This works only because:
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